TQ5121 [TRIQUINT]
3V Cellular TDMA/AMPS LNA/mixer Receiver IC; 3V蜂窝TDMA / AMPS LNA /混频器接收器IC
| 型号： | TQ5121 |
| 厂家： | 
TRIQUINT SEMICONDUCTOR |
| 描述： | 3V Cellular TDMA/AMPS LNA/mixer Receiver IC |
| 文件： | 总10页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WIRELESS COMMUNICATIONS DIVISION
TQ5121
DATA SHEET
Optional
GND
16
1
2
N/C
N/C
15 N/C
Mixer IF/
Vdd
14
Vdd MXR
MXR LO
3
4
3V Cellular TDMA/AMPS
LNA/mixer Receiver IC
13
12
11
10
9
GND
5
6
MXR RF
GND
VDD LNA
GND
LNA
Out
7
8
RF IN
GND
N/C
Features
§ Pin compatible with TQ9222
(dual-band TDMA receiver)
§ Single 3V operation
§ Low-current operation
§ 50 W matched inputs
§ QSOP-16 plastic package
Product Description
The TQ5121 is a 3V, RF receiver IC designed specifically for Cellular band TDMA
applications. It’s RF performance meets the requirements of products designed to
the IS-136 and AMPS standards. The TQ5121 is pin compatible with TQ9222, which
enables handset designers to use strategic board platform strategy. The TQ5121
contains LNA+Mixer circuits to handle the 800MHz cellular band.
The mixer uses a high-side LO frequency, with the IF covering a range of 70 to
140MHz. Most RF ports are internally matched to 50 W, greatly simplifying the
design and keeping the number of external components to a minimum. The TQ5121
achieves good RF performance with low current consumption, supporting long
standby times in portable applications. Coupled with the very small QSOP-16
package, the part is ideally suited for Cellular band mobile phones.
Applications
§ IS-136 Mobile Phones
§ AMPS Mobile Phones
§ ISM 900MHz
Electrical Specifications1
Parameter
Min
869
Typ
Max
894
Units
MHz
dB
Frequency
Gain
17.5
2.7
Noise Figure
Input 3rd Order Intercept
DC supply Current
dB
-8.5
10.0
dBm
mA
Note 1: Test Conditions: Vdd=2.8V, Ta=25C, filter IL=2.5dB, RF=881MHz, LO=991MHz, IF=110MHz,
LO input=-7dBm
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1
TQ5121
Data Sheet
Electrical Characteristics
Parameter
Conditions
Min.
869
950
70
Typ/Nom
Max.
894
1040
140
0
Units
RF Frequency
LO Frequency
IF Frequency
LO input level
Supply voltage
Gain
Cellular band
Cellular band
Cellular band
MHz
MHz
MHz
dBm
V
-7
-4
2.7
16.0
-2.0
2.8
4.0
17.5
dB
Gain Variation vs. Temp.
Noise Figure
-40 to 85C
+2.0
3.5
dB
2.7
dB
Input 3rd Order Intercept
Return Loss
-11.0
10
-8.5
dBm
dB
LNA input – external match
LNA output
10
dB
Mixer RF input
10
dB
Mixer LO input
10
dB
Isolation
LO to LNA in
40
dB
LO to IF; after IF match
RF to IF; after IF match
Vdd = 2.8V; “ON”
Vdd = 0V; “OFF”
40
40
dB
dB
IF Output Impedance
500
<50
10
Ohm
Ohm
mA
C
Supply Current
Temperature
13
85
-40
25
Note 1: Test Conditions: Vdd=2.8V, filter IL=2.5dB, RF=881MHz, LO=991MHz, IF=110MHz, LO input=-7dBm, TC = 25° C, unless otherwise specified.
Absolute Maximum Ratings
Parameter
Value
5.0
Units
V
DC Power Supply
Power Dissipation
500
mW
C
Operating Temperature
Storage Temperature
Signal level on inputs/outputs
Voltage to any non supply pin
-55 to 100
-60 to 150
+20
C
dBm
V
+.3
2
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TQ5121
Data Sheet
Typical Performance
Test Conditions
(Unless Otherwise Specified): Vdd=2.8V, Ta=25C, filter IL=2.5dB, RF=881MHz, LO=991MHz, IF=110MHz, LO input=-7dBm
IIP3 vs. Vdd vs. Temp
CG vs. Freq vs. Temp
20
19
18
17
16
15
14
13
12
11
10
-6
-7
-8
-9
-10
-11
-12
-13
-14
-40C
+25C
+85C
-40C
+25C
+85C
869 872 875 878 881 884 887 890 893
Freq (MHz)
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
Vdd (volts)
CG vs. Temp vs. Vdd
20
IIP3 vs. Temp vs. Vdd
-7
-7.5
-8
19.5
Vdd=2.7v
Vdd=2.8v
Vdd=3.0v
19
18.5
18
-8.5
-9
17.5
17
-9.5
-10
Vdd=2.7
Vdd=2.8
Vdd=3.0
16.5
16
-10.5
-11
15.5
15
-40
25
85
-40
25
85
Temp C
Temp C
CG vs. Vdd vs. Temp
Noise Figure vs. Freq vs. Temp
20
18
16
14
12
10
4
3.75
3.5
3.25
3
-40C
+25C
+85C
+25C
-40C
+85C
2.75
2.5
2.25
2
869 872 875 878 881 884 887 890 893
Freq (MHz)
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
Vdd (volts)
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3
TQ5121
Data Sheet
Application/Test Circuit
16
1
2
N/C
N/C
15 N/C
Mixer IF
800
C4
L2
Vdd MXR
800
14
13
3
4
C6
MXR LO
800
L3
C3
Vdd
MXR
VDD LNA
800
C5
5
6
12
11
C2
Band
Pass
Filter
C1
RF IN
800
10
7
8
Lx
9
N/C
L1
Bill of Material for TQ5121 Receiver Application/Test Circuit
Component
Receiver IC
Capacitor
Capacitor
Capacitor
Capacitor
Reference Designator
Part Number
TQ5121
Value
1.2pF
Size
Manufacturer
TriQuint Semiconductor
U1
C1
QSOP-16
0402
C2, C3
C4
1000pF
10pF
0402
0402
C5
0402
.01mF
8.2 pF
10nH
Capacitor
Inductor
C6
0402
L1, L2
0402
Inductor
L3
Lx (filter dependent)
F1
180nH
10nH
0402
Inductor
0602
Toyocom (select)
T726881A
627-881A
Toyocom
4
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TQ5121
Data Sheet
Fig 2. Suggested LNA Input Match
1.2pF
TQ5121 Product Description
The TQ5121 3V RFIC Downconverter is designed specifically
for cellular band TDMA applications. The TQ5121 contains a
LNA+Mixer circuit to handle the 800 MHz cellular band. The IF
frequency range covers 70 to 140 MHz with most of the ports
internally matched to 50 W simplifying the design and keeping
the number of external components to a minimum.
RF
IN
Pin 7
10nH
Note: These values assume ideal components and neglect board parasitic.
The discrepancy between these values and those of the typical application
circuit are the board and component parasitic
presented to the input pin. Highest gain and lowest return loss
Operation
occur when G is equal to the complex conjugate of the LNA
s
Please refer to the test circuit above.
input impedance. A different source reflection coefficient, G ,
opt
Low Noise Amplifier (LNA)
which is experimentally determined, will provide the lowest
possible noise figure, Fmin
.
The LNA section of the TQ5121 consists of a cascaded
common source FETs (see Fig 1). The LNA is designed to
operate on supply voltages from 3V to 5V. The source terminal
has to be grounded very close to the pin, this will avoid a
significant gain reduction due to degeneration. The LNA
requires a matching circuit on the input to provide superior
noise, gain and return loss performance. The output is close to
50 W for direct connection to a 50 W image stripping filter.
The noise resistance, Rn, provides an indication of the sensitivity
of the noise performance to changes in G as seen by the LNA
s
input.
2
4R
N
G
opt - G
S
FLNA = FMIN
+
×
1+ Gopt 2 × 1- Gs 2
Z
0
(
)
Components such as filters and mixers placed after the LNA
degrade the overall system noise figure according to the
following equation:
Vdd
Fig 1. TQ5121
Simplified
LOAD
F
2
- 1
Schematic of
LNA Section
F
SYSTEM = FLNA +
LNA
out
G
LNA
FLNA and GLNA represent the linear noise factor and gain of the
LNA and F2 is the noise factor of the next stage. Thus, the
system noise figure depends on the highest gain and minimum
noise figure of the LNA.
LNA
in
BIAS
BIAS
LNA Input Match
To obtain the best possible combination of performance and
flexibility, the LNA was designed to be used with off-chip
impedance matching on the input. Based on the system
requirements, the designer can make several performance
trade-offs and select the best impedance match for the
particular application.
Designing the input matching network involves a compromise
between optimum noise performance and best input return loss.
For example, when the TQ5121 LNA is matched for optimum
noise figure (1.35dB @ 880 MHz), the input return loss is
approximately 4dB. On the other hand, when the LNA is
matched for best return loss, the LNA noise figure is
approximately 1.95dB @ 881 MHz. See Table 1 for noise
parameters.
The input matching network primarily determines the noise and
gain performance. Fig 2 shows a suggested input match using
a series 1.2pF capacitor and a shunt 10nH inductor.
The LNA gain, noise figure and input return loss are a function
of the source impedance (Zs), or reflection coefficient (G ),
s
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5
TQ5121
Data Sheet
flexibility in matching to various IF frequencies and filter
impedance’s. See Figure 3.
Table 1. TQ5121 Noise Parameters
Freq
(MHz)
835
850
865
880
895
910
925
| opt|
G
< opt
G
Fmin
(dB)
1.34
1.38
1.36
1.35
1.36
1.35
1.35
Rn
(W)
Mixer: LO Port
0.678
0.655
0.652
0.652
0.649
0.659
0.687
33
34
36
38
38
40
41
61.6
61.1
61.2
60.9
61.3
61.2
65.6
As mentioned earlier, a common gate buffer amplifier is
positioned between the LO port and the mixer FET gate in order
to provide a good impedance to the VCO and to allow operation
at lower LO drive levels. The buffer amplifier provides the
voltage gain needed to drive the gate of the mixer FET while
consuming very little current (approximately 1.5mA).
Because of the broadband 50W input impedance of the buffer
amplifier and the internal DC blocking capacitor, the user’s VCO
can be directly connected to the LO input via a 50W line with no
additional components.
LNA Output Match
The output impedance of the LNA was designed to interface
directly with 50W terminations. This internal match serves to
reduce the number of external components required at this port.
An additional benefit accrues as an improvement in IP3
performance, return loss and power gain.
Mixer Input
Although the mixer input port has been designed with a
50W impedance, it has been found that LO leakage out through
the pin, can in some cases, reflect off the SAW filter and travel
back to the mixer input out of phase, causing some degradation
in conversion gain and system noise figure. Sensitivity to the
phenomena depends on the particular filter model and SAW-
mixer transmission line length.
The output of the LNA will most often be connected to an image
stripping filter. Depending on the filter type, additional
components might be needed to present a better match to the
LNA output. The TQ5121 general applications circuit (page 4)
shows a TOYOCOM (637-881A) saw filter. A series inductor
“Lx” of 10nH is added to the filter input to improve the match.
This series inductor also smoothes out excessive ripple in the
filter passband improving the overall performance of the circuit.
LO Buffer Tune
While the broadband input match of the LO buffer amplifier
makes interfacing easy, the broadband gain means that thermal
and induced noise at other frequencies can be amplified and
injected directly into the LO port of the mixer. Noise at the IF
frequency, and at LO +/- IF will be downconverted and emerge
at the IF port, degrading the downconverter noise figure.
Mixer
The mixer of the TQ5121 is implemented by a common source
depletion FET. The mixer is designed to operate on supply
voltages from 3V to 5V. An on-chip buffer amplifier simplifies
direct connection of the LO input to a commercial VCO at drive
levels down to -7dBm. The common-gate LO buffer provides a
good input match, and supplies the voltage gain necessary to
drive the mixer FET gate. The "open-drain " IF output allows for
As indicated on the diagram of Fig 4, in order to test the LO
response to these spurious signals, a two-tone signal was
injected into the LO port with the RF port terminated in 50W.
One signal generator is set to the LO frequency at its normal LO
drive level usually (-7 dBm). The second signal generator
(spurious signal) is set to the LO +/- the IF frequency. The
combined input power at mixer LO port has to be less than -50
dBm. The results shown in Table 3 indicate a good suppression
of the interfering signals.
Fig 3. Mixer Section
Mixer RF
Mixer IF
Output
Input
LO Bias and
Tuning
Mixer LO
Input
6
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TQ5121
Data Sheet
Measuring the LO Frequency Response
Fig 4. LO Spurious Response Diagram
The frequency response of the LO driver amplifier can be
measured using a semi-rigid probe (see Fig. 5) and a network
analyzer.
TQ5121
Mixer
Spectrum
Analyzer
RF
IF
Connect port 1 to the LO input (Pin 4) of the TQ5121 with the
source power set to deliver -7 dBm. Connect the coaxial probe
to Port 2 and place the probe tip approximately 0.1 inch away
from either Pin 3 or the inductor.
50 W
LO
Directional
Coupler
+
SIG 1:
flo
Fig 5. LO Buffer Frequency
Response
SIG 2:
flo +/- IF
Network
Analyzer
Port 2
Port 1
Table 3. LO Spurious Response Data
LO/Spurious Mixer LO Port
3
4
C/V
(dB)
Probe
TQ5121
(MHz)
Input Power
-57
991/1101
991/1101
-71.7
-71.8
-30
-32
-34
-36
-38
-40
-42
-58.9
Calculation of Nominal L Value
700 800 900 1000 1100 1200
Frequency (MHz)
The node between the LO buffer amplifier and the mixer FET is
brought out to Pin 3 (L_tune) and connected to a shunt inductor
to AC ground. This inductor is selected to resonate with internal
capacitance at the LO frequency in order to suppress out-of-
band gain and improve noise performance.
If the calculated shunt inductor (L2) is not a standard value, the
AC ground, implemented with C3, can be slide along the
transmission line to adjust for the right inductance (fig 6). Once
this is completed, the peak of the response should be centered
at the center of the LO frequency band.
The internal capacitance of the LO amplifier output plus the
stray capacitance on the board surrounding Pin 3 is
approximately 1.8 pF. The inductor is selected to resonate with
the total capacitance at the LO frequency using the following
equation:
Fig 6. Adjusting the
AC Ground
Ground
1
L
=
, where× C = 1.5pF
2
)
C 2P f
(
3
Placement of inductor
will adjust between
standard values
Must be confirmed with measurements on a board
approximating the final layout.
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7
TQ5121
Data Sheet
Mixer IF Port
The Mixer IF output is an "open-drain" configuration, allowing for
flexibility in efficient matching to various filter types and at
various IF frequencies.
For evaluation of the LNA and mixer, it is usually necessary to
impedance match the IF port to the 50W test systems. When
verifying or adjusting the matching circuit on the prototype circuit
board, the LO drive should be injected at pin 4 at the nominal
power level of -7 dBm, since the LO level does have an impact
on the IF port impedance.
There are several networks that can be used to properly match
the IF port to the SAW or crystal IF filter. The mixer supply
voltage is applied through the IF port, so the matching circuit
topology must contain either an RF choke or shunt inductor. An
extra DC blocking capacitor is not necessary if the output will be
attached directly to a SAW or crystal bandpass filters.
Figure 7 shows the IF matching network, A shunt L, series C,
shunt C, is the simplest and requires the fewest components.
DC current can be easily injected through the shunt inductor and
the series C provides a DC block, if needed. The shunt C, is
used to reduce the LO leakage.
Fig 7. IF Output Match (110MHz)
10pF
Mx IF
Pin 14
out
8.2pF
180nH
Vdd
0.01uF
10W
Note: These values assume ideal components and neglect board parasitics.
The discrepancy between these values and those of the typical application
circuit are the board and component parasitics
8
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TQ5121
Data Sheet
Package Pinout
Optional
GND
16
1
2
N/C
N/C
15 N/C
Mixer IF/
Vdd
14
Vdd MXR
MXR LO
3
4
13
12
11
10
9
GND
5
6
MXR RF
GND
VDD LNA
GND
LNA
Out
7
8
RF IN
GND
N/C
Pin Descriptions
Pin Name
N/C
Pin #
Description and Usage
No Connection
1
2
N/C
No Connection
VDD_MXR
MXR_LO
3
Mixer LO buffer supply voltage. Local bypass capacitor required.
Mixer LO input. DC blocked, matched to 50W
LNA supply voltage. Local bypass capacitor required.
Ground
4
VDD_LNA
GND
5
6
LNA_IN
GND_LNA
N/C
7
LNA input. DC blocked. Requires external matching elements for noise match and match to 50W
8
LNA first stage ground connection. Connection to ground.
9
No connection
LNA_OUT
GND
10
11
12
13
14
15
16
LNA output. DC blocked. Matched to 50W.
Ground
MXR_RF
GND
Mixer RF input, DC blocked. Matched to 50W.
Ground
MXR_IF
N/C
Mixer IF output. Open drain output, connection to Vdd required. External matching is required.
No connection
Optional
GND
Optional ground
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9
TQ5121
Data Sheet
Package Type: Power QSOP-16 Plastic Package
D
NOTE A
E
E1
NOTE B
b
c
A
q
A1
e
L
DESIGNATION
DESCRIPTION
OVERALL HEIGHT
STANDOFF
ENGLISH
METRIC
+/-.13 mm
NOTE
C
C
C
C
A
A1
b
c
D
e
E
E1
L
0.064 +/-.005 in
0.007 +/-.003 in
0.010 +/-.002 in
0.085 +/-.015 in
0.193 +/-.004 in
1.63
0.18
0.25
2.16
4.90
0.635
5.99
3.91
0.84
4
+/-.08 mm
+/-.05 mm
+/-.38 mm
+/-.10 mm
BSC
+/-.20 mm
+/-.08 mm
+/-.43 mm
+/-4 DEG
LEAD WIDTH
LEAD THICKNESS
PACKAGE LENGTH
LEAD PITCH
LEAD TIP SPAN
PACKAGE WIDTH
FOOT LENGTH
FOOT ANGLE
A, C
0.025
BSC
0.236 +/-.008 in
0.154 +/-.003 in
0.033 +/-.017 in
C
B, C
C
4
+/-4 DEG
q
NOTES:
A. THE D DIMENSION DOES NOT INCLUDE MOLD FLASHING AND MISMATCH. MOLD FLASHING AND MISMATCH SHALL NOT EXCEED .006 in (.15 mm)
PER SIDE.
B. THE E1 DIMENSION DOES NOT INCLUDE MOLD FLASHING AND MISMATCH. MOLD FLASHING AND MISMATCH SHALL NOT EXCEED .010 in (.25 mm)
PER SIDE.
C. PRIMARY UNITS ARE ENGLISH INCHES. THE METRIC EQUIVALENTS ARE SUBJECT TO ROUNDING ERROR.
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Tel: (503) 615-9000
Fax: (503) 615-8900
Email: info_wireless@tqs.com
For technical questions and additional information on specific applications:
Email: info_wireless@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of
this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1998 TriQuint Semiconductor, Inc. All rights reserved.
Revision C, August 6, 1999
10
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