TQPED [TRIQUINT]

Precision, 100UA Gain Selectable Amplifier; 精密， 100uA的可选增益放大器


型号：	TQPED
厂家：	TRIQUINT SEMICONDUCTOR
描述：	Precision, 100UA Gain Selectable Amplifier 精密， 100uA的可选增益放大器放大器
文件：	总3页 (文件大小：100K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Pre-Production Process

TQPED

0.5 um E/D pHEMT Foundry Service

Features

• E-Mode, 0.35 V, Vth

Metal 2 - 4um

• D-Mode, -0.8 V Vp

• InGaAs Active Layer pHEMT

Process

Metal 2

Metal 1

Dielectric

Metal 1

Dielectric

• 0.5 um Optical Lithography

Gates

• High Density Interconnects:

Metal 1 - 2um

Dielectric

NiCr

MIM Metal

•

2 Global

1 Local

Metal 0

Nitride

•

Isolation Implant

• High-Q Passives

N+

Pseudomorphic

Channel

• Thin Film Resistors

• High Value Capacitors

• Backside Vias Optional

• Based on Production TQPHT

pHEMT and Interconnect

• Nominal TOM3 FET Models

Available

MIM Capacitor

NiCr Resistor

E-Mode / D-Mode

pHEMT

Semi-Insulating GaAs Substrate

0.5 um pHEMT Device Cross-Section

General Description

Applications

TriQuint’s TQPED process is based on our production-released

0.5 µm TQPHT process. TQPED partners an E-Mode pHEMT

device with our TQPHT D-Mode transistors to be the first

foundry pHEMT process to integrate E-Mode and D-Mode tran-

sistors on the same wafer. This process is targeted for low noise

amplifiers, linear, low loss and high isolation RF switch applica-

tions, converters and integrated RF Front Ends. The TQPED

process offers a D-Mode pHEMT with a –0.8 V pinch off, and an

E-Mode pHEMT with a +0.35 V threshold voltage. The three

metal interconnecting layers are encapsulated in a high perform-

ance dielectric that allows wiring flexibility, optimized die size

and plastic packaging simplicity. Precision NiCr resistors and

high value MIM capacitors are included allowing higher levels of

integration, while maintaining smaller, cost –effective die sizes.

• Highly Efficient, and Linear

Power Amplifiers

• Low Loss, High Isolation, Low-

Harmonic Contnt Switches

• Integrated digital control logic

for Switches and Transceivers

• Converters

• Integrated RF Front Ends– LNA,

SW, PA

• Wireless Transceivers, Base sta-

tions, Direct Broadcast Satellite

Radars, Digital Radios, RF /

Mixed Signal ICs

• Power Detectors and Couplers

Production Release: Q1’2005

Page 1 of 3; Rev 1.0 12/1/2004

Pre-Production Process

TQPED

0.5 um E/D pHEMT Foundry Service

Process Details @ Vds = 3.0V

TQPED

Process

Details

Element

Parameter

Vp (1uA/um)

Idss

Value

Units

D-Mode pHEMT

-0.8

225

mA/mm

Imax

550

Breakdown, Vdg

Ft @ 50% Idss

Fmax @ 50% Idss

Gm (50% Idss)

Ron

15 min, 20 typ

GHz

350

mS/mm

Ohms * mm

1.5

E-Mode pHEMT

Vth (1uA/um)

Idss

+0.35

0.1

uA/um

mA/mm

Imax

310

Breakdown, Vdg

Ft @ 50% Idss

Fmax @ 50% Idss

Gm (50% Idss)

Ron

15 min, 18 typ

100

625

2.5

GHz

mS/mm

Ohms * mm

Common Process Element Details

Gate Length

Interconnect

MIM Caps

0.5

µm

Metal Layers

pF/mm2

Value

NiCr

Bulk

630

Resistors

Ohms/sq

285

Storage Temperature Range

Operating Temperature Range

-65 to +150

-55 to +150

Deg C

Maximum

Ratings

EFET/DFET Transistor

(Vs open; Idg = 1uA/um)

Capacitor

Semiconductors for Communications

TriQuint Semiconductor

2300 NE Brookwood Pkwy

Hillsboro, Oregon 97124

Phone: 503-615-9000

Fax: 503-615-8905

Email: info@triquint.com

www.triquint.com

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Pre-Production Process

TQPED

0.5 um E/D pHEMT Foundry Service

Prototyping and Development

Process Qualification Status

• Mature process based on TQPHT 150-mm process

• Process release to production scheduled for Q1 2005

• Full 150mm wafer Process Qualification in process. To

be completed early Q1 2005

• Prototype Development Quick Turn (PDQ):

•

Shared mask set

Run monthly

Hot Lot cycle time

• For more information on Quality and Reliability, contact

• Prototype Wafer Option (PWO):

TriQuint or visit: www.triquint.com/manufacturing/QR/

•

Customer-specific masks; Customer schedule

2 wafers delivered

Hot Lot cycle time

With thinning and sawing; optional backside vias

Applications Support Services

• Tiling of GDSII stream files including PCM

• Design Rule Check services

• Layout Versus Schematic check services

• Packaging Development Engineering

• Test Development Engineering:

• On-wafer

Design Tool Status

• Complete Design Manual Now

• Device Library of circuit elements: FETs, diodes, thin film

resistors, capacitors, inductors

• Design Kit for Agilent’s ADS design environment

• Design Kit planned for AWR Microwave Office

• Layout Library in GSD II format

• Packaged parts

• Thermal Analysis Engineering

• Yield Enhancement Engineering

• Part Qualification Services

• Cadence Development Kit with PCells in Preliminary

Release

• Layout Rule Sets for Design Rule Check for ICED, Ca-

dence

• Failure Analysis

• Qualified package models for supported package styles

• Noise parameters on specific device sizes available

Manufacturing Services

• Mask making

• Production 150-mm wafer fab

• Wafer Thinning

• Wafer Sawing

Training

• GaAs Design Classes:

•

Half-Day Introduction; Upon request

Four-Day Technical Training; Fall and Spring at

TriQuint Oregon facility

• Substrate Vias

• DC Diesort Testing

• RF On-wafer testing

• Plastic Packaging

• For Training & PDQ Schedules, please visit:

www.triquint.com/foundry/

• RF Packaged Part Testing

Please contact your local TriQuint Semiconductor Representative/ Distributor

or Foundry Services Division for Additional information:

E-mail: sales@triquint.com

Phone: (503) 615-9000

Fax: (503) 615-8905

Semiconductors for Communications

TriQuint Semiconductor

2300 NE Brookwood Pkwy

Hillsboro, Oregon 97124

Phone: 503-615-9000

Fax: 503-615-8905

Email: info@triquint.com

www.triquint.com

Page 3 of 3; Rev 1.0 12/1/2004

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