TQRLC [TRIQUINT]

Advanced Passives Foundry Service; 先进的无源器件代工服务
TQRLC
型号: TQRLC
厂家: TRIQUINT SEMICONDUCTOR    TRIQUINT SEMICONDUCTOR
描述:

Advanced Passives Foundry Service
先进的无源器件代工服务

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中文:  中文翻译
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ProductionProcess  
TQRLC
Advanced Passives Foundry Service  
Features  
Thick 4 Layer Metal; > 9 µm total  
thickness  
High Density Interconnects:  
3 Global  
1 Local  
High-Q Passives; Inductor Q >50  
@ 2 GHz  
Low Cost: Passives Only  
Thin Film Resistors  
Dielectric Encapsulated Metals  
Planarized Surface;  
simplified plastic packaging  
Volume Production Process  
TQRLCProcess Cross-Section  
Applications  
Passive Components:  
Phase Shifters  
Baluns  
Transformers  
Couplers  
General Description  
TriQuint’s TQRLC is a pure passives process. It is targeted at  
high performance, small size passive-only circuits and utilizes  
over 9 µm of gold metal. High density interconnections are ac-  
complished with three thick global and one surface metal inter-  
connect layers. The four metal layers are encapsulated in a high  
performance, low dielectric constant material that allows wiring  
flexibility and plastic packaging simplicity. Precision NiCr resis-  
tors, inductors, and high value MIM capacitors are available.  
The process is based on the TQTRx process, currently  
TriQuint’s highest volume process. The TQRLC process is  
available on 150-mm (6 inch) wafers.  
Mixers (with off-chip di-  
ode arrays)  
Circuits Requiring High-Q  
Passive Elements  
Matching Circuits  
RF Module Front-End Filters  
General RF and Microwave Imped-  
ance Matching  
Semiconductors for Communications  
Phone: 503-615-9000  
TriQuint Semiconductor  
2300 NE Brookwood Pkwy  
www.triquint.com  
Fax: 503-615-8905  
Page1of3;Rev2.33/18/04
Hillsboro, Oregon 97124  
Email: info@triquint.com  
ProductionProcess  
TQRLC
Advanced Passives Foundry Service  
Element  
Parameter  
Value  
Units  
µm  
TQRLC  
Process  
Details  
Interconnects Metal Layers  
Space Width  
Four: 0.4,2,2,5.5  
Met3= 5; Met1&2= 3  
Met3= 5; Met1&2= 2  
µm  
Trace Width  
µm  
BCB Dielectric Nom. Thickness  
ILD1= 1 +/-0.1;  
µm  
ILD2&3= 3.2 +/- 0.2  
Dielectric Constant  
2.8  
600  
50+/-3  
No  
MIM Caps  
Resistors  
Vias  
Values  
NiCr  
pF/mm2  
Ohms/sq  
Mask Layers  
No Vias  
10  
Capacitor Breakdown Voltage  
40  
V
Maximum  
Ratings  
Passivation  
Met3  
Via3  
ILD3  
dielectric  
Met2  
Met1  
Via2  
Via1  
ILD2  
dielectric  
Example of Metal Stack Configurations  
Possible with TQRLC Process; Edge– or  
Parallel-Coupled Structures Through  
The ILD Layers Are Also Possible.  
Met0  
MIM  
ILD1 dielectric  
Specifications Subject to Change  
Semiconductors for Communications  
Phone: 503-615-9000  
TriQuint Semiconductor  
2300 NE Brookwood Pkwy  
www.triquint.com  
Fax: 503-615-8905  
Page2of3;Rev2.33/18/04
Hillsboro, Oregon 97124  
Email: info@triquint.com  
Production Process  
TQRLC  
Advanced Passives Foundry Service  
Prototyping and Development  
Process Qualification Status  
Prototype Development Quickturn (PDQ):  
TQRLC is a fully-released process  
Reliability Reports  
Shared Mask Set;  
Run Monthly;  
Hot Lot Cycle Time;  
TQRLC Process Qualification  
TQTRx Element Qualification Report  
For more information on Quality and  
Reliability, contact TriQuint or visit:  
Prototype Wafer Option (PWO):  
Customer-specific Masks, Customer Schedule  
2 wafers delivered  
With thinning and sawing  
www.tqs.com/Manufacturing/QR/bdy_qr-pubs.htm.  
Applications Support Services  
Tiling of GDSII Stream Files including PCM  
Design Rule Check Services  
Layout versus Schematic Check Services  
Engineering Services:  
Design Tool Status  
Design Manual Available Now  
Device Library of Circuit Elements includes Thin Film  
Resistors, Capacitors, Inductors  
Agilent ADS Definition File for E-M Simulation Now  
Layout/Verification Kit for ICEditors  
Packaging Development  
Test Development Engineering (on-wafer and  
packaged parts)  
Thermal Analysis Engineering  
Yield Enhancement Engineering  
Cadence Layout Library Available Now  
Part Qualification Services  
Failure Analysis  
Manufacturing Services  
Mask Making  
Production 150 mm Wafer Fab  
Wafer Thinning  
Training  
GaAs Design Classes:  
Half Day Introduction; Upon Request  
Four Day Technical Training; Fall & Spring at  
TriQuint Oregon facility  
Wafer Sawing  
DC Die Sort Testing  
RF On-Wafer Testing  
Plastic Packaging  
For Training Schedules, please visit:  
www.triquint.com/foundry/  
RF Packaged Part Testing  
Please contact your local TriQuint Semiconductor Representative or  
Foundry Services Staff for additional information:  
E-mail: sales@triquint.com  
Phone: (503) 615-9000  
Fax: (503) 615-8905  
Semiconductors for Communications  
www.triquint.com  
TriQuint Semiconductor  
2300 NE Brookwood Pkwy  
Hillsboro, Oregon 97124  
Phone: 503-615-9000  
Fax: 503-615-8905  
Email: info@triquint.com  
Page 3 of 3; Rev 2.3 3/18/04  

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