TESDD5V0HC_15 [TSC]

Bi-directional ESD Protection Diode;
TESDD5V0HC_15
型号: TESDD5V0HC_15
厂家: TAIWAN SEMICONDUCTOR COMPANY, LTD    TAIWAN SEMICONDUCTOR COMPANY, LTD
描述:

Bi-directional ESD Protection Diode

文件: 总4页 (文件大小:197K)
中文:  中文翻译
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TESDD5V0HC  
Taiwan Semiconductor  
Small Signal Product  
Bi-directional ESD Protection Diode  
FEATURES  
- Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact)  
- Meet IEC61000-4-4 (EFT) rating. 40A (5/50ns)  
- Protects one Bi-directional I/O line  
- Working Voltage : 5V  
- Pb free version and RoHS compliant  
- Packing code with suffix "G" means  
green compound (halogen-free)  
SOD-523F  
MECHANICAL DATA  
- Case: SOD-523F small outline plastic package  
- Terminal: Matte tin plated, lead free., solderable  
per MIL-STD-202, Method 208 guaranteed  
- High temperature soldering guaranteed : 260°C/10s  
- Weight: 2 ± 0.5 mg  
- Marking code: TB  
APPLICATIONS  
- Cell Phone Handsets and Accessories  
- Notebooks, Desktops, and Servers  
- Personal Digital Assistants (PDA's)  
- Portable Instrumentation  
- Microprocessor Based Equipment  
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise noted)  
PARAMETER  
Peak Pulse Power (tp=8/20μs waveform)  
ESD per IEC 61000-4-2 (Air)  
VALUE  
SYMBOL  
UNIT  
W
PPP  
100  
± 15  
VESD  
KV  
oC  
ESD per IEC 61000-4-2 (Contact)  
± 8  
Junction and Storage Temperature Range  
TJ , TSTG  
-55 to +150  
PARAMETER  
MIN  
MAX  
5
SYMBOL  
VRWM  
V(BR)  
UNIT  
V
Reverse Stand-Off Voltage  
-
6
-
IR = 1 mA  
VR = 5 V  
Reverse Breakdown Voltage  
Reverse Leakage Current  
-
V
IR  
1
μA  
I
PP = 1 A  
PP = 5 A  
-
10  
15  
VC  
CJ  
Clamping Voltage  
V
I
-
VR = 0 V , f = 1.0 MHz  
Junction Capacitance  
35  
pF  
Document Number: DS_S1501016  
Version: C15  
TESDD5V0HC  
Taiwan Semiconductor  
Small Signal Product  
RATINGS AND CHARACTERISTICS CURVES  
(TA=25°C unless otherwise noted)  
Fig. 2 Pulse Waveform  
Fig. 1 Non-Repetitive Peak Pulse Power VS. Pulse Time  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
10  
Waveform parameters:  
tr = 8 μs , td = 20 μs  
1
0.1  
e-1  
td = Ipp / 2  
0.01  
0
5
10  
15  
20  
25  
30  
0.1  
1
10  
100  
1000  
Time (us)  
Pulse Duration (μs)  
Fig. 3 Admissible Power Dissipation Curve  
Fig. 4 Typical Junction Capacitance  
120  
100  
80  
60  
40  
20  
0
40  
35  
30  
25  
20  
15  
10  
5
f = 1.0 MHz  
0
0
20  
40  
60  
80  
100 120 140 160 180  
0
1
2
3
4
5
Ambient Temperature(oC)  
Reverse Voltage (V)  
Fig. 5 Clamping Voltage VS. Peak Pulse Current  
25  
20  
15  
10  
5
Waveform parameters:  
tr = 8 μs , td = 20 μs  
0
0
1
2
3
4
5
Peak Pulse Current (A)  
Document Number: DS_S1501016  
Version: C15  
TESDD5V0HC  
Taiwan Semiconductor  
Small Signal Product  
ORDER INFORMATION (EXAMPLE)  
TESDD5V0HC RKG  
Green compound code  
Packing code  
Part no.  
PACKAGE OUTLINE DIMENSIONS  
SOD-523F  
Unit (mm)  
Unit (inch)  
Min Max  
DIM.  
Min  
0.70  
1.50  
0.25  
1.10  
0.50  
0.07  
Max  
A
B
C
D
E
F
0.90  
1.70  
0.40  
1.30  
0.77  
0.20  
0.028 0.035  
0.059 0.067  
0.010 0.016  
0.043 0.051  
0.020 0.030  
0.003 0.008  
SUGGEST PAD LAYOUT  
Unit (mm)  
Unit (inch)  
Typ.  
DIM.  
Typ.  
0.40  
0.40  
1.00  
1.80  
0.016  
A
B
C
D
0.016  
0.039  
0.071  
Note: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts  
may vary depending on application.  
APPLICATION INFROMATION  
- Designed to protect one data, I/O, or power supply line  
- Designed to protect sensitive electronics from damage or latch-up due to ESD  
- Designed to replace multilayer varistors (MLVs) in portable applications  
- Offers superior electrical characteristics such as lower clamping voltage and no device degradation when compared to MLVs  
- The combination of small size and high ESD surge capability makes them ideal for use in portable applications  
CIRCUIT BOARD LAYOUT RECOMMENDATIONS  
- Good circuit board layout is critical for the suppression of ESD induced transients  
- Place the ESD Protection Diode near the input terminals or connectors to restrict transient coupling  
- Minimize the path length between the ESD Protection Diode and the protected line  
- Minimize all conductive loops including power and ground loops  
- The ESD transient return path to ground should be kept as short as possible  
Document Number: DS_S1501016  
Version: C15  
TESDD5V0HC  
Taiwan Semiconductor  
Small Signal Product  
Notice  
Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf,  
assumes no responsibility or liability for any errors or inaccuracies.  
Information contained herein is intended to provide a product description only. No license, express or implied,to  
any intellectual property rights is granted by this document. Except as provided in TSC's terms and conditions of  
sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty,  
relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose,  
merchantability, or infringement of any patent, copyright, or other intellectual property right.  
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.  
Customers using or seling these products for use in such applications do so at their own risk and agree to fully  
indemnify TSC for any damages resulting from such improper use or sale.  
Document Number: DS_S1501016  
Version: C15  

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