TTP258 [TTELEC]
Preliminary;
| 型号： | TTP258 |
| 厂家： | 
TT Electronics |
| 描述： | Preliminary |
| 文件： | 总44页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TTP258
TonTouchTM
Preliminary
§ PATENTEN
1. PATENT :『電流源控制及補償觸控電容感測方法及其裝置』
PAT NO. I339356 (Taiwan)
PAT NO. ZL 2007 1 0202087. 0 (CHINA)
2. PATENT :『具環境變化校正的電容式觸控感測裝置』
PAT NO. M383780 (Taiwan)
PAT NO. ZL 2010 2 0141537. 7 (CHINA)
3. PATENT :『省電型多鍵觸摸開關感測裝置』
PAT NO. M375250 (Taiwan)
PAT NO. ZL 2010 2 0302392. 4 (CHINA)
§ General Description:
TTP258 MCU is an easy-used 4-bit CPU base microcontroller. It
contains 1984-word ROM、144-nibble RAM、timer/Counter、interrupt
service 、IO control hardware、LVR and touch pad feature for specified
applications. The device is also suitable for diverse simple applications in
control appliance and consumer product.
§ Features:
1. Tontek RISC 4-bit CPU core
2. Total 26 crucial instructions and two addressing mode
3. Most instructions need 1 word and 1 machine cycle(2 system clocks)
except read table instruction(RTB)
4. advance CMOS process
5. Working memory with 1984*16 program ROM and 144*4 SRAM
6. 2-level stacks
7. Operating voltage:
5.5V~3.1V (LDO ON)；
5.5V~2.5V (LDO OFF、LVR ON)；
5.5V~2.2V (LDO OFF、LVR OFF)；
8. System operating frequency: (at VDD=5V )
. High-speed system oscillator (OSCH):
Built-in RC oscillator: 4MHz(typical)
.Low speed peripheral oscillator (OSCL):
Built-in RC oscillator: 16KHz(typical)
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TTP258
TonTouchTM
Preliminary
9. Offer 3 IO+10 touch pad or 13 general programmable I/O
IO port built-in key wake-up feature enable by software setting
Providing external interrupt inputs
Offering internal signal outputs, like buzzer(PWM)
10. One 8-bit TCP1 auto-reload timer/counter & onetime base counter
4 timer clock sources selected by software
Time base offers 2 various period interrupt request
11. One 8-bit TCP2 auto-reload timer/counter, can improve PWM function
4 timer clock sources selected by software
12. Built-in 3 set 8-bit PWM output
13. MCU system protection and power saving controlled mode:
Built-in watch dog timer (WDT) circuit
ROM code error detection
Out of user program’s range detection
Providing high/low system operating speed、sleep mode for
power saving control
Built-in low voltage reset (LVR) function
14. 10 pins with touch pad detection
15. Built-in LDO voltage 2.7V
16. Provides 8 interrupt sources
External: INT0, INT1 shared with IO pad
Internal: two Timer/counter, two Time base timer
Two touchpad’s interrupt
17. Provide package types
SOP 16
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TTP258
TonTouchTM
Preliminary
§ Applications:
1. Household electric appliances
2. Consumer products
3. Measurement controller
§ Package Description:
PD0/TP4
PD1/TP5
PD2/TP6
PD3/TP7
PB0/TP8
PB1/TP9
CAP
PC3/TP3
PC2/TP2
PC1/TP1
PC0/TP0
VDD
PA2/PWM2
PA1/INT1/PWM1
PA0/INT0/PWM0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
16-SOP-A
PD0/TP4
PD1/TP5
PD2/TP6
PD3/TP7
PB0/TP8
PB1/TP9
CAP
PC3/TP3
PC2/TP2
PC1/TP1
PC0/TP0
VDD
VREG
PA1/INT1/PWM1
PA0/INT0/PWM0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
16-SOP-B
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TTP258
TonTouchTM
Preliminary
§ Block Diagram:
OSCH &
Base Timer
OSCL
PA2~PA0
PB1~PB0
8 bit Timer/Counter
ROM
RAM
PC3~PC0
I/
O
8 bit Timer/Counter
PWM 0, 1, 2
PD3~PD0
System Control Unit
ST426
MCU
Interrupt
RESET
RSTB
Touch Pad
Detection
LVR
WDT
CAP
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TTP258
TonTouchTM
Preliminary
§ Pin Description:
Pin Name
Share Pin
I/O Pin no. Mask Option
Pin Description
VDD
-
-
Power +1
Power +1
-
-
-
Positive power supply
VSS
Negative power supply, ground
External reset input, active low,
50kΩ pull-up( VDD =5v)
RSTB
-
I
+1
PA0
PA1
PA2
INT0/PWM0/VPP IO
+3
-
I/O port with external interrupt
INT1/PWM1
PWM2
IO
IO
input
and
PWM
output
(PA0,PA1). PA2 is shared with
internal PWM2 output.
PB0
PB1
TP8
TP9
IO/I
IO/I
+2
+4
-
-
IO port or touch pad input.
PC0
PC1
PC2
PC3
PD0
PD1
PD2
PD3
CAP
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
-
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
O
IO port or touch pad input.
IO port or touch pad input.
+4
+1
-
-
-
-
Touch signal output
LDO Voltage output
VREG
Power +1
18
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TTP258
TonTouchTM
Preliminary
§ IO Cell type Description:
Pin Name
PA1
I/O Type
Figure IO-D
Figure IO-E
Figure IO-B
Figure IO-A
Figure IO-A
Figure IO-A
Description
STD IO with internal output & external input
STD IO with internal output & external input
STD IO with internal output
PA0
PA2
PB0~PB1
PC0~PC3
PD0~PD3
STD IO with external input
STD IO with external input
STD IO with external input
§ Absolute Maximum ratings:
ITEM
SYMBOL
Top
RATING
-20℃ ~ +70℃
-50℃ ~ +125℃
VSS-0.3 ~ VSS+12.5
VSS -0.3 ~ VDD+0.3
>5
UNIT
℃
Operating Temperature
Storage Temperature
OTP Supply Voltage
Input Voltage
℃
Tst
V
VPP
V
Vin
KV
Human Body Mode ESD
Note: VSS symbolizes for system ground
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TTP258
TonTouchTM
Preliminary
DC & AC Characteristics
§ DC Characteristics: (Test condition at room temperature=25oC)
Parameter
Symbol
Test Condition
Min. Typ. Max. Unit
LDO on；LVR on
3.1
3.1
2.5
2.2
2.0
2.4
-
-
5.5
5.5
5.5
5.5
2.4
3.0
LDO on；LVR off
LDO off；LVR on
LDO off；LVR off
LVR select 2.2V
LDO select 2.7V
Operating Voltage
VDD
V
-
-
Low Voltage Reset (LVR)
LDO Voltage
VLVR1
VLDO1
2.2
2.7
V
V
Ind1
VDD=5.0V, no load, FOSCH=4MHz,
-
2.5
3.0
mA
Operating Current
(Normal Mode, CPU working,
I/O no load )
VDD=5.0V, no load, FOSCL on, FOSCH off,
LVR off, LDO off
Ind2
Isd1
Isd2
-
-
-
30
0.7
5
50
1.0
10
uA
mA
uA
VDD=5.0V, no load, FOSCH=4MHz,
Operating Current
(Sleep Mode, CPU stop,
I/O no load)
VDD=3.0V, no load, FOSCL on, FOSCH off,
LVR off, LDO off
LVR Current
LDO Current
Input Ports
Input Ports
RSTB & INT
RSTB & INT
ILVR
ILDO
VIL
VDD=5.0V
-
-
55
-
uA
VDD=5.0V
100
-
uA
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
0
-
-
-
-
0.2
1.0
0.3
1.0
VDD
VDD
VDD
VDD
VIH
VIL
0.8
0
VIH
0.7
PA0 Sink Current
IOL
IOH
VDD=5.0V, VOL=0.6V
-
-
2
-
-
mA
mA
PA0 Source Current
VDD=5V, VOH=VDD-0.7V
-1
Output port Sink Current
(exclude PA0)
IOL
VDD=5.0V, VOL=0.6V
-
-
8
-
-
mA
mA
Output Port Source Current
(exclude PA0)
IOH
VDD=5V, VOH=VDD-0.7V
-4
I/O Port Pull-up Resistor
RSTB Pull-up Resistor
Band gap Voltage
RPH
RPH
VDD=5.0V
VDD=5.0V
100
30
150
50
200
80
KΩ
KΩ
V
VBGAP
1.0
1.12 1.23
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TTP258
TonTouchTM
Preliminary
§ AC Characteristics:(Test condition at room temperature=25oC)
Parameter
External Reset
Interrupt input
Test Condition
Min.
Typ.
Max.
Unit
CPU
Low active pulse width tRES
2
2
-
-
-
-
clock
Low active pulse width tINT
Low active pulse width twkup, Application de-bounce
should be manipulated by user’ software
Wake up input
2
-
-
OSCL
Hz
System
Oscillator
Frequency
FOSCH (Built-in RC)
VDD=5.0V
VDD=5.0V
-
4M
-
Peripheral
Oscillator
Frequency
Built-in FOSCL(RC)
12K
16K
21K
Hz
Startup Period
of
T
OSCH (Built-in RC)
wake-up from off mode
Wake-up from off mode
8
8
8
-
-
-
-
-
-
FOSCH
FOSCL
FOSCH
Oscillators
TOSCL (Built-in RC)
OSCLÆOSCH
T
OSCH ( Built-in RC)
Stable Time
Of
& OSCH off
(If H/L=0 then OSCH stop)
OSCHÆOSCL
System Clock
Switching
TOSCL ( Built-in RC)
8
-
-
-
FOSCL
& OSCL on
Timer/Counter
input clock
frequency
Input frequency rating, no de-bounce circuit built-in
,at VDD=5V
DC
4M
Hz
System Stable
Time after
After power up, the system needs to initialize the
configured state and OST.
-
-
40
ms
Power up
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TTP258
TonTouchTM
Preliminary
§ Memory Map:
ROM ADDRESS
RAM ADDRESS
Function Block
Program ROM [1984*16]
File Registers
-
000H~7BFH
-
-
-
-
000H ~007H
008H~01FH
020H~0AFH
200H~304H
Peripheral registers (I)
Working RAM [144*4]
Peripheral registers (II)
§ Interrupt Vectors:
Interrupt Vectors
Function Description
$000
$001
hardware RESET
Hardware IRQ
§ File registers:
Address Symbol R/W Default
Description
000H
001H
002H
003H
004H
005H
006H
007H
(DP1)
ACC
TB1
TB2
TB3
DPL
DPM
DPH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
Indirect addressing register
Accumulator & Read Table 1st data
Read Table 2nd data
Read Table 3rd data
Read Table 4th data
Data Pointer low nibble
Data Pointer middle nibble
Data Pointer high nibble
§ Peripheral registers: Interrupt request flag register
Address Symbol R/W Default
Description
CPU power saving control register
Peripheral power saving control register
Interrupt enable control register
Interrupt request flag register
Extended interrupt enable register
Extended interrupt request flag register
PWM control register
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
010H
011H
012H
013H
014H
015H
PS
PSP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
0100
0000
0000
0000
0000
0000
0000
xxxx
xxxx
-
INTC
INTF
INTC1
INTF1
PWMC
PWM0L
PWM0H
-
PAC
PA
PBC
PB
PWM0 duty low nibble data register
PWM0 duty high nibble data register
R/W
R/W
R/W
R/W
1111
1111
1111
1111
I/O port A control register
I/O port A data register
I/O port B control register
I/O port B data register
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TTP258
Preliminary
TonTouchTM
016H
017H
018H
019H
01AH
01BH
01CH
01DH
01EH
01FH
200H
201H
202H
203H
204H
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20EH
20FH
210H
211H
212H
213H
214H
215H
216H
217H
218H
219H
21AH
300H
301H
302H
303H
304H
PCC
PC
PDC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
1111
1111
1111
1111
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
xxxx
xxxx
0000
xxxx
xxxx
----
I/O port C control register
I/O port C data register
I/O port D control register
I/O port D data register
PD
PWM1L
PWM1H
PWM2L
PWM2H
TPINTC
TPINTF
TCP1C
TCP1L
TCP1H
TCP2C
TCP2L
TCP2H
PAI
PWM1 duty low nibble data register
PWM1 duty high nibble data register
PWM2 duty low nibble data register
PWM2 duty high nibble data register
Touchpad interrupt enable control register
Touchpad interrupt request flag register
TCP1 Timer/counter control register
TCP1 Timer/counter data low register
TCP1 Timer/counter data high register
TCP2 Timer/counter control register
TCP2 Timer/counter data low register
TCP2 Timer/counter data high register
Port A pad data reading address
Port B pad data reading address
Port C pad data reading address
Port D pad data reading address
-
PBI
PCI
PDI
-
R
R
R
-
----
----
----
-
-
-
-
-
TCPFS
TBC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000
1111
0111
0000
0000
0000
0000
xxxx
xxxx
xxxx
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
0000
TCP clock source FS pre-scale register
Time base control register
MCKS
TPCHS0
TPCHS1
TPCHS2
TPCTL
TPCT0
TPCT1
TPCT2
Modulation clock selector register
Touch pad channel selector register
Touch pad channel selector register
Touch pad channel selector register
Touch pad control register
Touch pad Duty counter 1st nibble
Touch pad Duty counter 2nd nibble
Touch pad Duty counter 3rd nibble
LDO fail flag
Touch pad C load
Special control register 0
Special control register 1
Touchkey output register for special function
Reset flag
LDOFLAG R/W
CSA
R/W
R/W
R/W
R/W
R/W
W
W
W
R/W
SPCON0
SPCON1
ODATA
RESETF
TBRB
MRO
CLRWDT
LVREN
Time base counter clear address
Mask option register write enable address
Clear WDT 2nd instruction
LVREN register
Note:
a. Default means initial value after power on or reset.
b. R is “read” only, W is “write” only, R/W is both of “read” & “write”.
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TTP258
TonTouchTM
Preliminary
§ System function description:
S-1: System Oscillator
The high-speed oscillator is operated in built-in RC mode. Built-in RC
oscillator is fixed 4MHz
S-2: Peripheral Oscillator
The low speed oscillator was built-in an internal RC oscillator that is for low
power consumption consideration and fixed peripheral device timing control.
Built-in RC oscillator and the frequency range between 12 KHz ~ 21 KHz.
S-3: CPU clock
The CPU clock comes from system/peripheral oscillator which was controlled
by H/L bit in PS register. In the normal operation, the system clock comes from
high-speed system oscillator (OSCH/2). The low speed operation frequency
(OSCL/2) comes from RC oscillator.
OSCEN
OSCH
RC oscillator
Figure: System High Speed Oscillator
1
M
U
X
OSC
CPU machine
/2
0
H/L
16K Hz (Built-in RC)
Peripheral clock OSCL (16K Hz)
TBCK
Figure: System Oscillator & CPU Clock Sources
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TTP258
TonTouchTM
Preliminary
S-4: Power saving mode (Sleep mode)
The CPU enters sleep mode is operated by writing CPU power saving register
(PS). During the power saving mode, CPU holds the internal status of the
system.
S-5: MCU System Operation Modes
The MCU has 3 operating modes, including high-speed operation, low speed
operation, sleep modes. After power on reset, the MCU will go into high-speed
operation mode automatically. After wake up from sleep mode, the MCU will
resume the last operation mode.
High speed operating
mode
OSCH on & OSCL on
H/L
Reset release
Low speed operating
mode
Reset
OSCH off & OSCL on
Reset
RESET
SLEEP/ wake up
SLEEP/ wake up
Reset
SLEEP mode
CPU stop
Figure: System Operation State Diagram
* Power saving mode condition & Release
Modes
High speed oscillator
High speed oscillator
CPU clock
Sleep mode
Stopped as H/L=0
Keep Operating as H/L=1
Stopped
CPU internal status
Memory, Flag, Register, I/O
Program counter
Stop & Retain the status
Retain the status
Hold the next executed address
Peripherals: Time base, Timers,
Interrupts
Keep Operating
Watch Dog Timer
Disable & cleared
Release Condition
Reset, external and internal INT sources, Input Wake-up
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TTP258
TonTouchTM
Preliminary
S-6: Watch Dog Timer (WDT)
The clock of watchdog timer comes from time base overflow (TB1OV). User
can use the time up signal to prevent a software malfunction or abnormal
sequence from jumping to an unknown memory location causing a system fatal
failure. Normally, if the watchdog timer time up signal active that will reset the
chip. At the same time, program and hardware can be initialized and resume
system under normal operation. The chip also provides 2 steps clear watchdog
command as the programmer writes INTF with $F data first that will enable the
WDT clear, and then writes clear WDT 2nd register ($303H) after. Completely
finishes the two write & read steps will clear the watchdog timer. User should
well arrange the two command steps for avoiding the dead lock loop.
User should keep in minds that always reset WDT at main
program and never clear the WDT in the interrupt routine.
The max period of WDT =(TB1OV cycle time) * 8
TB1OV
as clock
Q
WDT
QB
TFF
TFF
TFF
DFF
Overflow
POR+RESET
SLEEP
INTF write $F first then
Write $303H after
Write INTF first &
Write $303H after
Figure: Watch Dog Timer control circuit
S-7: Low Voltage Reset (LVR)
The low voltage reset (LVR) forces the MCU in reset state during power
failure, especially as MCU working in AC power application, preventing from
abnormal state is the key issue. The control bit LVREN is in independent
register. It can prevent LVREN change by unexpected program. The LVR can
select always on or control by register by metal trim and LVR voltage is 2.2V.
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TTP258
TonTouchTM
Preliminary
S-8: RESET
The chip has four kinds of reset sources: POR (power on reset), External
reset, Watch dog timer reset, LVR (low voltage reset). The reset feature can be
divided into 2 kind groups that one is system reset and the other is CPU reset.
The system reset will initialize the CPU and peripheral device with default state.
The CPU reset only initializes the CPU state and keeps the peripheral state no
change.
.POR (power on reset)
The chip provides automatic reset function when the power is turned on. The
VDD should be below 1.6V and its rising slope (from 0.1VDD up to 0.9VDD)
needs less than 10ms.
.External Reset (RSTB)
This is one kind of system resetting signal, but only forced externally. When
the chip acknowledged the low level from the pin RSTB exceed 1 us, it will
generate the reset procedure to reset CPU & all the peripheral back to their
initial state (default values).
.Burn out Reset (Program sequence abnormal)
As CPU out of program area, the CPU can detect the abnormal condition and
generate a system reset request.
.Watch Dog Timer Reset
The reset signal will generate automatically when the watchdog timer runs
overflow. If the watchdog timer is cleared regularly by users’ program, no
watchdog reset will occur. Unless the MCU is forced into abnormal state, the
software-controlled procedure is disrupted and causing watchdog timer
overflow, then it will generate reset signal to initializes the chip returning to
normal operation.
.Low Voltage Reset (LVR)
The LVR function is used to monitor the supply voltage of MCU, it will
generate a reset signal (with 4*OSCL de-bounce time) to reset the
microcontroller as the VDD power falls below the default setting level VLVR. It
can also be enabled or disabled by programming “LVREN” bit in LVREN register
(304H). User write $5H to this register, it can enable LVREN, write $AH can
disable LVREN. If user writes other value to LVREN register, it cannot change
LVREN bit.
RESETF[300H]: reset source flag register[R/W], power on value [0000]
Register
Bit Name
Read/Write
Bit3
ROMF
R/W
Bit2
BOF
R/W
Bit1
LVRF
R/W
Bit0
WDTF
R/W
WDTF: Watch dog timer overflow reset flag (0: no active; 1: active)
LVRF: Low voltage reset flag (0: no active; 1: active)
BOF: Burn out flag (0: no active; 1: active)
ROMF: ROM fail flag (0: no active; 1: active)
(The RESETF is cleared by power on reset and external RESET)
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TTP258
TonTouchTM
Preliminary
S-9. Power saving control register
PS[008H]: Power saving register[R/W] , default value [0100]
Register
Bit Name
Read/write
Bit3
Bit2
H/L
Bit1
Bit0
-
SLEEP
-
-
-
R/W
R/W
SLEEP: Into sleep mode. (0: inactive; 1: active)
H/L: System clock selection. (1: System clock; 0: peripheral clock)
The SLEEP bits will be cleared to “0” automatically, when the release
conditions occur from reset, interrupt, or input wake up.
PSP[009H]: Peripheral power saving register[R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
LDOEN
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
LDOEN: LDO enable. (0: disable; 1: enable)
LVREN[304H]: LVR enable control register[R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LVREN
R/W
-
-
-
-
-
-
LVREN: low voltage reset enable, (0: disable, 1: enable), When write $5 to this address,
LVREN is set to 1 , write $A to this address, LVREN is clear to 0.
LDOFLAG[216H] : LDO falg register[R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LDOFAIL
R/W
-
-
-
-
-
-
LDOFAIL: When VDD voltage is small then LDO voltage, LDOFAIL will be set. This bit can be
clear by write 0.
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
S-10. Special control register
SPCON0 [218H]: Special control register 0 [R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
CDSC2
R/W
Bit2
CDSC1
R/W
Bit1
CDSC0
R/W
Bit0
VREFS
R/W
VREFS: Voltage reference selection for touch sensor detect (0: 1/2 VDD; 1: 2/3 VDD), use in
TPNI select comparator output signal mode.
CDSC: Charge and discharge sequence control for touch sensor function
CDSC2 ~ CDSC0
Sequence change clock
000
001
010
011
100
101
110
111
OFF
8
12
16
24
32
Reserve
Reserve
SPCON1 [219H]: Special control register 1 [R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
INTTS
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
INTTS: INT0 Interrupt input type selection (0: Schmitt; 1: comparator)
reference voltage use band gap voltage
Compare
The system oscillator generates the system control timing for CPU core
or peripheral devices with fixed control phase, so the waveform of
oscillator becomes sensitive to noise, abnormal duty especially fatal for
CPU. Any switching of clock source needs oscillation stable time (OST)
to make sure the oscillation is stable and synchronized with CPU timing
phase. The relative OST for different oscillator with reference value as
below table:
OST
From Stop state
oscillating
Unit
System clock(OSCH)
RC Peripheral clock(OSCL)
8
8
8
8
OSCH clock
OSCL RC clock
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Preliminary
S-11. Interrupts
The CPU provides only 1 interrupt vector ($001H) and no priority, but can
expand to multi-sources. Interrupt source includes external interrupts (INT0,
INT1), timer/counter interrupts (TCP1,TCP2), Time base timer interrupt
(TBxINT) or other peripheral device interrupt request (PERINT). The interrupt
control registers (INTC or INTC1) contain the interrupt control bits to enable
and disable corresponding interrupt request and the corresponding interrupt
request flags in the (INTF or INTF1) registers. Before finishing the INT service
routine, another INT request will keep waiting until program return from
interrupt routine.
If the interrupt request needs service, the programmer may set the
corresponding INT enable bit to allow interrupt active. External interrupts are
triggered by both falling and rising edge trigger and set the related interrupt
request flag (INTFx). The internal timer/counter interrupt is setting the TCPxF
to 1, resulting from the timer/counter overflow. The time base interrupt TBxINT
was provided 2 periodic interrupt request cycles for user operating a periodic
routine.
When the corresponding interrupt enable and flag bits is set to 1, the CPU
will active the interrupt service routine. Then CPU reads the service flag and
check the request priority then proceeds with the relative interrupt service.
After CPU writes the corresponding bits to 0 in the INTFx register, the service
flag will be cleared to 0(using STX #n, $m instruction). The INTF & INTF1
registers’ bit can only write “0” to clear the flag. User writes “1” to Flag bit with
no effect.
INT0 input type can select Schmitt or comparator by SPCON1 register, if
comparator select then the comparator reference voltage is the band gap
voltage(1.12+-10%), it will consumption more current than Schmitt because
band gap turn on. It can be used to detect VDD voltage for battery low and so
on.
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Preliminary
INTC[00AH]: Interrupt control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TB2IE
R/W
Bit2
TCP2IE
R/W
Bit1
TCP1IE
R/W
Bit0
TB1IE
R/W
TB1IE: Enable time base 1st interrupt. (0: disable; 1: enable)
TCP1IE: Enable interrupt of TCP1 timer/counter. (0: disable; 1: enable)
TCP2IE: Enable interrupt of TCP2 timer/counter. (0: disable; 1: enable)
TB2IE: enable time base 2nd interrupt. (0: disable; 1: enable)
INTF[00BH]: Interrupt request flag register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TB2F
R/W
Bit2
TCP2F
R/W
Bit1
TCP1F
R/W
Bit0
TB1F
R/W
TB1F: Time base timer 1st interrupt request flag. (0: inactive; 1: active)
TCP1F: TCP1 Timer/counter interrupt request flag. (0: inactive; 1: active)
TCP2F: TCP2 Timer/counter interrupt request flag. (0: inactive; 1: active)
TB2F: Time base 2nd interrupt request flag. (0: inactive; 1: active)
INTC1[00CH]: Extended interrupt control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
-
-
Bit2
-
-
Bit1
INT1IE
R/W
Bit0
INT0IE
R/W
INT0IE: enable INT0 external interrupt. (0: inactive; 1: active)
INT1IE: enable INT1 external interrupt. (0: inactive; 1: active)
INTF1[00DH]: Extended interrupt request flag register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
-
-
Bit2
-
-
Bit1
INT1F
R/W
Bit0
INT0F
R/W
INT0F: INT0 external interrupt request flag. (0: inactive; 1: active)
INT1F: INT1 external interrupt request flag. (0: inactive; 1: active)
INTxS1 INTxS0
Trigger type
Low active
Falling edge
00
01
10
11
Rising edge
Dual edge trigger
Note: INTxF Trigger type are selected by mask option
TPINTC[01EH]: Touchpad interrupt control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TPCTIE
R/W
Bit2
TPCMPIE
R/W
Bit1
-
-
Bit0
-
-
TPCMPIE: Capacitor overcharge interrupt enable. (0: disable; 1: enable)
TPCTIE: Duty counter overflow interrupt enable. (0: disable; 1: enable)
TPINTF[01FH]: Touchpad request flag register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TPCTF
R/W
Bit2
TPCMPF
R/W
Bit1
-
-
Bit0
-
-
TPCMPF: Capacitor overcharge’s flag. (0: inactive; 1: active)
TPCTF: Duty counter’s overflow flag. (0: inactive; 1: active)
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Preliminary
§ Peripheral function description:
P-1: System clock pre-scale
The system clock almost is the most high frequency of MCU. For various peripherals,
application needs different clock source divided from system clock. TCPFS register is a
selector for choosing suitable frequency (FS).
TCPFS[20CH]: System clock pre-scale register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
FS2
R/W
Bit1
FS1
R/W
Bit0
FS0
R/W
-
-
FS2~FS0: the selector value of TCPFS register
FS2 ~ FS0
FS
FS2 ~ FS0
FS
0
1
2
3
OSCH/1
OSCH/2
OSCH/4
OSCH/8
4
5
6
7
OSCH/16
OSCH/32
OSCH/64
OSCH/128
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Preliminary
P-2: Time Base Counter
The time base counter has 2 interrupt sources and both of them come from
the peripheral internal RC oscillator. The time base 1st overflow output (TB1OV)
can cause interrupt and the period is selected by TB1S2~TB1S0 in TBC register.
The time base 2nd overflow output (TB2OV) also offers two sample frequency
options by TB2S bit in the TBC register.
TBCK
16 KHz
TBCK/2
8 KHz
TBCK/16
TB1OV
TB2OV
1 KHz
256Hz
64Hz
8Hz
TBCK/64
TBCK/256
TBCK/2048
TBCK/8192
TBCK/16384
TBCK
14 bit Binary
Counter
2Hz
(if OSCL=16KHz)
1Hz
MUX
Write TBRB &
CLEAR counter
TB2S
TB1S2~TB1S0
TBC[20DH]: Time base control register[R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
TB1S2
R/W
Bit1
TB1S1
R/W
Bit0
TB2S
TB1S0
R/W
R/W
TB1S2 ~ TB1S0: Base timer1 overflow frequency selection bits.
TB2S: Base timer2 overflow frequency selection (0: 32Hz; 1:16Hz)
(Every time writing the TBRB will clear the time base counter)
TB2S
Base timer overflow
frequency (TB1OV)
TBCK/512
TB2OV
(if OSCL=16KHz)
0
1
32Hz
16Hz
TBCK/1024
TB1S2 TB1S1 TB1S0
Base timer overflow
frequency (TB1OV)
TBCK
TB1OV
(if OSCL=16KHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16KHZ
8KHZ
1KHZ
256HZ
64 HZ
8HZ
TBCK/2
TBCK/16
TBCK/64
TBCK/256
TBCK/2048
TBCK/8192
TBCK/16384
2HZ
1HZ
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Preliminary
P-3: 8 bits Timer/Counter (TCP) for TCP1
One 8-bit timer/counters (TCP) with 4 kind clock sources and preload data
buffer can implement as a timer or counter feature. The clock sources of TCP1
are selected by TCP1S0 & TCP1S1 two bits of the timer control registers
(TCP1C). TCP1OV is the timer or counter overflow signal and the rising edge
will set the relative INT flag.
TCP1C[200H]: TCP1 Timer/counter control register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TCP1LD
R/W
Bit2
TCP1S1
R/W
Bit1
TCP1S0
R/W
Bit0
TCP1EN
R/W
TCP1EN: TCP1 counting enabled. (0: disable; 1: enable)
TCP1LD: TCP1 auto-reload enabled. (0: disable; 1: enable)
TCP1S1 & TCP1S0: TCP1 clock source selection bits.
TCP1S1
TCP1S0
Selected Clock source
0
0
1
1
0
1
0
1
CK0
CK1
CK2
CK3
TCP1L[201H]: TCP1 low nibble data register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
TCP1_3/TCP1D3 TCP1_2/TCP1D2 TCP1_1/TCP1D1 TCP1_0/TCP1D0
R/W
R/W
R/W
R/W
TCP1_3~TCP1_0: reading the counter low nibble data.
TCP1D3~TCP1D0: writing TCP1D low nibble of data buffer.
TCP1H[202H]: TCP1 high nibble data register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
TCP1_7/TCP1D7 TCP1_6/TCP1D6 TCP1_5/TCP1D5 TCP1_4/TCP1D4
R/W
R/W
R/W
R/W
TCP1_7~TCP1_4: reading the counter high nibble data.
TCP1D7~TCP1D4: writing TCP1D high nibble of data buffer.
* TCP1D: Like a 8 bit TCP1 data register[R/W], default value [00H]
TCP1D Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
Bit1
Bit0
Bit Name TCP1D7 TCP1D6 TCP1D5 TCP1D4 TCP1D3 TCP1D2 TCP1D1 TCP1D0
The special R/W function for TCP1 has different Target, AS writing TCP1H/L
registers that are updating preload data of the TCP1D. As read TCP1H/L
registers that are the brand new TCP1 counter value.
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Preliminary
P-4: 8 bits Timer/Counter/PWM for TCP2
One 8-bit timer/counters (TCP2) with 4 kind clock sources and preload data
buffer can implement as a timer or counter feature. The clock sources of TCP2
are selected by TCP2S0 & TCP2S1 two bits of the timer control registers
(TCP2C). TCP2OV is the timer or counter overflow signal and the rising edge
will set the relative INT flag.
TCP2C[203H]: TCP2 Timer/counter/PWM control register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TCP2LD
R/W
Bit2
TCP2S1
R/W
Bit1
TCP2S0
R/W
Bit0
TCP2EN
R/W
TCP2EN: TCP2 counting enabled. (0: disable; 1: enable)
TCP2LD: TCP2 auto-reload enabled. (0: disable; 1: enable)
TCP2S1 & TCP2S0: TCP2 clock source selection bits.
TCP2S1
TCP2S0
Selected Clock source
0
0
1
1
0
1
0
1
CK0
CK1
CK2
CK3
TCP2L[204H]: TCP2 low nibble data register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
TCP2_3/TCP2D3 TCP2_2/TCP2D2 TCP2_1/TCP2D1 TCP2_0/TCP2D0
R/W
R/W
R/W
R/W
TCP2_3~TCP2_0: reading the counter low nibble data.
TCP2D3~TCP2D0: writing TCP2D low nibble of data buffer.
TCP2H[205H]: TCP2 low high data register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
TCP2_7/TCP2D7 TCP2_6/TCP2D6 TCP2_5/TCP2D5 TCP2_4/TCP2D4
R/W R/W R/W R/W
TCP2_7~TCP2_4: reading the counter high nibble data.
TCP2D7~TCP2D4: writing TCP2D high nibble of data buffer.
* TCP2D: Like a 8 bit TCP2 data register[R/W], default value [00H]
TCP2D
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit Name TCP2D7 TCP2D6 TCP2D5 TCP2D4 TCP2D3 TCP2D2 TCP2D1 TCP2D0
The special R/W function for TCP2 has different Target, AS writing TCP2H/L registers that are
updating preload data of the TCP2D. As read TCP2H/L registers that are the brand new TCP2
counter value.
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Preliminary
P-5: 16 bits Timer/Counter
Two sets TCP can be cascaded to form a 16-bit timer/counter when TCP2
chooses TCP1OV as clock source (TCP2S1=1 & TCP2S0=1). In the 16-bit timer
application, data load is controlled by writing TCP1EN=1 , then user should
enable the TCP2EN at first, then using TCP1EN to control the starting or
stopping counting of 16-bit timer/counter. The rising TCP2OV will reload the
contents in the pre-load register into timer/counter, if TCP1LD in TCP1C &
TCP2LD in TCP2C are enabled. The interrupt feature is different, in this case,
the TCP1 INT will be inhibit when TCP1OV occur, the TCP2 INT is normally.
Figure: 16 Bit Timer/Counter Configuration
.Timer
When TCPx works as a Timer, user needs give the preload data TCPxD for
periodic interrupt. After initial setting, user starts the TCPx counting by setting
TCPxEN=1, the TCPx cycle period is:
Tc = (selected clock cycle) * (256) if TCPxD=00H
Tc = (selected clock cycle) * (TCPxD) otherwise
When 16 bits timer/counter:
Tc = (selected clock cycle) * (65536) if TCP1D=00H & TCP2D=00H
Tc = (selected clock cycle) * (TCP2D*256+TCP1D) otherwise
When user writes data to the TCPxD, the data just keep in TCPxL/H. During
the TCPxEN=1 command executed, the TCPxD’s complement value will load
into counter TCPx as initial value and start the timer function. Necessary
TCPxLD=1, timer run with reload feature as TCPx up counts and reaches the
value of “FFH” or 255 for TCPx. At the same time, interrupt request flag TCPxF
will set activated, if software enables the corresponding interrupt enable bit,
INT hardware will cause MCU interrupt service routine.
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Preliminary
.Counter
Counter feature is implemented only by TCPxLD=0, the TCPxD can be zero
or not that depends on software needs. User starts & stops the counter by
changing the TCPxEN bit value. On the save side, reading the counter value
after stopping the count by disable TCPxEN=0, if reading the counter value
during value changing that means clock in happening at the same time. The
reading of counter value may disrupt for transient state. If 8 bit counter is not
enough for counting, user can enable the interrupt and using the data RAM as
software counter for extending the counter stage.
CK0
Data Bus
Timer/Counter
M
U
X
CK1
CK2
CK3
PWMx Circuit
TCP2OV
Preload Data
TCP2S1
TCP2S0
TCP2L
Data Bus
TCP2EN
Figure: Timer/Counter/PWM
TCP1S1 TCP1S0 TCP1
PWM Output
PWM0,1,2
CK0
CK1
CK2
CK3
0
0
1
1
0
1
0
1
FS
TCP2
OSCH
TBCK
TB1OV
TCP2S1 TCP2S0 TCP2
CK0
CK1
CK2
CK3
0
0
1
1
0
1
0
1
FS
OSCH
TBCK
TCP1OV
FS: System scaled frequency.
TBCK: Peripheral clock source, 16KHZ in the RC mode. (Typical)
TB1OV: Time base 1st overflow output.
PWM0~2: TCP2 cycle time with PWMxD duty output signal
TCP1OV: Timer/counter1’s overflow output.
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Preliminary
.PWM
The PWM period generated from TCP2. When PWMxEN (PWMC<0> or
PWMC<1> or PWMC<2>) enable, and PWMOUT pin (PA0, PA1, or PA2 the PAx
must be output mode and select normal IO by mask option) change to output
mode, PWMx signal will output to PWMOUT pin.
The duty of PWMx value is store in PWMxL and PWMxH, user write PWMxH
first, last write PWMxL. When write the PWMxL the 8 bits duty value will be
load to PWMxD at the same time. PWM’s duty value cannot bigger than TCP2
pre-load data. If not, PWMOUT is an unexpected signal.
User can select PWMOUT pin start with 1 or start with 0 by option. When
TCP2 enable, timer start increment, if timer/counter value bigger than PWM’s
duty value, PWMOUT will change state. The PWMOUT back to start state,
When TCP2 is overflow.
User does not use PWM in 16 bits timer/counter mode. If not, PWMOUT is
an unexpected signal.
User does not use TCP2D=00H. If not, PWMOUT is an unexpected signal.
PWMC[00EH]: PWM control register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
-
-
Bit2
PWM2EN
R/W
Bit1
PWM1EN
R/W
Bit0
PWM0EN
R/W
PWM0EN: PWM0 output enabled. (0: disable; 1: enable)
PWM1EN: PWM1 output enabled. (0: disable; 1: enable)
PWM2EN: PWM2 output enabled. (0: disable; 1: enable)
PWM0L[00FH]: PWM0 duty low nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM0D3
R/W
Bit2
PWM0D2
R/W
Bit1
PWM0D1
R/W
Bit0
PWM0D0
R/W
PWM0D3~0: PWM0 duty low nibble data
PWM0H[010H]: PWM0 duty high nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM0D7
R/W
Bit2
PWM0D6
R/W
Bit1
PWM0D5
R/W
Bit0
PWM0D4
R/W
PWM0D7~4: PWM0 duty high nibble data
PWM1L[01AH]: PWM1 duty low nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM1D3
R/W
Bit2
PWM1D2
R/W
Bit1
PWM1D1
R/W
Bit0
PWM1D0
R/W
PWM1D3~0: PWM1 duty low nibble data
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Preliminary
TonTouchTM
PWM1H[01BH]: PWM1 duty high nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM1D7
R/W
Bit2
PWM1D6
R/W
Bit1
PWM1D5
R/W
Bit0
PWM1D4
R/W
PWM1D7~4: PWM1 duty high nibble data
PWM2L[01CH]: PWM2 duty low nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM2D3
R/W
Bit2
PWM2D2
R/W
Bit1
PWM2D1
R/W
Bit0
PWM2D0
R/W
PWM2D3~0: PWM2 duty low nibble data
PWM2H[01DH]: PWM2 duty high nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM2D7
R/W
Bit2
PWM2D6
R/W
Bit1
PWM2D5
R/W
Bit0
PWM2D4
R/W
PWM2D7~4: PWM2 duty high nibble data
PWMxEN
PWMx
TCP2 COUNT
PWMxO
Duty Compare
8-bits duty
TCP2OV
8-bits duty PWMxD
Low duty
High duty
Write PWMxL
Write PWMxH
High duty tmp
Figure: Timer/Counter/PWM
Table: PWM duty
PWMxD
PWM duty
(0 * clock cycle) / TCP2 timer’s period
(1 * clock cycle) / TCP2 timer’s period
(2 * clock cycle) / TCP2 timer’s period
….
Note
All off
0
1
2
….
n
….
((n) * clock cycle) / TCP2 timer’s period
….
TCP2D
((TCP2D) * clock cycle) / TCP2 timer’s period
All on
Note:
1. PWMxD cannot bigger than TCP2D
2. TCP2 timer’s period = (TCP2D) * clock cycle.
3. PWM can start 0 or start 1 by option.
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Preliminary
. I/O PAD Cell Structure & Function Description
Input Port
The input port can be programmed as input with pull-up resistor and input
data can read by port reading command. Then a wake-up function also offers
the system wake up feature for keys or special external triggers then a wake-up
function also offers the system wake up feature for keys or special external
triggers.
Input Data
Pull-up
Read Data
Wake-up
Active
0
R
No
R
0
0
1
1
1
?
0
Inhibited
Non-active
1
1
No
R
Inhibited
Floating
Floating
Non-active
Inhibited
No
R: pull-up resistor
X: don’t care the value
?: unknown
Pull-High R
Wake-up
P
PAD
Read
Data
External Input
Figure IO-E: Input Port
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Preliminary
I/O Port with external input
The input/output port has the I/O control register for switching input or
output mode and output data register stores the output data in output mode. If
control register=1 and output data=1, the I/O port is programmed as input
with pull-up resistor and also actives the wake-up function. User intends to read
the port data with differed read instruction. The read PI is reading data comes
from PAD input data. The data register reading result will have the same value
with output register data. Software can performs a configuration (data=0,
changing the control 0 or 1) for open drain type that specifies suitable for key
scan application. An additional feature supports the interrupt input triggers and
Timer external clock sources.
I/O control Data Output data Pull-up R Wake-up feature External inputs
0
X
0
1
No
No
Enable
No
No
Enable
No
Enable
Enable
1
1
X: don’t care the value
I/O control Data
MODE
Output mode
Input mode
PAD
0
1
Output Register data
Input data
Read PI
Read Input Data
Output Register data
PAD input data
0
1
Pull-up R
P
Data Bus
S
D
Q
CK QB
I/O control Register Write
PR
S
P
D
Q
P
Output Data Register Write
Read PI
CK QB
N
M
U
X
0
1
Read
Wake-up
N
N
Timer/counter external clock
External interrupt
Figure IO-A: Standard IO Port with wake-up/interrupt/timer clock inputs
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Preliminary
I/O port with internal output
The standard input/output port has the I/O control register for switching
input or output mode and output data register stores the output data in output
mode. If control data=1 and output data=1, the I/O port is programmed as
input with pull-up resistor and also actives the wake-up function. User intends
to read the port data with differed read instruction. The read PI is reading data
comes from PAD input data. The data register reading result will have the same
value with output register data. If enable internal output, the internal output
will control by output data (on/off) and outputs to PAD.
I/O control Data
Output data
Pull-up
No
Wake-up
No
0
X
0
1
1
1
No
No
Enable
Enable
X: don’t care the value
I/O control Data
Internal output
PAD
0
enable
disable
X
Output internal data
Output Register data
PAD input data
0
1
X: don’t care the value
Read PI
Mode
Output mode
Input mode
Read Input Data
Output Register data
PAD input data
0
1
Pull-up R
P
S
Data Bus
D
Q
CK QB
I/O ctrl Register Write
PR
S
P
D
Q
CK QB
Data Register Write
Read PI
N
PAD
M
U
X
0
Read
Wake-up
N
N
Internal output signal
MUX
Output enable (PWMEN)
Figure IO-B: Standard I/O Port with internal output signal
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TTP258
TonTouchTM
Preliminary
Standard I/O Port
The standard input/output port has the I/O control register for switching
input or output mode and output data register stores the output data in output
mode. If control data=1 and output data=1, the I/O port is programmed as
input with pull-up resistor and also actives the wake-up function. User intends
to read the port data with differed read instruction. The read PI is reading data
comes from PAD input data. The data register reading result will have the same
value with output register data. Software can performs a configuration (data=0,
changing the control 0 or 1) for open drain type that specifies suitable for key
scan application.
I/O control Data
Output data
Pull-up
No
Wake-up
No
0
X
0
1
1
1
No
No
Enable
Enable
X: don’t care the value
I/O control Data
MODE
Output mode
Input mode
PAD
0
1
Output Register data
Input data
Read PI
Read Input Data
Output Register data
PAD input data
0
1
Pull-High R
P
S
Data Bus
D
Q
I/O control Register Write
CK
QB
PR
S
P
D
Q
PAD
Output Data Register Write
Read PI
CK QB
N
M
U
X
0
Wake-up
1
Read
N
N
Figure IO-C: Standard I/O Port
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
I/O port with internal output & external input
The standard input/output port has the I/O control register for switching
input or output mode and output data register stores the output data in output
mode. If control data=1 and output data=1, the I/O port is programmed as
input with pull-up resistor and also actives the wake-up function. User intends
to read the port data with differed read instruction. The read PI is reading data
comes from PAD input data. The data register reading result will have the same
value with output register data. If enable internal output, the internal output
will control by output data (on/off) and outputs to PAD.
I/O control Data
Output data
Pull-up
No
Wake-up
No
0
X
0
1
1
1
No
No
Enable
Enable
X: don’t care the value
I/O control Data
Internal output
PAD
0
0
1
enable
disable
X
Output internal data
Output Register data
PAD input data
X: don’t care the value
Read PI
Mode
Output mode
Input mode
Read Input Data
Output Register data
PAD input data
0
1
Pull-up
Data Bus
S
D
Q
P
CK
QB
I/O ctrl Register Write
PR
S
P
D
Q
Data Register Write
Read PI
CK
QB
N
PAD
M
U
X
Read
Wake-up
N
N
Timer/counter external clock
External interrupt
Internal output signal (PWM)
Output enable
Figure IO-D: Standard I/O Port with internal output signal & external input
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
S
Pull-up
Data Bus
D
Q
R
R
CK QB
I/O ctrl Register
Write
PR
S
P
D
Q
Data Register
Write
CK QB
N
PAD
Read PI
0
1
M
U
X
Read
Wake-up
N
N
External interrupt
MUX
Internal output signal
(PWM)
MUX
INTTS
VBGAP
Output enable
(PWMEN)
Figure IO-E: Standard I/O Port with internal output signal & external input
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
3. I/O Pad Cells
The main features of pad cell are including ESD/EFT protection and
general I/O access. A general I/O pad cell can be configured as input with or
without pull-up resistor, or working as a CMOS or NMOS output driver. The input
pad cell must have pull-up resistor for avoiding a floating state when user
doesn’t care or not be used. For concerning the standby current, user can use
data register or I/O control register to fit the application.
. I/O File Register
PAC[012H]: Port A I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
PAC2
R/W
Bit1
PAC1
R/W
Bit0
PAC0
R/W
-
-
PAC2~PAC0: port A I/O control data
PA[013H]: Port A data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
PA2
R/W
Bit1
PA1
R/W
Bit0
PA0
R/W
-
-
PA2~PA0: port A data
PBC[014H]: Port B I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
PBC1
R/W
Bit0
PBC0
R/W
-
-
-
-
PBC1~PBC0: port B I/O control data
PB[015H]: Port B data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
PB1
R/W
Bit0
PB0
R/W
-
-
-
-
PB1~PB0: port B data
PCC[016H]: Port C I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PCC3
R/W
Bit2
PCC2
R/W
Bit1
PCC1
R/W
Bit0
PCC0
R/W
PCC3~PCC0: port C I/O control data
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TTP258
TonTouchTM
Preliminary
PC[017H]: Port C data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PC3
R/W
Bit2
PC2
R/W
Bit1
PC1
Bit0
PC0
R/W
R/W
PC3~PC0: port C data
PDC[018H]: Port D I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PDC3
R/W
Bit2
PDC2
R/W
Bit1
PDC1
R/W
Bit0
PDC0
R/W
PDC3~PDC0: port D I/O control data.
PD[019H]: Port D data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PD3
R/W
Bit2
PD2
R/W
Bit1
PD1
R/W
Bit0
PD0
R/W
PD3~PD0: port D data
PAI[206H]: Port A pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
Bit2
PAI2
R
Bit1
PAI1
R
Bit0
PAI0
R
-
-
PAI2~PAI0: port A pad data
PBI[207H]: Port B pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
PBI1
R
Bit0
PBI0
R
-
-
-
-
PBI1~PBI0: port B pad data
PCI[208H]: Port C pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PCI3
R
Bit2
PCI2
R
Bit1
PCI1
R
Bit0
PCI0
R
PCI3~PCI0: port C pad data
PDI[209H]: Port D pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PDI3
R
Bit2
PDI2
R
Bit1
PDI1
R
Bit0
PDI0
R
PDI3~PDI0: port D pad data
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
. IO Port’s Special function
When SpecIO’s is selected by mask option, PA0~PA2 is special function. It
can ouput ODATA register to user. ODATA can be store Key touch information
by software. PA0 is input port, PA2 & PA3 is output. User can use this function
to get Key touch information.
ODATA[21AH]: Touchkey output register for special function [R/W], default value [0000]
Register
Bit3
ODATA3
R/W
Bit2
ODATA2
R/W
Bit1
ODATA1
R/W
Bit0
ODATA0
R/W
Bit Name
Read/Write
ODATA3~0: Touchkey information
PA0 (input)
PA1 (output)
PA2(output)
1
0
ODATA0
ODATA2
ODATA 1
ODATA 3
16’/04/06
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
10 non-contact inputs touch pad detector
The touch pad detector applies the charge sharing conception. The inputs
share the pad with IO ports. Built-in charge sharing control, duty detector and
de-bounce feature can response the input with varied output refresh rate that
dependant on the system request. For power saving concern, auto power off
function and wake up de-bounce capability can support a lower average
operating current.
Modulation
OSCH/
clock selector
OSCL
Data Bus
Edge
Clock
CH0
Detector
Gating
CH1
:
12 bits Duty counter &
Reload data latch
TPCTF
:
:
:
Key scan & Timing control
CH8
CH9
TPCMPF
Touch pad selector
Touch available Pad
Figure: 10 keys Touch pad detector
Parameters
Touch pad OSC
Modulation clock
Duty counter
Target value
Remark
Using OSCH or OSCL
N=1,2,4,8,16,32,64,OSCL
With INT
4MHz or 16KHz (typ.)
OSCH/N or OSCL
12 bits
Reload data latch
Touch pads
12 bit
1~10 keys
Write only
Mask option
Key de-bounce time
Sensitivity level
s/w implements
Offset value by s/w
By application or cover thickness
Resolution=1 modulation clock
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
The state machine of sequence control is simplified as:
Wait Å----
|___no__|
|
|
|
Initial C
Reload Duty counter (clear TPCTF & TPCMPF)
|
|
Enable counter
|
Wake-up condition (TPCMPF=1 | TPCTF=1 ) ---Æ wake up
|
Wait
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
TPINTC[01EH]: Touchpad interrupt control register [R/W], default value [0000]
TPINTC
Bit Name
Read/Write
Bit3
TPCTIE
R/W
Bit2
TPCMPIE
R/W
Bit1
Bit0
-
-
-
-
TPCMPIE: Capacitor overcharge interrupt enable. (0: disable; 1: enable)
TPCTIE: Duty counter overflow interrupt enable. (0: disable; 1: enable)
TPINTF[01FH]: Touchpad request flag register [R/W], default value [0000]
TPINTF
Bit Name
Read/Write
Bit3
TPCTF
R/W
Bit2
TPCMF
R/W
Bit1
Bit0
-
-
-
-
TPCMPF: Capacitor overcharge’s flag. (0: inactive; 1: active)
TPCTF: Duty counter’s overflow flag. (0: inactive; 1: active)
TPCT0[213H]: Touch pad duty counter & latch data register 0 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT3/CT3
R/W
Bit2
TPCT2/CT2
R/W
Bit1
TPCT1/CT1
R/W
Bit0
TPCT0/CT0
R/W
TPCT3~TPCT0: Duty counter 1st nibble for counter read
CT3~CT0: 1st nibble of reload latch data
TPCT1[214H]: Touch pad duty counter & latch data register 1 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT7/CT7
R/W
Bit2
TPCT6/CT6
R/W
Bit1
TPCT5/CT5
R/W
Bit0
TPCT4/CT4
R/W
TPCT7~TPCT4: Duty counter 2nd nibble for counter read
CT7~CT4: 2nd nibble of reload latch data
TPCT2[215H]: Touch pad duty counter & latch data register 2 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT11/CT11 TPCT10/CT10
R/W R/W
Bit2
Bit1
TPCT9/CT9
R/W
Bit0
TPCT8/CT8
R/W
TPCT11~TPCT8: Duty counter 3rd nibble for counter read
CT11~CT8: 3rd nibble of reload latch data
Duty counter value= TPCT2*256 +TPCT1*16+TPCT0
The duty counter will be enabled by writing the TPCHS0 register and will set
the TPCTF flag if duty counter overflow. As writing any of the TPCHS0
addresses will reload the 12 bit counters and clear the TPCTF & TPCMPF.
16’/04/06
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Ver.: 1.2
TTP258
TonTouchTM
Preliminary
MCKS[20EH]: Modulation clock selector register [R/W], default value [0111]
Register
Bit Name
Read/Write
Bit3
Bit2
MCKS2
R/W
Bit1
MCKS1
R/W
Bit0
MCKS0
R/W
-
-
MCKS2~MCKS0: Modulation clock selector
MCKS2 ~ MCKS0 Sample time MCKS2 ~ MCKS0 Sample time
000
001
010
011
OSCH/1
OSCH/2
OSCH/4
OSCH/8
100
101
110
111
OSCH/16
OSCH/32
OSCH/64
OSCL
The TPCMPF will be set as no modulation clock going into duty counter
with de-bounce feature and will also call the interrupt as TPCMPIE=1 .
TPCHS0[20FH]: Touch pad channel selector register0 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TPEN3
R/W
Bit2
TPEN2
R/W
Bit1
TPEN1
R/W
Bit0
TPEN0
R/W
TPEN3~TPEN0: Touch pad channel selector 1st nibble
TPCHS1[210H]: Touch pad channel selector register1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TPEN7
R/W
Bit2
TPEN6
R/W
Bit1
TPEN5
R/W
Bit0
TPEN4
R/W
TPEN7~TPEN4: Touch pad channel selector 2nd nibble
TPCHS2[211H]: Touch pad channel selector register2 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
TPEN9
R/W
Bit0
TPEN8
R/W
-
-
-
-
TPEN9~TPEN8: Touch pad channel selector 3rd nibble
As program writes the TPCHS0 register hardware automatically discharges
the external capacitor and enables the sensor clock input until period end.
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Ver.: 1.2
TTP258
Preliminary
TonTouchTM
TPCHS0
TPEN3~0
0001
TPCHS1
TPCHS2
Channel Enable State
TPEN7~4
0000
TPEN9~8
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
00
00
00
00
00
00
00
00
01
10
0010
0000
0100
0000
1000
0000
0000
0001
0000
0010
0000
0100
0000
1000
0000
0000
0000
0000
When TPCHS0 is writing, TPCTL will be set TP RUN mode, and touchpad
begin to scan touchpad
Users can enable multi-channel by setting corresponding bit 1, which will
turn on all enable channel at the same time.
TPCTL[212H]: Touch pad control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
TPCTL2
R/W
Bit1
TPCTL1
R/W
Bit0
TPCTL0
R/W
-
-
TPCTL2~TPCTL0: Touch pad control selector
As program writes the TPCTL register hardware automatically discharges the
external capacitor and enables the sensor clock input until period end.
TPCTL2 ~ TPCTL0
Channel Enable State
000
001
010
011
100
101
110
111
TP STOP
TP RUN
-
Discharge
Inner Key
-
-
-
TP STOP: STOP the touch pad feature and release pad for IO port
TP RUN: TP RUN is touchpad scan start signal, its scan the channel by TPCHS2~0 select.
Inner Key: Select switch select Inner Key. Inner Key is reference Key, this pad is no bounding
to package.
Discharge: Discharge can hold touchpad in discharge state, to avoid discharge time too short.
As touch pad analog switch keeps on, the relative IO port should be disabled
as tri-state by hardware.
In user selection table, the available touch pads will be generated a ROM
code in option ROM.
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TTP258
TonTouchTM
Preliminary
CSA[217H]: select Capacity load register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
CSA3
R/W
Bit2
CSA2
R/W
Bit1
CSA1
R/W
Bit0
CSA0
R/W
CSA3~CSA0: Select Capacity for touch pad
CSA3 ~CSA0
0000
Capacity Load
0 pf
CSA3 ~ CSA0
1000
Capacity Load
4.0 pf
0001
0.5 pf
1001
4.5 pf
0010
1.0 pf
1010
5.0 pf
0011
1.5 pf
1011
5.5 pf
0100
2.0 pf
1100
6.0 pf
0101
2.5 pf
1101
6.5 pf
0110
3.0 pf
1110
7.0 pf
0111
3.5 pf
1111
7.5 pf
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Page 41 of 44
Ver.: 1.2
TTP258
TonTouchTM
Preliminary
§ Mask Option Table:
All the OTP mask option register can open for user to reset the initial value,
but should enable the MRO. User writes MRO address first then changes the
target mask option register data. The MRO enable will be cleared with other
writing address.
MOP0: option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
Read/Write
MOP1: PWM start level option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
Bit2
PWM2S
R/W
Bit1
PWM1S
R/W
Bit0
PWM0S
R/W
-
-
Read/Write
MOP2: INT trigger option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
INT1S1
R/W
Bit2
INT1S0
R/W
Bit1
Bit0
INT0S0
R/W
INT0S1
R/W
Read/Write
MOP3: option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
Read/Write
MOP4: LVR power on option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
LVREN
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
Read/Write
MOP5: Touch pad pin option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
Bit2
Bit1
SpecIO
R/W
Bit0
TPNIS
R/W
-
-
-
-
Read/Write
16’/04/06
Page 42 of 44
Ver.: 1.2
TTP258
TonTouchTM
Preliminary
The following table shows the mask option in this chip. All the mask options
must be defined clearly and ensure to meet user’s proper function.
No.
Mask Option
Function Descriptions
Start 0
+1
PWM0S
PWM1S
PWM2S
0
1
Start 1
+1
+1
+2
0
Start 0
1
Start 1
0
Start 0
1
Start 1
INT0F trigger type
INT0S1,INT0S0
00
01
10
11
00
01
10
11
0
Low level trigger
Falling edge trigger
Rising edge trigger
Dual edge trigger
Low level trigger
Falling edge trigger
Rising edge trigger
Dual edge trigger
TPNI use Schmitt trig output signal
TPNI use comparator output signal
LVREN disable
+2
INT1F trigger type
INT1S1,INT1S0
+1
+1
+1
TPNIS
1
LVREN select
SpecIO
0
1
LVREN enable
0
PA0~PA2 is normal IO port
1
PA0~PA2 is special function
16’/04/06
Page 43 of 44
Ver.: 1.2
TTP258
TonTouchTM
Preliminary
§ Application Circuit
Cs
LDO
VDD
VSS
CAP
C1
IO Data Out
/PWM
C2
PA0~PA2
PB0~PB1
PC0~PC3
PD0~PD3
Touch Pad
§ Package & PAD Information:
§ Ordering Form:
Package type LVRen
LVR
LDO
2.7V
2.7V
16-SOP-A
16-SOP-B
TTP258RD-AOBN
TTP258OD-FOBN
By Register
Always on
2.2V
2.2V
Modified Record:
Body:
2014/05/20：1st version
2015/10/01：Ver. 1.1 (Operating voltage)
2016/04/06：Ver. 1.2
(Page 8 OSCL & test condition；Page 20 if OSCL=16KHz；Page 24、36：typical condition)
16’/04/06
Page 44 of 44
Ver.: 1.2
相关型号：
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