UP0115P [UPI]
Controller for Low-Dropout Linear Regulator;
| 型号： | UP0115P |
| 厂家： | 
uPI Semiconductor Corp. |
| 描述： | Controller for Low-Dropout Linear Regulator |
| 文件： | 总11页 (文件大小：1047K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
uP0115P/Q/R
Controller for
Low-Dropout Linear Regulator
Features
General Description
The uP0115 is a controller specifically designed to form a Operate with 4.5V ~ 13.2V Supply Input
low dropout voltage regulator by driving an N-Channel
MOSFET. The output voltage is tightly regulated to internal
reference with 1.5% accuracy via a voltage divider. An EN
pin is provided for output voltage enable/disable control.
The uP0115P features a softstart function that adjusts
output voltage ramp up time by an external capacitor to
limit the inrush current from input voltage.
The uP0115Q/R features a power OK indication function
that is asserted high with delay when the output voltage is
within regulation.
Adjustable Output Voltage, Down to 0.8V
1.5% Initial Accuracy
Excellent Line and Load Regulation
Fast Transient Response
Chip Enable Control
Adjustable External Softstart (uP0115P)
Output Voltage Power OK Signal (uP0115Q/R)
Low External Component Count
Low Cost and Easy to Use
Other features include fast transient response, output short
circuit protection and thermal shutdown. This part is
available in a space-saving SOT23-6 package.
RoHS Compliant and Halogen Free
Ordering Information
Applications
Order Number Package Top Marking
Remark
EN and SS
Desktop PCs, Notebooks, and Workstations
Graphic Cards
uP0115PMA6
S69
S70
S71
uP0115QMA6 SOT23-6L
uP0115RMA6
EN/SS and POK
EN and POK
Low Voltage Logic Supplies
Microprocessor and Chipset Supplies
Split Plane Microprocessor Supplies
Advanced Graphics Cards Supplies
Sound Cards and Auxiliary Power Supplies
SMPS Post Regulators
Note:
(1) Please check the sample/production availability with
uPI representatives.
(2) uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirement. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.
Pin Configuration & Typical Application Circuit
EN/SS
GND
1
2
3
6
5
4
VCC
DRV
EN
1
2
3
6
5
4
VCC
DRV
EN
1
2
3
6
5
4
VCC
DRV
SS
GND
GND
FB
POK
FB
POK
FB
VIN
Enable
Disable
C2
C3
DRV
POK
EN
R3
VOUT
VCC
VCC
(uP0115P/R)
R1
R2
FB
C1
SS
(uP0115P)
C4
GND
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uP0115P/Q/R
Functional Pin Description
Pin No.
Q
Name
Pin Function
P
R
Enable Input. Pulling this pin below 0.3V turns the regulator off, reducing the quiescent current
to a fraction of its operating value.
En
1
--
1
Enable Input and Softstart. Connect this pinwith a capacitor to ground to set preferred
softstart interval. Pulling this pin under 0.3V disables the output voltage.
EN/SS --
1
2
3
--
2
3
Ground.
GND
FB
2
3
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from
the output to GND is used to set the regulation voltage as VOUT = Vref x(R1+R2)/R2 (V)
Softstart. Connect this pin with a capacitor to ground to set preferred softstart interval.
SS
4
--
4
--
4
Power OK Indication. This pin is an open-drain output and is set high impedance with 3ms
delay once VOUT reaches 92% of its rating voltage.
POK --
Driver Output. Connect this pin to the gate of external N-Channel MOSFET to form a linear
regulator.
DRV
VCC
5
6
5
6
5
Supply Input for Control Circuit. This pin provides bias voltage to the control circuitry and
6 driver for the pass transistor. For the device to regulate, the voltage on this pin must be at least
2.5V greater than the output voltage, and no less than VCC_MIN.
Functional Block Diagram
Power On
Reset
VCC
VREF
Band
Gap
uP0115P/R
DRV
EN
90%Vref
3ms
uP0115Q/R
POK
FB
Delay
Error
Amp.
VDD
Level
Shift
GND
EN/SS
SS
uP0115Q
uP0115P
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uP0115P/Q/R
Functional Description
Definitions
Consequently, the output voltage will follow softstart
voltage and ramps up to its target smoothly. Thus it
reduces the inrush current from power input. The output
voltage ramp up time is calculated as:
Some important terminologies for LDO are specified
below.
Dropout Voltage
V
× C
SS
The input/output voltage differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. Measured when the output
drops 2% below its nominal value. Dropout voltage is
affected by junction temperature, load current and
minimum input supply requirements.
ref
I
T
=
SS
SS
VDD
Band
Gap
Line Regulation
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average
chip temperature is not significantly affected.
ISS
VREF
Ideal
Diode
Error
Amp.
CSS
Load Regulation
The change in output voltage for a change in load current
at constant chip temperature. The measurement is made
under conditions of low dissipation or by using pulse
techniques such that average chip temperature is not
significantly affected.
DIS
Delay
EN
SS
EN Delay
Maximum Power Dissipation
The maximum total device dissipation for which the
regulator will operate within specifications.
TSS
VOUT
POK
Quiescent Bias Current
POK
Delay
Current which is used to operate the regulator chip and is
not delivered to the load.
The quiescent current IQ is defined as the supply current
used by the regulator itself that does not pass into the
load. It typically includes all bias currents required by the
LDO and any drive current for the pass transistor.
Figure 1 Softstart Mechanism
The uP0115Q/R does not provide a specified EN pin for
enable/disable control of the output voltage. However,
pulling low the EN/SS pin lower than 0.3V disables the
output voltage.
Initialization
The uP0115 automatically initiates upon the receipt of
supply input voltage. The uP0115 performs power on reset
and is ready for chip enable command as long as the supply
voltage is higher than 4.2V typically.
Output Voltage Programming
Figure 2 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply. The output voltage
is sensed through a voltage divider and regulated to
internal reference voltage VREF. The output voltage is
programmed as:
Chip Enable and Soft Start
The uP0115P features an enable pin for enable/disable
control of the chip. The EN pin is internally pulled high by
an 10uA current source. Pulling VEN lower than 0.3V
disables the chip and reduces its quiescent current down
to 15uA. Pulling VEN higher than 0.5V enables the output
voltage, providing POR is recognized.
VOUT = VREF x (R1+R2) / R1
It’s recommended to maintain 50-100uA through the
output divider network for a tight load and line regulation.
The internal voltage reference with 1.5% accuracy over
full temperature range. This commands the use of 0.5%
or better accuracy resistors to build a precision power
supply.
A 5uA current source charges the softstart capacitor and
clamps the reference voltage to the non-inverting input of
the error amplifier as shown in Figure 1.
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uP0115P/Q/R
Functional Description
VIN
Enable
Disable
C2
C3
DRV
FB
EN
VOUT
VCC
VCC
R1
R2
C1
SS
C4
GND
Figure 2. Typical application of 2.5V to 1.8V conversion
with a 5.0V control supply.
Power OK Indication
The uP0115Q/R features power OK indication with time
delay. The POK pin is an open drain output that is as-
serted high impedance with 3ms after the softstart cycle
is competed as long as the output voltage is within its
regulation band.
Output Under Voltage Protection
The DRV voltage is monitored during softstart and FB
voltage is monitored during normal operation for output
under voltage protection. The uP0115 asserts UVP if the
error amplifier saturates and DRV voltage goes to ceiling
high for 10us during softstart. This demands VCC > (VOUT
+
VTH + 1V) where VTH is the threshold voltage of the external
N-Channel MOSFET. This is to ensure that the output
voltage can follow the softstart signal and will not saturate
the error amplifier. That means a low threshold voltage
MOSFET is required for low VCC applications.
The output voltage monitors UVP when softstart cycle is
completed. The uP0115 asserts UVP if the feedback
voltage is lower than 0.5V.
The uP0115 disables the output voltage upon the triggering
of UVP. The UVP is latch-off type and can only be reset by
POR of VCC or toggling the EN pin.
Over Temperature Protection
The uP0115 consumes negligible power when normally
driving an N-Channel MOSFET. However, an over
temperature protection function is implemented for
abnormal conditions, for example, DRV short circuits to
ground. The over temperature threshold level is about
135OC with 30OC hysteresis. The uP0115 initiates another
softstart cycle after the temperature is cooled down by
30OC.
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uP0115P/Q/R
Absolute Maximum Rating
(Note 1)
Supply Input Voltage VCC ---------------------------------------------------------------------------------------------------- -0.3V to +15V
DRV Pin --------------------------------------------------------------------------------------------------------------------------- -0.3V to +15V
POK Pin -------------------------------------------------------------------------------------------------------------------------- -0.3V to +15V
Other Pins ----------------------------------------------------------------------------------------------------------------------- -0.3V to +7V
Storage Temperature Range ---------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature -------------------------------------------------------------------------------------------------------------------- 150OC
Lead Temperature (Soldering, 10 sec) ----------------------------------------------------------------------------------------------- 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) -------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ---------------------------------------------------------------------------------------------------------------- 200V
Thermal Information
Package Thermal Resistance (Note 3)
SOT23 - 6L θJA ------------------------------------------------------------------------------------------------------------- 250OC/W
SOT23 - 6L θJC ------------------------------------------------------------------------------------------------------------- 140OC/W
Power Dissipation, PD @ TA = 25OC
SOT23 - 6L ---------------------------------------------------------------------------------------------------------------------------- 0.4W
Recommended Operation Conditions
(Note 4)
Operating Junction Temperature Range -------------------------------------------------------------------------------- -40OC to +125OC
OperatingAmbient Temperature Range -------------------------------------------------------------------------------- -40OC to +85OC
Supply Input Voltage, VCC --------------------------------------------------------------------------------------------------- +4.5V to +13.2V
Electrical Characteristics
(VCC = 12V, TA = 25OC, unless otherwise specified)
Parameter
Supply Input Voltage
Supply Input Voltage
POR Threshold
Symbol
Test Conditions
Min
Typ
Max Units
VCC
VCC_RTH
VCC_HYS
ICC
VOUT = VREF
4.5
4.0
--
--
4.2
0.2
--
13.2
4.5
--
V
V
POR Hysteresis
V
Supply Input Current
Shutdown Current
VFB =0.8V
VEN = 0V
0.3
--
0.8
15
--
mA
uA
mA
mA
ISHDN
--
Driver Source Current
Driver Sink Current
Feedback Voltage
Reference Voltage
IDRV_SRC VDRV = 6V
IDRV_SNK VDRV = 6V
5
--
5
--
--
VFB
IFB
VCC = 12V
0.788
--
0.8
--
0.812
20
V
nA
Feedback Input Current
Line Regulation
∆VREF(LINE) 4.5V < VCC < 13.2V, IOUT = 0A.
by design
--
0.01
70
--
0.1
--
%/V
dB
dB
Error Amplifier Open Loop Gain
Power Supply Ripple Rejection
--
@100Hz, IOUT = 10mA, by design
50
--
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uP0115P/Q/R
Electrical Characteristics
Prameter
Symbol
Test Conditions
Min
Typ Max Units
Softstart
Softstart Source Current
POK Indication (uP0115Q/R)
FB Power OK Threshold
Power OK Hysteresis
Power Sink Capability
Power OK Delay Time
Enable
ISS
4
5
6
uA
VPOKTH
--
--
90
9
--
--
%
%
VPOKHYS
IPOK = 4mA
0.1
--
--
0.4
--
V
TPOK
VEN
IEN
From softstart end to POK set high
3
ms
Enable High Level Threshold
Enable Hysteresis
0.3
--
0.4
30
0.5
--
V
mV
uA
us
Internal Pull-High Current Source
Enable Delay
VEN = 0V
6
10
13
--
EN go High to SS go High
--
100
600
Enable De-glitch
--
--
ns
Under Voltage Protection
Under Voltage Protection
Threshold during Normal
Operation
VFB
Normal Operation
--
--
0.5
2
--
--
V
Under Voltage Protection Delay
Thermal Protection
TUVP
From UVP triggering to DRV going low
us
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TSD
--
--
135
30
--
--
OC
OC
TSDHYS
Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25OC on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
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uP0115P/Q/R
Typical Operation Characteristics
Power On from VCC
Power Off from VCC
VCC (2V/Div)
VCC (2V/Div)
V
DRV(2V/Div)
VOUT (500mV/Div)
VOUT (500mV/Div)
VDRV(2V/Div)
VSS (5V/Div)
VSS (2V/Div)
20ms/Div
10ms/Div
VIN = 5V, VOUT = 1.5V, IOUT = 10mA
Turn On Waveform
EN (5V/Div)
VIN = 5V, VOUT = 1.5V, IOUT = 50mA
Turn Off Waveform
EN (5V/Div)
VDRV(2V/Div)
VOUT(500mV/Div)
VDRV(5V/Div)
VOUT(500mV/Div)
VSS (5V/Div)
VSS (2V/Div)
20ms/Div
4ms/Div
VIN = 5V, VOUT = 1.5V, IOUT = 50mA
VIN = 5V, VOUT = 1.5V, IOUT = 50mA
Load Transient
VOUT(20mV/Div)
Iout(2A/Div)
200us/Div
VIN = 1.5V, VOUT = 1.05V, IOUT = 0A to 5A
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uP0115P/Q/R
Typical Operation Characteristics
Feedback Voltage vs. Temperature
Supply Current vs. Supply Voltage
0.9
0.85
0.8
0.40
0.35
0.30
0.25
Enable
Disable
0.20
0.15
0.10
0.05
0.00
0.75
0.7
4.5
6.5
8.5
10.5
12.5
-50
0
50
100
150
Temperature (oC)
Supply Voltage (V)
DRV Source Current vs. DRV Voltage
DRV Sink Current vs. DRV Voltage
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
DRV Voltage (V)
DRV Voltage (V)
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uP0115P/Q/R
Application Information
The uP0115 is an controller specifically designed to form θJA specified in the N-MOSFET datasheet is measured in
a low dropout voltage regulator by driving an N-Channel the natural convection at TA = 25OC. Given power
MOSFET. External components including input/output dissipation PD, ambient temperature and thermal
capacitors and pass transistors should be carefully resistance θJA, the junction temperature is calculated as:
selected to guarantee optimal performance of the linear
regulator.
Pass Transistor
AnN-Channel MOSFET is required as the pass transistor
TJ = TA + DTJA = TA + PD x qJA
To limit the junction temperature within its maximum rating,
the allowable maximum power dissipation is calculated
as:
of an low-dropout voltage regulators. No special concern
PD(MAX) = ( TJ(MAX) -TA ) /θJA
TJ(MAX)
about the threshold voltage is required when the controller
is powered by 12V voltage. Low threshold voltage is
required when the controller is powered by 5V voltage to
ensure that the controller is capable of turning on the pass
transistor. As a thumb of rule, make sure that:
VTH < VCC - VOUT + 1V.
where
is the maximum operation junction
temperature 125OC, TA is the ambient temperature and
the θJA is the junction to ambient thermal resistance. The
thermal resistance θJA highly depends on the PCB design.
Copper plane under the drain pad N-MOSFET is an
effective heatsink and is useful for improving thermal
conductivity.
Thermal resistance should also be carefully considered
as described in the related sections.
Input Capacitors
Layout Consideration
A minimum of 100uF capacitor is recommended to be
placed directly next to the drain of the pass transistors.
This allows for the regulator being some distance from
any bulk capacitance on the rail. Additionally, larger
capacitors closely to the regulator reduces VIN sag,
improving load transient response.
A minimum of 1uF ceramic capacitor is recommended to
be placed physically near the controller for bypassing the
supply input.
1. Place a local bypass capacitor as close as possible to
the VCC pin. Use short and wide traces to minimize
parasitic resistance and inductance.
2. Use large copper plane on the drain pad ofN-MOSFET
to improve the thermal performance of the voltage
regulator.
3. Connect voltage divider directly to the point where
regulation is required. Place voltage divider close to
the device.
Output Capacitors and Stability
Aminimum bulk capacitance of 470uF, along with a 0.1uF
ceramic decoupling capacitor is recommended. Increasing
the bulk capacitance will improve the overall transient
response. ESR of output capacitors should be well
considered to ensure stable operation of the device.
Thermal Considerations
Power dissipation in the pass transistor is calculated as:
PD = (VIN - VOUT) x IOUT
Take the following moderate operation condition as an
example: VIN = 3.3V, VOUT = 1.8V, IOUT = 1A averaged, the
power dissipation is:
PD = (3.3V- 1.8V) x 1A = 1.5W
This power dissipation is conducted through the package
into the ambient environment. In the process, the
temperature of the die (TJ) rises above ambient. Large
power dissipation may cause considerable temperature
raise in the pass transistor in large dropout applications.
The geometry of the package and of the printed circuit
board (PCB) greatly influences how quickly the heat is
transferred to the PCB and away from the chip. The most
commonly used thermal metrics for IC packages are
thermal resistance from the chip junction to the ambient
air surrounding the package (θJA):
θJA = ( TJ -TA ) / PD
uP0115P/Q/R-DS-F0000, Oct. 2014
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uP0115P/Q/R
Package Information
SOT23-6L Package
2.80 - 3.00
0.95 BSC
0.30 - 0.50
0.00 - 0.15
1.90 BSC
Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target.
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
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uP0115P/Q/R
Important Notice
uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete.
uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is
assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries.
COPYRIGHT (C) 2011, UPI SEMICONDUCTOR CORP.
uPI Semiconductor Corp.
Sales Branch Office
uPI Semiconductor Corp.
Headquarter
12F-5, No. 408, Ruiguang Rd. Neihu District,
Taipei Taiwan, R.O.C.
TEL : 886.2.8751.2062 FAX : 886.2.8751.5064
9F.,No.5, Taiyuan 1st St. Zhubei City,
Hsinchu Taiwan, R.O.C.
TEL : 886.3.560.1666 FAX : 886.3.560.1888
uP0115P/Q/R-DS-F0000, Oct. 2014
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11
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