UP1722PMA5-18 [UPI]
1.5MHz, 1.3A, High-Efficiency Synchronous-Rectified Buck Converter;
| 型号： | UP1722PMA5-18 |
| 厂家： | 
uPI Semiconductor Corp. |
| 描述： | 1.5MHz, 1.3A, High-Efficiency Synchronous-Rectified Buck Converter |
| 文件： | 总15页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
uP1722P/Q
1.5MHz, 1.3A, High-Efficiency
Synchronous-Rectified Buck Converter
Features
General Description
The uP1722 is a high efficiency synchronous-rectified buck
converter with internal power switches. Fixed 1.5MHz PWM
operation allows possible smallest output ripple and
external component size. With high conversion efficiency
and small package, the uP1722 is ideally suitable for
portable devices and USB/PCIE-based interface cards
where PCB area is especially concerned.
2.6V to 5.5V Input Voltge ge
1.3A Peak Output Current
Accurate Reference ith +/- 2% Accuracy
0.6V (uP17
0.5V (uP1722Q)
Up to 95% Cnsion Efficiency
Typical Quscent Current: 60uA
With internal low RDS(ON) switches, the uP1722 is capable
of delivering 1.3A peak output current over a wide input
voltage range from 2.6V to 5.5V. The output voltage is
adjustable from 0.6V/0.5V (uP1722P/uP1722Q) to VIN by
a voltage divider. Other features include internal soft-start,
chip enable, under-voltage, over-temperature and over-
current protections. The uP1722 is available in space-saving
WDFN2x2-6L, TSOT23-5L and SOT23-5L packages with
fixed or adjustable output voltage options.
Integrated Low DS(ON) Upper and Lower
MOSFitches: 300mΩ and 250mΩ
CurreodPWM Operation
Fd Frequency: 1.5MHz
imum Duty Cycle for Lowest Dropout
Soft-Start
Under-Voltage Protection
Ordering Information
Ovr-Temperature and Over-Current Protection
Order Number
uP1722PMT5-XX
uP1722QMT5-XX
uP1722PMA5-XX
uP1722QMA5-XX
Package
TopMarking
N45PXX
N45QXX
N45PXX
N45QX
Space-Saving WDFN2x2-6L, TSOT23-5L and
SOT23-5L packages
TSOT23-5L
RoHS Compliant and Halogen Free
SOT23-5L
Applications
Battery-Powered Portable Devices
uP1722PDE6-00 WDFN2x2-6L
MP3 Players
XX: Output Voltage
00: adjustable
Digital Still Cameras
10: 1.0V; 12: 1.2V; 15: 1.5V; 18: 1V;
25: 2.5V; 33: 3.3V
Wireless and DSL Modems
Personal Information Appliances
Cellular Telephones
Status:
In Production: uP1722PMA5-00, uP1722PMT5-00
Others: Please check the smple/production availability
with uPI representatives.
802.11 WLAN Power Supplies
FPGA/ASIC Power Supplies
Note:
Dynamically Adjustable Power Supply for
CDMA/WCSMA Power Amplifiers
(1) Please check the roduction availability with
uPI representatives.
(2) uPI products are compatwith the current IPC/JEDEC
J-STD-020 requiremnt. They are halogen-free, RoHS
compliant and 100% mattn (Sn) plating that are suitable
for use in SnPb or Pb-free sldering processes.
USB-Based xDSL Modems and Other Network
Interface Cards
uP1722P/Q-DS-F0002, Sep. 2016
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1
uP1722P/Q
Pin Configuration
EN
GND
LX
1
2
3
5
4
FB
VIN
GND
EN
1
2
3
5
4
LX
FB
NC
EN
FB
1
2
3
6
5
G
X
GN
VIN
VIN
(T)SOT23-5L
(T)SOT23-5L
FN2x2-6L
Typical pplication Circuit
L
VIN
VOUT
VIN
LX
C1
R
COUT
EN
VOUT
CIN
R1
GND
VIN
VOUT
CIN
L
COUT
C1
R1
R2
3.3V
1V
4.7uF
4.7uF
2.2uH
10
0uF
180pF
10K
6.8K
3.3V
1.2V
2.2H
120pF
10K
10K
3.3V
5V
1.8V
1V
4.7uF
4.7uF
4.7uF
uF
2.2u
H
2.2uH
10uF
10uF
10uF
10uF
47pF
180pF
120pF
47pF
10K
10K
10K
10K
20K
6.8K
10K
20K
5V
1.2V
1.8V
5V
5V
3.3V
4.7uF
2.2uH
10uF
27pF
15K
68K
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uP1722P/Q
Functional Block Diagram
VIN
Current
Sense
Slope
Compensation
Current Limit
Detector
VREF
Control Logic
r
LX
FB
Under
Voltage
Protection
OSC &
Shutdown
Control
For Fixed
VOUT Only
EN
GND
Functional Pin Description
Pin No.
PMT/PMA QMT/QMA
Pin
Name
Pin Function
PDE
2
Chip Enable (ive High). Logic low shuts down the converter.
1
2
3
3
2
5
EN
GND
LX
Groun. Tthe pin directly to the cathode terminal of CIN, COUT and
ground plane wh the lowest impedance.
5
4
Internal itches Output. Connect this pin to the output inductor.
upply Input. Input voltage that supplies current to the output
nd powers the internal control circuit. Bypass input voltage with
m 4.7uF X5R or X7R ceramic capacitor.
4
1
3
VIN
Switcher Feedback Voltage. This pin is the inverting input of the error
plifier. VOUT senses the switcher output through an external resistor
dder network. For the fixed voltage version, connect this pin to the
utput voltage.
5
4
6
1
FB
NC
Not Internally Connected.
--
--
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uP1722P/Q
Functional Description
The uP1722 is a high efficiency synchronous-rectified buck current to ramp up linearly. The switch remains on until
converter with internal power switches. Fixed 1.5MHz PWM either the current-limit is trippethe PWM comparator
operation allows possible smallest output ripple and turns off the switch for regulating outpoltage. The upper
external component size. With high conversion efficiency switch current is sensed, spe compensated and
and small package, the uP1722 is ideally suitable for compared with the error amplifr oOMPto determine
portable devices and USB/PCIE-based interface cards the adequate duty cycle. he pin senses output
where PCB area is especially concerned.
feedback voltage from an externaistive divider.
With internal low RDS(ON) switches, the uP1722 is capable When the load current incrses, it causes a slight
of delivering 1.3A peak output current over a wide input decrease in the feedvoltage relative to the 0.6V/0.5V
voltage range from 2.6V to 5.5V. The output voltage is reference, which in turn cathe error amplifier output
adjustable from 0.6V/0.5V to VIN by a voltage divider. Other voltage to increantil the average inductor current
features include internal soft-start, chip enable, under- matches the new oad cunt.
voltage, over-temperature and over-current protections. The
Low Dropout Mo
uP1722 is available in space-saving WDFN2x2-6L, TSOT23-
The uP1722 ases duty cycle to maintain output voltage
5L and SOT23-5L packages, in an adjustable version and
within its rion as the supply input drops gradually in
fixed output voltages.
the battery-ereapplications. The uP1722 operates with
100% y cycle and enters low dropout mode as the supply
Input Supply Voltage, VIN
VIN pin provides power for the internal control circuit and inpues the output voltage. This maximizes the
supplies current to the output voltage. The supply voltage batt
range is from 2.6V to 5.5V. A power on reset (POR)
Current Lmit Function
continuously monitors the input supply voltage. The POR
The 722 continuously monitors the inductor current for
level is typically 2.5V at VIN rising.
current limit by sensing the voltage drop across the upper
The uP1722 draws pulsed current with sharp edges each
swh when it turns on. When the inductor current is higher
time the upper switch turns on, resulting in voltage ripps
than current limit threshold (1.5Atypical), the current limit
and spikes at supply input. A minimum 1uF cermic
fction activates and forces the upper switch turning off to
capacitor with shortest PCB trace is highly recommded
limit inductor current cycle by cycle. If the load continuously
for bypassing the supply input.
demands more current than what the uP1722 could provide,
Chip Enable/Disable and Soft Start
the uP1722 can not regulate the output voltage. Eventually
under voltage protection will be triggered and shuts down
the uP1722 if VFB is too low.
Pulling EN pin lower than 0.4V shuts down 2
and reduces its quiescent current lower than 1the
shutdown mode, both upper and lowswitches are turned Under Voltage Protection
off.
Undervoltage Protection is triggered if the output voltage is
Pulling EN pin higher than 1.5V enas the u1722 and lower than 17% of its target level and shuts down uP1722.
initiates the soft start cycle. The uP1722 lts the in-rush The uP1722 can only be reset by POR of VIN or toggling
current at start-up. This prevents unwanted shutdown the EN pin.
otherwise may be triggered voltage drop due to large
inrush current.
Output Voltage Setting and Feedback Network
The output voltage can be set from VREF to VIN by a voltage
divider as:
PWM Operation
The uP1722 adopts mpensated, current mode
PWM control capable of aving 100% duty cycle.During
normal operation, the uP1722 erates at PWM mode to
regulate output voltage transferring the power to the
output voltage cycle by ycle at a constant 1.5MHz
frequency. The uP17turs on the upper switch at each
rising edge of the internal oscillator allowing the inductor
R1+ R2
VOUT
=
× VREF
R1
The internal VREF is 0.6V/0.5 with 2.0% accuracy. In real
applications, a 22pF feedforward ceramic capacitor is
recommended in parallel with R2 for better transient
response. The feedforward is internally implemented for
the fixed voltage versions.
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uP1722P/Q
Absolute Maximum Rating
(Note 1)
Supply Input Voltage, VIN --------------------------------------------------------------------------------------------- -0.3V to +6V
LX Pin Voltage
DC ------------------------------------------------------------------------------------------------------------------------------ -V to +(VIN +0.3V)
< 30ns -------------------------------------------------------------------------------------------------------------------------- -3.5V to +7V
Other Pins ---------------------------------------------------------------------------------------------------------------------- -0.3V to +6V
StorageTemperature Range ----------------------------------------------------------------------------------------- -65OC to +150OC
JunctionTemperature -------------------------------------------------------------------------------------------------------------------------------- 150OC
LeadTemperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------------------------- 200V
Thermal Information
Package Thermal Resistance (Note 3)
(T)SOT23-5LθJA --------------------------------------------------------------------------------------------------------------- 250OC/W
(T)SOT23-5LθJC ----------------------------------------------------------------------------------------------------------------- 100OC/W
WDFN2x2-6L θJA ------------------------------------------------------------------------------------------------------------------- 155OC/W
WDFN2x2-6L θJC -------------------------------------------------------------------------------------------------------------- 20OC/W
PowerDissipation, PD @ TA = 25OC
(T)SOT23-5L ---------------------------------------------------------------------------------------------------------------------------- 0.4W
WDFN2x2-6L------------------------------------------------------------------------------------------------------------------------------------ 0.6W
Recommended Operation Conditions
(Note 4)
Operating Junction Temperature Range --------------------------------------------------------------------- -40OC to +125OC
OperatingAmbientTemperature Range -------------------------------------------------------------------------------- -40OC to +85OC
Supply Input Voltage, VIN --------------------------------------------------------------------------------------------------- +2.6V to +5.5V
Electrical Characteristics
(VIN = 3.3V, TA = 25OC, unless otherwise specifie
Parameter
Symb
est Conditions
Min
Typ
Max Units
Supply Current
VIN risg
2.6
--
--
--
--
V
2
Input Under Voltage Lockout
Quiescent Current
VUVLO
IN falling
VEN = 3.3V, VFB > VREF, IOUT = 0mA, (No
switching)
IQ
--
--
60
100
1
uA
uA
Shutdown Current
Reference
ISHDN VEN = 0V
0.01
Soft-Start Time
Guaranteed by design
--
250
--
us
V
uP1722P IOUT = 10mA
uP1722Q IOUT = 10mA
0.588 0.6 0.612
0.490 0.5 0.510
Reference Voltage
VREF
Output Voltage Li
Regulation
∆VOUT VIN = 2.6V to 5.5V
∆VOUT IOUT = 10mA to 1A
--
--
0.04
0.5
0.4
--
%/V
%
Output Voltage Load
Regulation
uP1722P/Q-DS-F0002, Sep. 2016
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uP1722P/Q
Electrical Characteristics
Parameter
Oscillator
Symbol
Test Conditions
Guaranteed by design
VIN = VOUT ; VFB = 0.45V
Min
Typ Max
Units
COMP to Current Sense
Transconductance
--
2
--
A/V
Switching Frequency Range
Maximum Duty Cycle
Power Switches
fOSC
DC
1.25
00
--
1.75
--
MHz
%
RDS(ON) of Upper Switch
RDS(ON) of Lower Switch
Logic Input
RP_FET
RN_FET
VIN = 3.3V, ILX = 100mA
VIN = 3.3V, ILX = -100mA
-
--
300
250
--
--
mΩ
mΩ
EN Logic Low Threshold
EN Logic High Threshold
Protection
VIL
VIH
VIN = 2.6V to 5.5V, Shutdown
VIN = 2.6V to 5.5V, Enable
--
--
--
0.4
--
V
V
1.5
FB Under Voltage
Protection
∆FB_UVP FB Falling
--
1.3
--
0.133
1.5
--
--
--
V
A
Over Current Protection
IOUT_OCP
Thermal Shutdwon
Temperature
TSHDN
Guaranteeby den
Guaranteed by dgn
150
OC
Thermal Shutdown
Hysteresis
∆TSHDN
--
20
--
OC
Note 1. Stresses listed as the above Absolute Maximum Rngs may cause permanent damage to the device.
These are for stress ratings. Functional opeion of the device at these or any other conditions beyond those
indicated in the operational sections of the specations is not implied. Exposure to absolute maximum
rating conditions for extended periods memain possibility to affect device reliability.
Note 2. Devices are ESDsensitive. Handling recommended.
Note 3. θJA is measured in the natural convect= 25OC on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measuret standard.
Note 4. The device is not guaranted to functioutside its operating conditions.
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uP1722P/Q
Typical Operation Characteristics
Power On from EN
Power Off from EN
EN 5V/Div
EN 5V/Div
LX 5V/Div
LX 5V/Div
VOUT 1V
VOUT 1V/Div
ILX 1A/Div
IL/Div
Time (100us/Div)
Time (2us/Div)
VIN= 5V, VOUT = 1.2V, IOUT = 1A
VIN= V, VOUT = 1.2V, IOUT = 1A
Load Transient
Switching Frequency vs. Input Voltage
1.54
1.53
.52
1.51
1.50
1.49
1.48
LX 5V/Div
ILX 500mA/Div
VOUT 100mV/Div
2.6
3.1
3.6
4.1
4.6
5.1
5.6
Time (100us/Div)
VIN= 5V, VOUT = 1.2V, IOUT 0A~ 1A
Input Voltage (V)
IOUT = 500mA
Line Regulon
Load Regulation
1.26
1.24
1.22
1.2
1.242
1.232
1.222
1.212
1.202
1.192
1.182
1.172
1.162
1.152
1.18
1.16
1.14
2.6
3.1
3.6
4.1
4.6
5.1
0
0.2
0.4
0.6
0.8
1
1.2
VIN (V)
IOUT (A)
uP1722P/Q-DS-F0002, Sep. 2016
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uP1722P/Q
Typical Operation Characteristics
Efficiency vs. Output Current
100
90
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
VOUT = 1.2V
0.01
0.1
1
IOUT (A)
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uP1722P/Q
Application Information
Output Inductor Selection
Input Capacitor Selection
The uP1722 draws pulsed currewith sharp edges from
the input capacitor resulting in ripple anoise at the input
supply voltage. A minimum 4.X5R or X7R ceramic
capacitor is highly recommend the pulsed current.
The input capacitor should be plas near the device as
possible to avoid the stray ductanalong the connection
trace. Y5V dielectrics, asidom losing most of their
capacitance over temature, they also become resistive
at high frequencies. This es their ability to filter out
high frequency noi
Output inductor selection is usually based on the
considerations of inductance, rated current value, size
requirements andDC resistance (DCR).
The inductance is chosen based on the desired ripple
current. Large value inductors result in lower ripple currents
and small value inductors result in higher ripple currents.
Higher VIN or VOUT also increases the ripple current as shown
in the equation below.Areasonable starting point for setting
ripple current is ∆IL = 390mA (30% of 1.3A). For most
applications, the value of the inductor will fall in the range
of 1uH to 10uH.
The capacitor witlow ES(equivalent series resistance)
provides the smarop voltage to stabilize the input voltage
during the transient loing. For input capacitor selection,
the ceramicitors larger than 4.7uF is recommend.
The capaciust nform to the RMS current requirement.
The aximuS ripple current is calculated as:
VOUT
VIN
1
∆IL =
× VOUT × (1−
)
fOSC × LOUT
Maximum current ratings of the inductor are generally
specified in two methods: permissible DC current and
saturation current. PermissibleDC current is the allowable
DC current that causes 40OC temperature raise. The
saturation current is the allowable current that causes 10%
inductance loss. Make sure that the inductor will t
saturate over the operation conditions including temperat
range, input voltage range, and maximum output current.
possible, choose an inductor with rated current higher than
1.0A so that it will not saturate even under current imit
condition.
V
OUT ×(V − VOUT )
IN
IIN(RMAX)
×
V
IN
This formula has a maximum at VIN = 2xVOUT, where IIN(RMS)
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
or much relief. Note that the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
is makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Always consult the manufacturer if there is any
question.
The size requirements refer to the area and heigh
requirement for a particular design. For better cy,
choose a low DC resistance inductor. DCly
inversely proportional to size.
Output Capacitor Selection
The uP1722 is specifically design to operate with minimum
4.7uF X5R or X7R ceramic capacitor. The value can be
increased to improve load/line transient performance. Y5V
dielectrics, aside from losing most of their capacitance over
temperature, they also become resistive at high
frequencies. This reduces their ability to filter out high
frequency noise.
Different core materials and shapes ill change the size/
current and price/current relationshof an indur. Toroid
or shielded pot cores in ferrite or pemalloy marials are
small and don’t radiate much energy, gerally cost
more than powdered iron core inductors with similar electrical
characteristics. The choice which style inductor to use
often depends on the price vs. srequirements and any
radiated field/EMI requirets.
The ESR of the output capacitor determines the output
ripple voltage and the initial voltage drop following a high
slew rate load transient edge. The output ripple voltage
can be calculated as:
1
∆VOUT = ∆IC ×(ESR +
)
8× fOSC × COUT
uP1722P/Q-DS-F0002, Sep. 2016
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uP1722P/Q
Application Information
where fOSC = operating frequency, COUT = output capacitance It is helpful to analysis the power dissipation of uP1722 for
and ∆IC = ∆IL = ripple current in the inductor.
avoiding the uP1722 from exceeg the maximum junction
temperature. In typical applications, e conduction loss
dominates the total power loss iuP1722. The conduction
loss has its maximum at high uty, low input voltage,
and high ambient temperaturs.
The ceramic capacitor with low ESR value provides the low
output ripple and low size profile. Connect a 4.7uF ceramic
capacitor at output terminal for good performance and place
the input and output capacitors as close as possible to the
device.
Consider the uP1722 in drout mode operation at an input
voltage of 2.6V, a load curren400mA and an ambient
temperature of 75OC. on-resistance of the upper switch
is about 500mΩ at this coion. Therefore the power
dissipation PD is:
Using Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
available in smaller case sizes. Their high ripple current,
high voltage rating and low ESR make them ideal for
switching regulator applications. Because the uP1722
control loop does not depend on the output capacitor’s ESR
PD = IO2 UT × RDS) = 80mW
This results 50 x 0.08 = 20OC temperature raise at
junction. ctn temperature is 95OC and is lower
than its maum ting 125OC.
for stable operation, ceramic capacitors can be used to
achieve very low output ripple and small circuit size.
However, care must be taken when these capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VIN. At best, this ringing can
couple to the output and be mistaken as loop instabilityt
worst, a sudden inrush of current through the long wire
can potentially cause a voltage spike at VIN, large enough
to damage the part.
CheckTransient Response
The loop response can be checked by looking at
the lsient response. Switching regulators take
veral cycles to respond to a step in load current. When
a loatep occurs, VOUT immediately shifts by an amount
equal to (∆IOUT x ESR), where ESR is the effective series
retance of COUT. ∆IOUT also begins to discharge or charge
COUT, which generates a feedback error signal. The regulator
p then acts to return VOUT to its steady state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
When choosing the input and output ceramic capaors,
choose the X5R or X7R dielectric formulations. The
dielectrics have the best temperature and tage
characteristics of all the ceramics for a gived
size.
Thermal Considerations
In most applications, the uP1722 ds not disste much
heat due to its high efficiency. Howeer, overteperature
protection is implemented in case of ons where
the uP1722 is operating at high ambient temperature. If
the junction temperature reaes approximately 150OC, the
OTP turns both power switches aet the LX node become
high impedance. The uPrestores normal operation
if the junction temperas to 130OC.
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uP1722P/Q
Application Information
Examples of 2-layer PCB layout are shown in Figure1, 2
and 3 for different part number, pectively.
PCB Layout Considerations
High switching frequencies and relatively large peak
currents make the PCB layout a very important part of
switching mode power supply design. Good design
minimizes excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can result in
instability or regulation errors. Follow the PCB layout
guidelines for optimal performance of uP1722.
Via to VIN
FB
1
2
3
5
4
Via to GND
Via to VOUT
c
GND
LX
1 For the main current paths, keep their traces short,
direct and wide.
Via to VIN
VIN
2 Put the input/output capacitors as close as possible to
the device pins.
Via for GND
3 LX node is with high frequency voltage swing and should
be kept in small area. Keep analog components away
from LX node to prevent stray capacitive noise pick-up.
VOUT
Via to V
Fig1. Top Layer Layout Example for uP1722PMT5
and uP1722PMA5
4 Connect feedback network behind the output capacitors.
Place the feedback components near the uP1722 and
keep the loop area small. .
VIN
5 A ground plane is preferred, but if not available, keep
the signal and power grounds sepregated with smll
signal components returning to theGNDpin at one poin
They should not share the high current path of CIN or
VIN
GND
EN
LX
FB
1
2
3
5
4
COUT
.
6 Flood all unused areas on all layers with coper.
Flooding with copper will reduce the temperature e
of power components. These copper areas should be
connected to VIN orGND.
Via to VIN
VOUT
Figure 2. Top Layer Layout Example for uP1722QMT5
and uP1722QMA5
6
5
4
NC
EN
1
2
3
FB
GND
GND
LX
VIN
VIN
VOUT
Figure 3. Top Layer Layout Example for uP1722PDE6
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uP1722P/Q
Package Information
TSOT23-5L Package
2.80 - 3.02
0.95 BSC
0.30 - 0.51
1.00 MAX
0.00
1.90 BSC
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimensior dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for use only. This value is not a device specification.
TYP. Typical. Provided as a general value. Tis not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash protrusions. Mold flash or protrusions shall not exceed 0.15mm.
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uP1722P/Q-DS-F0002, Sep. 2016
www.upi-semi.com
uP1722P/Q
Package Information
SOT23-5L Package
2.80 - 3.00
0.95 BSC
0.30 - 0.50
0.00 - 0
1.90 BSC
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimensior dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for use only. This value is not a device specification.
TYP. Typical. Provided as a general value. Tis not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash protrusions. Mold flash or protrusions shall not exceed 0.15mm.
uP1722P/Q-DS-F0002, Sep. 2016
www.upi-semi.com
13
uP1722P/Q
Package Information
WDFN2x2-6L Package
1.90 - 2.10
1.15 - 1.65
0.30 - 0.40
4
6
3
1
0.65 BSC
0.20 - 0.35
0.70 - 0.80
0.20 REF
0.00 - 005
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimensior dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for use only. This value is not a device specification.
TYP. Typical. Provided as a general value. Tis not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash protrusions. Mold flash or protrusions shall not exceed 0.15mm.
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uP1722P/Q-DS-F0002, Sep. 2016
www.upi-semi.com
uP1722P/Q
ImportantNotice
uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other cges to its products
and services at any time and to discontinue any product or service without notice. Customers should obtailatest relevant information
before placing orders and should verify that such information is current and complete.
uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledmeever, no responsibility
is assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other righof third paich may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of uPI or its bsidiarie
COPYRIGHT (C) 2011, UPI SEMICONDUCTOR CORP.
uPI Semiconductor Cor
Headquarter
uPI Semiconductor Corp.
Sales Branch Office
9F.,No.5, Taiyuan 1st St. Zubei City,
Hsinchu Taiwan, R..
12F-5, No. 408, Ruiguang Rd. NeihuDistrict,
Taipei Taiwan, R.O.C.
TEL : 886.3.560.1666 FAX : 886.3.560.1888
TEL : 886.2.8751.2062 FAX : 886.2.8751.5064
uP1722P/Q-DS-F0002, Sep. 2016
www.upi-semi.com
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