UP8206PDX8-D1 [UPI]
Battery Protection IC;
| 型号： | UP8206PDX8-D1 |
| 厂家： | 
uPI Semiconductor Corp. |
| 描述： | Battery Protection IC 电池 |
| 文件： | 总24页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
uP8206
Battery Protection IC
for 2-Serial to 4-serial-Cell Pack (Secondary Protection)
Features
General Description
The uP8206 series is used for secondary protection of
lithium-ion rechargeable batteries, and incorporates a high-
accuracy voltage detection circuit and a delay circuit. Short-
circuits between cells accommodate series connection of
two to four cells.
High-Accuracy Voltage Detection Circuit for Each
Cell
Overcharge Detection Voltage n (n = 1 to 4)
4.0V to 4.6V (in 50 mV steps)
Accuracy :+25 mV (+25OC),
Applications
Accuracy : +30 mV (-5OC to +55OC)
Overcharge Hysteresis Voltage n (n = 1 to 4)
0.38 +0.15V
Lithium-ion Rechargeable Battery Packs (for
Secondary Protection)
Notebook Computers
Portable Instrumentation
Portable Equipment
Delay Time for Overcharge Detection Can be Set
by an Internal Circuit Only (External Capacitors
are Unnecessary)
Output Control Function via CTL Pin
Pin Configuration
High Withstand Voltage Devices Absolute
Maximum Rating: 28V
VDD
SENSE
VC1
1
2
3
4
CO
8
7
6
5
Wide Operating Voltage Range 4V to 24V
CTL
VSS
VC3
Wide Operating Temperature Range -40OC to
+85OC
VC2
Low Current Consumption
UUTDFN1.97x2.46 – 8L
At 3.5V for Each Cell 5.0uA Max. (+25OC)
At 2.3V for Each Cell 4.0uA Max. (+25OC)
VDD
SENSE
VC1
1
2
3
4
8
7
6
5
CO
RoHS Compliant and Halogen-Free
CTL
VSS
VC3
VC2
TSSOP– 8L
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uP8206
Ordering Information
Order Number
Package
Top Marking
ECPXY
Note
Code X: Over-Charge Detection Voltage
A: 4.30V; B: 4.35V; C: 4.40V; D: 4.45V; E: 4.50V
F: 4.55V;G: 4.60V
uP8206PDX8-XY UUTDFN1.97x2.46-8L
Code Y: Over-Charge Detection Delay Time
1: 6.5s; 2: 3.5s; 3: 4s
uP8206ATA8-XY
Note:
TSSOP-8L
8206AXY
(1) Please check the sample/production availability with uPI representatives.
(2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS
compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes.
Marking Rule
Line1: Product Code
ECPXY
-ECP: Product Code
-XY: Version Code
Line2: Lot Number
aaa bbb
UUTDFN1.97x2.46 - 8L
Line1: Product Code
8206AXY
-8206A: Product Code
-XY: Version Code
Line2: Lot Number
aaa bbb
TSSOP - 8L
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uP8206
Functional Pin Description
Pin No.
Pin Name
VDD
Pin Function
Positive Power Input Pin.
1
2
Positive Voltage Connection Pin of Battery 1.
SENSE
Negative Voltage Connection Pin of Battery 1.
Positive Voltage Connection Pin of Battery 2.
3
4
5
6
VC1
VC2
VC3
VSS
Negative Voltage Connection Pin of Battery 2.
Positive Voltage Connection Pin of Battery 3.
Negative Voltage Connection Pin of Battery 3.
Positive Voltage Connection Pin of Battery 4.
Negative Power Input Pin.
Negative Voltage Connection Pin of Battery 4.
CO Output Control Pin.
7
8
CTL
CO
FET Gate Connection Pin for Charge.
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uP8206
Functional Block Diagram
VDD
Overcharge
detection
SENSE
comparator 1
Oscillator
Reference voltage
1
VC1
Overcharge
detection
comparator 2
Overcharge
detection/release
delay circuit
Reference voltage
2
VDD
Control
Logic
VC2
Overcharge
detection
comparator 3
Reference voltage
3
CO
VC3
Overcharge
detection
comparator 4
Reference voltage
4
VSS
CTL
4
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uP8206
Example of Application Circuit
1. Overheat Protection Via PTC
SC Protector
EB+
RVDD
VDD
CVDD
R1
SENSE
VC1
BAT1
C1
C2
C3
C4
R2
BAT2
R3
VC2
BAT3
R4
VC3
CO
BAT4
VSS
CTL
CCTL
PTC
EB-
Cautions
1. The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual
application.
2. Apull-down resistor is included in the CTLpin. To perform overheat protection via the PTC in the uP8206A/P Series,
connect the PTC before connecting batteries.
3. When the power fluctuation is large, connect the power supply of the PTC to the VDDpin of the uP8206A/P Series.
4. Cell connections: To prevent incorrect output activation, the VSS pin must be connected first. Connect sequences
must be used as following:
4-series cell configuration
BAT4 J BAT3 J BAT2 J BAT1
3-series cell configuration
BAT3 J BAT2 J BAT1
2-series cell configuration
BAT2 J BAT1
uP8206-DS-F0001, Apr. 2018
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5
uP8206
Test Circuit
(1) Test Condition 1, Test Circuit 1
(4) Test Condition 4, Test Circuit 2
Set V1, V2, V3, and V4 to 3.5V. Overcharge detection In the uP8206A/P Series, set V1, V2, V3, and V4 to 3.5V
voltage 1 (VCU1) is the V1 voltage when CO is H after the and V5 to 14V. The CTL pin response time (tCTL) is the
voltage of V1 has been gradually increased. The overcharge period from when V5 reaches 0 V after V5 is in a moment
hysteresis voltage (VHC1) is the difference between V1 and of time (within 10us) decreased down to 0V to when CO
VCU1 when CO is L after the voltage of V1 has been gradually becomes H.
decreased. Overcharge detection voltage VCUn (n = 2 to 4)
(5) Test Condition 6, Test Circuit 2
and overcharge hysteresis VHCn (n = 2 to 4) can be
Set V1, V2, V3, and V4 to 3.5V and V5 to 0V. The CTL
determined in the same way as when n = 1.
input H voltage (VCTLH) is the maximum voltage of V5 when
CO is L after V5 has been gradually increased. Next, set
(2) Test Condition 2, Test Circuit 1
Set V1, V2, V3, and V4 to 3.5V and in a moment of time V5 to 14V. The CTL input L voltage (VCTLL) is the minimum
(within 10us) increase V1 up to 5.0V. The overcharge voltage of V5 when CO is H after V5 has been gradually
detection delay time (tCU) is the period from whenV1 reached decreased.
5.0V to when CO becomes H. After that, in a moment of
time (within 10us) decrease V1 down to 3.5V. The
overcharge release delay time (tCL) is the period from when
V1 has reached 3.5V to when CO becomes L.
VDD
SENSE
VC1
CO
CTL
VSS
VC3
V
(3) Test Condition 3, Test Circuit 1
V1
V2
V3
V5
V4
Set V1, V2, V3, and V4 to 3.5V and in a moment of time
(within 10us) increase V1 up to 5.0V. This is defined as the
first rise. Within tCU 20 ms after the first rise, in a moment
of time (within 10us) decrease V1 down to 3.5V and then
in a moment of time (within 10us) restore up to 5.0V. This
is defined as the second rise. When the period from when
V1 was fallen to the second rise is short, CO becomes H
after tCU has elapsed since the first rise. If the period from
when V1 falls to the second rise is gradually made longer,
CO becomes H when tCU has elapsed since the second
rise. The overcharge timer reset delay time (tTR) is the period
from V1 fall till the second rise at that time.
VC2
uP8206
Test Circuit 2
(6) Test Condition 5, Test Circuit 3
After setting V1, V2, V3, and V4 to 3.5V and V5 to 0V, in
a moment of time (within 10us) increase V5 up to 8.5V and
decrease V5 again down to 0V. When the period from when
V5 was raised to when it has fallen is short, if an overcharge
detection operation is performed subsequently, the
overcharge detection time is tCU. However, when the period
from when V5 is raised to when it is fallen is gradually
made longer, the overcharge detection time during the
subsequent overcharge detection operation is shorter than
tCU. The transition time to test mode (tTST) is the period
from when V5 was raised to when it has fallen at that time.
VDD
SENSE
VC1
CO
CTL
VSS
VC3
V
V1
V2
V3
V4
VC2
VDD
SENSE
VC1
CO
CTL
VSS
VC3
V5
uP8206
V
Test Circuit 1
V1
V2
V3
V4
VC2
uP8206
Test Circuit 3
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uP8206
Test Circuit
(7) Test Condition 7, Test Circuit 4
The current consumption during operation (IOPE) is the total
of the currents that flow in the VDD pin and SENSE pin
when V1, V2, V3, and V4 are set to 3.5V.
The current consumption during over discharge (IOPED) is
the total of the currents that flow in the VDDpin and SENSE
pin when V1, V2, V3, and V4 are set to 2.3V.
VDD
SENSE
VC1
CO
CTL
VSS
VC3
A
V1
V2
V3
V4
VC2
uP8206
Test Circuit 4
(8) Test Condition 8, Test Circuit 5
The SENSE pin current (ISENSE) is I1, the VC1 pin current
(IVC1) is I2, the VC2 pin current (IVC2) is I3, the VC3 pin
current (IVC3) is I4, and the CTL pin H current (ICTLH) is I5
when V1, V2, V3, and V4 are set to 3.5V, and V5 to 14V.
The CTL pin L current (ICTLL) is I5 when V1, V2, V3, and V4
are set to 3.5V and V5 to 0V.
VDD
SENSE
VC1
CO
CTL
VSS
VC3
I1
I5
A
A
V5
V4
V1
V2
V3
I2
A
I3
I4
VC2
A
A
uP8206
Test Circuit 5
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uP8206
Functional Description
Overcharge Detection
When the voltage of one of the batteries exceeds the
overcharge detection voltage (VCU) during charging under
normal conditions and the state is retained for the
overcharge detection delay time (tCU) or longer, CO
becomes H. This state is called overcharge.Attaching FET
to the CO pin provides charge control and a second
protection.
CTL *1
In the uP8206A/P Series, if the voltage of all the batteries
decreases below the total of the overcharge detection
voltage (VCU) and the overcharge hysteresis voltage (VHC)
and the state is retained for the overcharge release delay
time (tCL) or longer, CO becomes L.
Pull-down resistor
Overcharge Timer Reset
*1. The reverse voltage H to L or L to H of CTL pin is VDD
pin voltage -2.9V (Typ.), does not have the hysteresis.
When an overcharge release noise that forces the voltage
of the battery temporarily below the overcharge detection
voltage (VCU) is input during the overcharge detection delay
time (tCU) from when VCU is exceeded to when charging is
stopped, tCU is continuously counted if the time the
overcharge release noise persists is shorter than the
overcharge timer reset delay time (tTR). Under the same
conditions, if the time the overcharge release noise persists
tTR or longer, counting of tCU is reset once. After that, when
VCU has been exceeded, counting tCU resumes.
Caution
1. Since the CTL pin implements high resistance of 8
MΩ to 12MΩ for pull down, be careful of external
noise application. If an external noise is applied, CO
may become H. Perform thorough evaluation using
the actual application.
CTL Pin
The uP8206 Series has a control pin. The CTL pin is used
to control the output voltage of the CO pin. In the uP8206A/
P Series, the CTLpin takes precedence over the overcharge
detection circuit.
Table 1. uP8206 Control via CTL Pin
CO Pin
CTL PIN
uP8206A/P
"H"
Normal state*1
"Open"
"L"
"H"
"H"
--
"L" to "H"
"H" to "L"
--
*1. The state is controlled by the overcharge detection
circuit.
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uP8206
Functional Description
Test Mode
Timing Charts
In the uP8206 Series, the overcharge detection delay time 1. Overcharge Detection Operation
(tCU) can be shortened by entering the test mode. The test
mode can be set by retaining the VDD pin voltage 8.5V or
VCUn
VHCn
higher than the SENSE pin voltage for at least 80 ms (V1 =
Battery Voltage
V2 = V3 = V4 = 3.5V, TA = 25OC). The status is retained by
( n = 1 to 4)
the internal latch and the test mode is retained even if the
CTL Pin
VDD pin voltage is decreased to the same voltage as that
of the SENSE pin. When CO becomes “H” and when the
delay time has elapsed after overcharge detection, the latch
for retaining the test mode is reset and the uP8206 Series
exits from the test mode.
tTR or shorter
tTR or
longer
CO Pin
tCU
tCL
tCU or shorter
VDD Pin Voltage
2. Overcharge Timer Reset Operation
tTR or longer
tTR or shorter
tTR or shorter
8.5V or more
VDD, VSENSE
VCUn
SENSE Pin Voltage
VHCn
VHCn
Battery Voltage
( n = 1 to 4)
VCUn
Battery Voltage
n = 1 to 4
tTR
CO Pin
tTST = 80ms max
tCU
tCU or shorter
Test Mode
Timer reset
CO Pin
*1
tCL
*1.
During normal mode, tCU = 6.5s (Typ). In the product tCU
50ms(Typ.)
=
=
=
During normal mode, tCU = 3.5s (Typ). In the product tCU
28ms(Typ.)
During normal mode, tCU = 4.0s(Typ.). In the product tCU
32ms(Typ.)
Caution
1. Set the test mode when no batteries are
overcharged.
2. The overcharge release delay time (tCL) is not
shortened in the test mode.
3. The overcharge timer resets delay time (tTR) is not
shortened in the test mode.
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uP8206
Functional Description
Battery Protection IC Connection Example
(2) 3-serial cell
(1) 4-serial cell
SC Protector
EB+
SC Protector
EB+
RVDD
VDD
RVDD
CVDD
VDD
R1
SENSE
VC1
CVDD
BAT1
C1
C2
C3
R1
SENSE
R2
BAT1
C1
BAT2
R2
VC1
R3
VC2
BAT2
C2
BAT3
R3
VC2
VC3
CO
BAT3
BAT4
C3
C4
R4
VC3
CO
VSS
CTL
External
input
VSS
CTL
RCTL
External
input
EB-
RCTL
EB-
Table 3. Constants for 3-serial cell External Components
Table 2. Constants for 4-Serial cell External Components
No.
1
Part
R1 to R3
C1 to C3, CVDD
RVDD
Min. Typ. Max. Unit
No.
1
Part
R1 to R4
C1 to C4, CVDD
RVDD
Min. Typ. Max. Unit
0.1
0.01
50
1
10
1
kΩ
uF
Ω
0.1
0.01
50
1
10
1
kΩ
uF
Ω
2
0.1
100
2
0.1
100
3
500
3
500
4
RCTL
0
100
500
Ω
4
RCTL
0
100
500
Ω
Caution
Caution
1. The above constants are subject to change without prior
notice.
1. The above constants are subject to change without prior
notice.
2. It has not been confirmed whether the operation is normal
or not in circuits other than the above example of
connection. In addition, the example of connection shown
above and the constant will not guarantee successful
operation. Perform thorough evaluation using the actual
application to set the constant.
2. It has not been confirmed whether the operation is normal
or not in circuits other than the above example of
connection. In addition, the example of connection shown
above and the constant will not guarantee successful
operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1 to R3 and to C1 to C3 and
3. Set the same constants to R1 to R4 and to C1 to C4 and
CVDD
.
CVDD
.
4. Set RVDD, C1 to C3, and CVDD so that the condition (RVDD
)
4. Set RVDD, C1 to C4, and CVDD so that the condition (RVDD
x (C1 to C4, CVDD) > 5x10-6 is satisfied.
)
x (C1 to C3, CVDD) > 5x10-6 is satisfied.
5. Set R1 to R3, C1 to C3, and CVDD so that the condition
(R1 to R3) . (C1 to C3, CVDD) > 1x10-4is satisfied.
5. Set R1 to R4, C1 to C4, and CVDD so that the condition
(R1 to R4) . (C1 to C4, CVDD) > 1x10-4is satisfied.
6. In the uP8206A/P Series, normally input H to the
external input, and input L when setting CO to H.
6. In the uP8206A/P Series, normally input H to the
external input, and input L when setting CO to H.
7. Cell connections: To prevent incorrect output activation,
the VSS pin must be connected first. Connect sequences
must be used as following:
7. Cell connections: To prevent incorrect output activation,
the VSS pin must be connected first. Connect sequences
must be used as following:
3-series cell configuration
4-series cell configuration
BAT3 J BAT2 J BAT1
BAT4 J BAT3 J BAT2 J BAT1
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uP8206
Functional Description
(3) 2-serial cell
Precautions
Do not connect batteries charged with VCU + VHC or more.
If the connected batteries include a battery charged with
VCU + VHC or more, H may be output at CO after all pins
are connected.
SC Protector
EB+
RVDD
VDD
In some application circuits, even if an overcharged battery
is not included, the order of connecting batteries may be
restricted to prevent transient output of CO detection pulses
when the batteries are connected. Perform thorough
evaluation with the actual application circuit.
CVDD
R1
SENSE
VC1
BAT1
C1
C2
R2
BAT2
VC2
Before the battery connection, short-circuit the battery side
pins RVDD and R1, shown in the figure in “Battery
Protection IC Connection Example” .
VC3
CO
VSS
CTL
External
input
The application conditions for the input voltage, output
voltage, and load current should not exceed the package
power dissipation.
RCTL
EB-
Do not apply to this IC an electrostatic discharge that
exceeds the performance ratings of the built-in electrostatic
protection circuit.
Table 4. Constants for 2-serial cell External Components
No.
1
Part
R1 to R2
C1 to C2, CVDD
RVDD
Min. Typ. Max. Unit
uPI claims no responsibility for any disputes arising out of
or in connection with any infringement of patents owned
by a third party by products including this IC.
0.1
0.01
50
1
10
1
kΩ
uF
Ω
2
0.1
100
3
500
4
RCTL
0
100
500
Ω
Caution
1. The above constants are subject to change without prior
notice.
2. It has not been confirmed whether the operation is normal
or not in circuits other than the above example of
connection. In addition, the example of connection shown
above and the constant will not guarantee successful
operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1 to R2 and to C1 to C2 and
CVDD
.
4. Set RVDD, C1 to C2, and CVDD so that the condition (RVDD
x (C1 to C2, CVDD) > 5x10-6 is satisfied.
)
5. Set R1 to R2, C1 to C2, and CVDD so that the condition
(R1 to R2) . (C1 to C2, CVDD) > 1x10-4is satisfied.
6. In the uP8206A/P Series, normally input H to the
external input, and input L when setting CO to H.
7. Cell connections: To prevent incorrect output activation,
the VSS pin must be connected first. Connect sequences
must be used as following:
2-series cell configuration
BAT2 J BAT1
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uP8206
Absolute Maximum Rating
(Note 1)
Supply Voltage Range between VDDand VSS ------------------------------------------------------------------------ VSS -0.3V to +28V
Supply Input Voltage Range, SENSE, VC1, VC2, VC3 ------------------------------------------------------------- VSS -0.3V to +28V
CO Output Pin Voltage Range, CO ------------------------------------------------------------------------------------------------- -0.3Vto +9V
Supply Input Voltage Range, SENSE to VC1, VC1 to VC2, VC2 to VC3, VC3 to VSS ---------------------------- -0.3V to +8V
Other Pins, CTL ---------------------------------------------------------------------------------------------------------------------------- -0.3V to 28V
StorageTemperature Range ----------------------------------------------------------------------------------------------------------- -45OC to +125OC
JunctionTemperature ------------------------------------------------------------------------------------------------------------------------------------ 125OC
LeadTemperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------------------------------------- 2kV
CDM (ChargedDevice Mode) ------------------------------------------------------------------------------------------------------------------------- 1kV
Thermal Information
Package Thermal Resistance (Note 3)
UUTDFN1.97x2.46 - 8LθJA --------------------------------------------------------------------------------------------------------- 102OC/W
UUTDFN1.97x2.46 - 8LθJC --------------------------------------------------------------------------------------------------------- 20OC/W
TSSOP8 - 8L θJA ----------------------------------------------------------------------------------------------------------------------- 145OC/W
TSSOP8 - 8L θJC ------------------------------------------------------------------------------------------------------------------------ 50OC/W
PowerDissipation, PD @ TA = 25OC
UUTDFN1.97x2.46 - 8L -------------------------------------------------------------------------------------------------------------------------- 0.6W
TSSOP8 - 8L ------------------------------------------------------------------------------------------------------------------------------------- 0.625W
Recommended Operation Conditions
(Note 4)
Operating JunctionTemperature Range ------------------------------------------------------------------------------------------- -40OC to +125OC
OperatingAmbientTemperature Range ------------------------------------------------------------------------------------------- -40OC to +85OC
Supply Input Voltage, VDD,Vss ---------------------------------------------------------------------------------------------------------- 4Vto +25V
Supply Input Voltage, VC1, VC2, VC3, CTL --------------------------------------------------------------------------------------- 0V to +25V
Input Voltage, VCn - VC(n-1), (n = 1,2,3), VC0 = Vss ---------------------------------------------------------------------------- 0V to +5V
Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESDsensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25OC on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
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uP8206
Electrical Characteristics
(TA = 25oC, unless otherwise specified)
Test
Test
Parameter
Symbol
Test Conditions
Min
Typ
Max Units
Condtion Circuit
DETECTION VOLTAGE
4.20V to 4.80V, adjustable,
TA = 25oC
VCUn
0.025
-
VCUn+
VCUn
VCUn
-0.38
V
V
V
1
1
1
1
1
1
0.025
VCUn
0.030
VHCn
0.15
Overcharge Detection
Voltage(n = 1, 2, 3, 4)
VCUn
4.20V to 4.80V, adjustable,
TA = -5OC to 55OC*1
VCUn
-
+
0.030
Overcharge Hysteresis
Voltage(n = 1, 2, 3, 4)
VHCn
-
+
VHCn
0.15
uP8206XXX8-AY
uP8206XXX8-BY
uP8206XXX8-CY
uP8206XXX8-DY
uP8206XXX8-EY
uP8206XXX8-FY
uP8206XXX8-GY
4.275 4.30 4.325
4.325 4.35 4.375
4.375 4.40 4.425
4.425 4.45 4.475
4.475 4.50 4.525
4.525 4.55 4.575
4.575 4.60 4.625
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Overcharge Detection
Voltage
VCU
V
Overcharge Hysteresis
Voltage
VHC
-0.53 -0.38 -0.23
V
V
1
1
INPUT VOLTAGE
Supply Voltage
between VDD and
VSS
VDSOP
4
--
24
--
--
--
.
VDD
0.95
CTL Input "H" Voltage
VCTLH
VCTLL
--
--
V
V
6
6
2
2
.
VDD
0.4
CTL Input "L" Voltage
--
INPUT CURRENT
Current Consumption
during Operation
IOPE
V1 = V2 = V3 = V4 = 3.5V
--
--
2.5
2.0
5.0
4.0
uA
uA
7
7
4
4
Current Consumption
during Over Discharge
IOPED V1 = V2 = V3 = V4 = 2.3V
ISENSE V1 = V2 = V3 = V4 = 3.5V
SENSE Pin Current
VC1 Pin Current
VC2 Pin Current
VC3 Pin Current
--
1.5
0
3.2
0.3
0.3
0.3
uA
uA
uA
uA
8
8
8
8
5
5
5
5
IVC1
IVC2
IVC3
V1 = V2 = V3 = V4 = 3.5V
V1 = V2 = V3 = V4 = 3.5V
V1 = V2 = V3 = V4 = 3.5V
-0.3
-0.3
-0.3
0
0
V1 = V2 = V3 = V4 = 3.5V,
VCTL = VDD
CTL Pin "H" Current
CTL Pin "L" Current
ICTLH
ICTLL
1.1
1.5
--
1.8
--
uA
uA
8
8
5
5
V1 = V2 = V3 = V4 = 3.5V,
VCTL = 0V
-0.15
uP8206-DS-F0001, Apr. 2018
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13
uP8206
Electrical Characteristics
(TA = 25oC, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ Max Units
Output Current
CO = 0.1V, VDD = SENSE, SENSE-VC1
= VC1-VC2 = VC2-VC3 = VC3-VSS = 3.5V
CO Pin Sink Current
ICOL
ICOH
5
1
--
--
--
--
uA
SENSE-VC1 or VC1-VC2 or VC2-VC3 or
VC3-VSS = VCU, VCO = VCOH - 1V
CO Pin Source Current
mA
Output Voltage
SENSE-VC1 or VC1-VC2 or VC2-VC3
or VC3-VSS = VCU , VDD = 14V, IOH = 0mA
6
7
9
CO Pin Drive Voltage
VCO
V
VDD = 4.3V, CTL = 0V
1.5
2.0
--
*1. Since products are not screened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
14
uP8206-DS-F0001, Apr. 2018
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uP8206
Electrical Characteristics
TA = -40oC to 85oC
Test
Test
Parameter
Symbol
Test Conditions
Min
Typ
Max Units
Condtion Circuit
DETECTION VOLTAGE
Overcharge Detection
Voltage(n = 1, 2, 3, 4)
4.20V to 4.80V, adjustable,
TA = 25oC
VCUn
0.045
-
VCUn
0.045
+
VCUn
VHCn
VCUn
V
V
1
1
1
1
Overcharge Hysteresis
Voltage(n = 1, 2, 3, 4)
VHCn
-
VHCn
+
-0.38
0.19
0.19
uP8206XXX8-AY
uP8206XXX8-BY
uP8206XXX8-CY
uP8206XXX8-DY
uP8206XXX8-EY
uP8206XXX8-FY
uP8206XXX8-GY
4.255 4.30 4.345
4.305 4.35 4.395
4.355 4.40 4.445
4.405 4.45 4.495
4.455 4.50 4.545
4.505 4.55 4.595
4.555 4.60 4.645
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Overcharge Detection
Voltage
VCU
V
Overcharge Hysteresis
Voltage
VHC
-0.57 -0.38 -0.19
V
V
1
1
INPUT VOLTAGE
Supply Voltage
between VDD and
VSS
VDSOP
4
--
24
--
--
--
.
VDD
0.95
CTL Input "H" Voltage
VCTLH
VCTLL
--
--
V
V
6
6
2
2
.
VDD
0.4
CTL Input "L" Voltage
--
INPUT CURRENT
Current Consumption
during Operation
IOPE
V1 = V2 = V3 = V4 = 3.5V
V1 = V2 = V3 = V4 = 2.3V
--
--
2.50 5.50
uA
uA
7
7
4
4
Current Consumption
during Over Discharge
IOPED
2.00 4.10
1.50 3.74
SENSE Pin Current
VC1 Pin Current
VC2 Pin Current
VC3 Pin Current
ISENSE V1 = V2 = V3 = V4 = 3.5V
--
uA
uA
uA
uA
8
8
8
8
5
5
5
5
IVC1
IVC2
IVC3
V1 = V2 = V3 = V4 = 3.5V
V1 = V2 = V3 = V4 = 3.5V
V1 = V2 = V3 = V4 = 3.5V
-0.42
-0.42
-0.42
0
0
0
0.42
0.42
0.42
V1 = V2 = V3 = V4 = 3.5V,
VCTL = VDD
CTL Pin "H" Current
CTL Pin "L" Current
ICTLH
ICTLL
1.00 1.50 1.90
-0.18 -- --
uA
uA
8
8
5
5
V1 = V2 = V3 = V4 = 3.5V,
VCTL = 0V
uP8206-DS-F0001, Apr. 2018
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15
uP8206
Electrical Characteristics
TA = -40oC to 85oC
Parameter
Symbol
Test Conditions
Min
Typ Max Units
Output Current
CO = 0.1V, VDD = SENSE, SENSE-VC1
= VC1-VC2 = VC2-VC3 = VC3-VSS = 3.5V
CO Pin Sink Current
ICOL
ICOH
5.5
1.1
--
--
--
--
uA
SENSE-VC1 or VC1-VC2 or VC2-VC3 or
VC3-VSS = VCU, VCO = VCOH - 1V
CO Pin Source Current
mA
Output Voltage
SENSE-VC1 or VC1-VC2 or VC2-VC3 or
VC3-VSS = VCU , VDD = 14V, IOH = 0mA
5.94
1.44
7
2
9.04
--
CO Pin Drive Voltage
VCO
V
VDD = 4.3V, CTL = 0V
*1. Since products are not screened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
16
uP8206-DS-F0001, Apr. 2018
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uP8206
Electrical Characteristics
Detection Delay Time
(1) uP8206PDX8-X1, uP8206ATA8-X1 (TA = 25oC, unless otherwise specified)
Test
Test
Parameter
Delay Time
Symbol
Test Conditions
Min
Typ
Max Units
Condition Circuit
Overcharge Detection
Delay Time
tCU
tTR
5.2
6.5
7.8
s
2
3
2
4
5
1
1
1
2
3
Overcharge Timer
Reset Delay Time
3.96
6.34 10.15
ms
ms
ms
ms
Overcharge Release
Delay Time
tCL
40.65 50.78 60.94
CTL Pin Response
Time
tCTL
tTST
--
--
--
--
2.5
80
Transition Time to Test
Mode
V1 = V2 = V3 = V4 = 3.5V,
VDD >= VSENSE + 8.5V
(2) uP8206PDX8-X2, uP8206ATA8-X2
Test
Test
Parameter
Delay Time
Symbol
Test Conditions
Min
Typ
Max Units
Condition Circuit
Overcharge Detection
Delay Time
tC U
tTR
2.8
3.96
1.37
--
3.5
4.2
s
2
3
2
4
5
1
1
1
2
3
Overcharge Timer
Reset Delay Time
6.34 10.15 ms
Overcharge Release
Delay Time
tC L
1.71 2.05
ms
ms
ms
CTL Pin Response
Time
tC TL
tTST
--
--
2.5
80
Transition Time to Test
Mode
V1 = V2 = V3 =V4 = 3.5V,
VD D >= VSENSE + 8.5V
--
(3) uP8206PDX8-X3, uP8206ATA8-X3
Test
Test
Parameter
Delay Time
Symbol
Test Conditions
Min
Typ
Max Units
Condition Circuit
Overcharge Detection
Delay Time
tCU
tTR
3.2
3.15
25
--
4
4.8
s
2
3
2
4
5
1
1
1
2
3
Overcharge Timer
Reset Delay Time
3.91 4.69
31.25 37.5
ms
ms
ms
ms
Overcharge Release
Delay Time
tCL
CTL Pin Response
Time
tCTL
tTST
--
--
2.5
80
Transition Time to Test
Mode
V1 = V2 = V3 =V4 = 3.5V,
VDD >= VSENSE + 8.5V
--
uP8206-DS-F0001, Apr. 2018
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17
uP8206
Detection Delay Time
(1) uP8206PDX8-X1, uP8206ATA8-X1 (TA = -40oC to 85oC)
Test
Test
Parameter
Delay Time
Symbol
Test Conditions
Min
Typ
Max Units
Condition Circuit
Overcharge Detection
Delay Time
tCU
tTR
3.7
2
6.5
9.6
s
2
3
2
4
5
1
1
1
2
3
Overcharge Timer
Reset Delay Time
6.34 13.65
ms
ms
ms
ms
Overcharge Release
Delay Time
tCL
36.85 50.78 65.34
CTL Pin Response
Time
tCTL
tTST
--
--
--
--
3
Transition Time to Test
Mode
120
(2) uP8206PDX8-X2, uP8206ATA8-X2
Test
Test
Parameter
Delay Time
Symbol
Test Conditions
Min
Typ
Max Units
Condition Circuit
Overcharge Detection
Delay Time
tCU
tTR
1.99
2
3.5
5.16
s
2
3
2
4
5
1
1
1
2
3
Overcharge Timer
Reset Delay Time
6.34 13.65 ms
Overcharge Release
Delay Time
tCL
1.24
--
1.71 2.20
ms
ms
ms
CTL Pin Response
Time
tCTL
tTST
--
--
3
Transition Time to Test
Mode
--
120
(3) uP8206PDX8-X3, uP8206ATA8-X3
Test
Test
Parameter
Delay Time
Symbol
Test Conditions
Min
Typ
Max Units
Condition Circuit
Overcharge Detection
Delay Time
tCU
tTR
2.28
1.23
4
5.89
s
2
3
2
4
5
1
1
1
2
3
Overcharge Timer
Reset Delay Time
3.91 8.40
ms
ms
ms
ms
Overcharge Release
Delay Time
tCL
22.8 31.25
40
3
CTL Pin Response
Time
tCTL
tTST
--
--
--
--
Transition Time to Test
Mode
120
18
uP8206-DS-F0001, Apr. 2018
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uP8206
Typical Operation Characteristics
Overcharge Detection Voltage vs.
Temperature
Overcharge Release Voltage vs. Temperature
4.2
4.5
4.45
4.4
4.15
4.1
4.05
4
VC2
VC3
VC2
VC3
4.35
4.3
VSENSE
VC1
VSENSE
VC1
3.95
3.9
4.25
4.2
-40
-20
0
20
40
60
80
100
-40
-20
0
20
Temperature (OC)
VSENSE = VC1 = VC2 = VC3 = 4.35V
40
60
80
100
Temperature (OC)
VSENSE = VC1 = VC2 = VC3 = 4.05V
Current Consumption during Operation vs.
Temperature
Current Consumption during Over Discharge
vs. Temperature
5
4.5
4
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (OC)
Temperature (OC)
VSENSE = VC1 = VC2 = VC3 = 3.5V
VSENSE = VC1 = VC2 = VC3 = 2.3V
Overcharge Detection Delay Time vs.
Temperature
Overcharge Release Delay Time vs.
Temperature
7.5
7.25
7
55
54
53
52
51
50
6.75
6.5
6.25
6
5.75
5.5
-40
-20
0
20
Temperature (OC)
VSENSE = VC1 = VC2 = VC3 = 4.35V
40
60
80
100
-40
-20
0
20
Temperature (OC)
VSENSE = VC1 = VC2 = VC3 = 4.05V
40
60
80
100
uP8206-DS-F0001, Apr. 2018
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19
uP8206
Typical Operation Characteristics
CTL Input Voltage vs. Temperature
CTL Pin Response Time vs. Temperature
12
11.8
11.6
11.4
11.2
11
2
1.8
1.6
1.4
1.2
1
CTL Input “H” Voltage
CTL Input “L” Voltage
10.8
10.6
10.4
10.2
10
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (OC)
Temperature (OC)
VSENSE = VC1 = VC2 = VC3 = 3.5V, VCTL = 0V
increase and decrease
VSENSE = VC1 = VC2 = VC3 = 3.5V, VCTL = 14V
20
uP8206-DS-F0001, Apr. 2018
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uP8206
Application Information
Battery Protection Connections
The following diagrams show the uP8206 package device
in two to four cell configurations.
EB+
EB+
1
2
VDD
CO
8
1
2
VDD
CO
8
SENSE
VC1
CTL
VSS
VC3
7
6
5
SENSE
VC1
CTL
VSS
VC3
7
6
5
Battery 1
Battery 2
Battery 1
Battery 2
3
4
3
4
VC2
VC2
2-Series Cell
3-Series Cell
Battery 3
EB-
EB-
Figure 1. 2-Series Cell
Figure 3. 3-Series Cell
EB+
VDD
CO
8
1
2
SENSE
VC1
CTL
VSS
VC3
7
6
5
Battery 1
Battery 2
3
4
VC2
4-Series Cell
Battery 3
Battery 4
EB-
Figure 2. 4-Series Cell
uP8206-DS-F0001, Apr. 2018
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21
uP8206
Package Information
UUTDFN1.97x2.46 - 8L
0.15 - 0.25
0.15 - 0.25
1.87 - 2.07
0.50 BSC
Bottom View - Exposed Pad
0.127 REF
0.00 - 0.05
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
22
uP8206-DS-F0001, Apr. 2018
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uP8206
Package Information
TSSOP - 8L Package
2.90 - 3.10
1
0.22 TYP
0.65 TYP
0.80 - 1.05
0.127 TYP
1.20 MAX
0.05 - 0.15
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
uP8206-DS-F0001, Apr. 2018
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23
uP8206
Important Notice
uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other
changes to its products and services at any time and to discontinue any product or service without notice. Customers
should obtain the latest relevant information before placing orders and should verify that such information is current and
complete.
uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment.
However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor
for any infringements of patents or other rights of third parties which may result from its use or application, including but
not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for
use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license
is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries.
COPYRIGHT (C) 2011, UPI SEMICONDUCTOR CORP.
uPI Semiconductor Corp.
Sales Branch Office
uPI Semiconductor Corp.
Headquarter
12F-5, No. 408, Ruiguang Rd. NeihuDistrict,
Taipei Taiwan, R.O.C.
TEL : 886.2.8751.2062 FAX : 886.2.8751.5064
9F.,No.5, Taiyuan 1st St. Zhubei City,
Hsinchu Taiwan, R.O.C.
TEL : 886.3.560.1666 FAX : 886.3.560.1888
24
uP8206-DS-F0001, Apr. 2018
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