UP9625QQMI [UPI]
Wide Input Voltage, High Performance, Single Synchronous Step-Down Converter;
| 型号： | UP9625QQMI |
| 厂家： | 
uPI Semiconductor Corp. |
| 描述： | Wide Input Voltage, High Performance, Single Synchronous Step-Down Converter |
| 文件： | 总16页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Conceptual
uP9625
Wide Input Voltage, High Performance,
Single Synchronous Step-Down Converter
Features
General Description
The uP9625 is a high-efficiency, single synchronous buck
converter with an internal power switch. With internal low
RDS(ON) switches, the high-efficiency buck converter is
capable of delivering up to 7A output current for charger
interface. The proprietary RCOTTM technology provides fast
transient response and high noise immunity. When there
is a ripple injection circuit, it can support ceramic and
OSCON output capacitors for low ESR application. This
combination is ideal for building modern low duty ratio,
untra-fast load step responseDC-DC converters. The output
voltage ranges from 2.9V to 21V, and the conversion input
voltage ranges is from 6V to 32V. The quasi-constant
switching frequency is 100kHz. RCOTTM control tracks the
100kHz switching frequency over a wide range of input and
output voltages, while it increases the switching frequency
at step-up of load.
Input Voltage AbsolutMam Rating: 40V
Wide Input Voltage Rangto 32V
Input Over Voltage tection: 35V (typ.)
Output Voltagnge: 2.9V to 21V
Wide Output Load Re: 0A to 7A
Built-In 1% erence
RCOTTM (Rust Constant On-Time) Control
Architecture
Quasitant Switching Frequency
Oper: 10kHz
s, 2mms and 8ms Selectable Output
VSoft-Start
ged Start-up Capability
Buin Output Discharge
The strong gate drivers of the uP9625 allow low RDS(ON)
FETs for high current applications. It is available in spae
saving WQFN4x4-26L and WQFN4x4-32L packages.
ilt-in VIN OVP/Output UVP/OCP/OTP
Available in WQFN4x4-26L and WQFN4x4-32L
ackages
Ordering Information
Order Number
Package Type
Top Markin
uP9625P
uP9625Q
uP
RoHS Compliant and Halogen Free
Applications
uP9625PQMY WQFN4X4-26L
uP9625QQMY WQFN4X4-26L
Portable Charging Devices
uP9625QQMI
WQFN4x4-32L
Point-of-Load Systems
Notebook Computers
I/O Supplies
uP9625P: EN=L, LX = OFF, VREG=OFF
uP9625Q: EN=L, LX= OFF, VREG= N
System Power Supplies
Note:
(1) Please check the sample/produion availility with
uPI representatives.
\
(2) uPI products are compatible with the current IPC/JEDEC
J-STD-020 requirement. Tey are halogen-free, RoHS
compliant and 100% matte tin (plating that are suitable
for use in SnPb or Pb-free solderinocesses.
Pin Configuration
LX_C 25
VIN 26
16 PGND
15 PGND
14 PGND
13 PGND
12 PGND
11 PGND
10 PGND
LX_C 20
BO
NC 22
13 PGND
12 PGND
11 PGND
10 PGND
35
Exposed Pad III
(VIN)
BOOT 27
MODE 28
OCP 29
AGND 30
EN 31
28
27
d Pad II
Exposed Pad I
33
Exposed Pad I
(LX)
VIN)
(LX)
ODE 23
EN 25
9
8
7
PGND
34
NC
Exposed PadII
(AGND)
VFB 26
VDRV/VREG
VFB 32
9
VDRV/VREG
WQFN4x4-26L
WQFN4x4-32L
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1
Conceptual
uP9625
Typical Application Circuit
EN
VIN=6~32V
CIN
100uF/50V
EN Pull L For Disable
VIN
CIN1
10uF/50V
Internal Active H For Enable
VDRV/VREG
Schottky Dode
0 ohm
220nF
1uF
10
VIN
VDD
82k
BOOT
OCP
4.7uF
LX_C
VOUT
VOUT=2.9V~21V
L1=22uH
Option*
LX
COMP
R3
1 ohm
C2
R5
47k
EC Cout
220uF/35V
C3
10nF
4.7nF
0 0hm
Option*
Option*
VDRV/VREG
Option*
VFB
MODE
AGND
R1
100k
PGND
EP
R2=2k
VIN=6~32V
CIN
100uF/50V
EN
N
EN Pull L For Disable
CIN1
10uF/50V
VDV/VREG
Internal Active H For Enable
Schottky Diode
0 ohm
220nF
1uF
10
VIN
OCP
82k
BOOT
LX_C
4.7uF
VOUT
LX
VOUT=2.9V~21V
L1=22uH
10k
COMP
R3
1 ohm
C2
R5
47k
MLCC Cout
22uF*4/35V
C3
10nF
4.7nF
0 0hm
100p
0.1uF
VDRV/V
MODE
AGND
VFB
Option*
100k
R1
PGND
EP
R2=2k
2
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Conceptual
uP9625
Functional Pin Description
Pin No.
PQMY/QQMY
Pin Name
Pin Function
QQMI
1
Error Amplifier Output. This is the ouof the error amplifier
and the non-inverting input of the PWcotor. Use this pin
in combination with the FB pin to compethe voltage-
control feedback loop of the converter.
1
COMP
Converter Power Supply Input. This n provides bias
voltage for the IC and powerinternal 5V linear regulators.
Connect this pin to 6V ~ 32V voltaurce and bypass it with
an R/C filter.
2
2
VDD
VIN
Power Supply Input. Inut voltage that supplies current to the
output voltage.
3,17~19
21~24, 26
Output Voltage Feck. Connect to output capacitor.
Signal Ground.
4
5
3
VOUT
AGND
4,30
Power Groun
6,9~13
7
5~8, 10~16
PGND
5V LDO Ouate Drive Supply Voltage Input.
Not Iternally ected.
9
VDRV / VREG
NC
8,22
--
Inrnal Swhes Output. Connect this pin to the output
ind.
14~16
20
17~20
25
LX
Internal Sches Output. Connect the bootstrap capacitor
CT to BOOT pin.
LX_C
ootstrap Supply for the Floating Upper MOSFET Gate
Der. Connect the bootstrap capacitor CBOOT between BOOT
pin anthe LX_C pin to form a bootstrap circuit. The bootstrap
pacitor provides the charge to turn on the upper MOSFET.
ure that CBOOT is placed near the IC. Externally connected to
EG with a Schottky diode.
21
27
BOOT
Soft Start and PSM/CCM Selection. Connect a resistor to
select soft-start time and operation mode (Table 1). The soft-
start time is detected and stored into internal register during the
start-up.
23
24
28
29
MODE
OCP
Over Current Protection Setting. Connect a resistor from this
pin to GND to set the over current protection level. The 10uA
current is sourced and set Over Current Protection as follows:
VOCSET = 10uA x ROCP.
ILIM=(VOCSET/(8XRDS(ON)))+(IRIPPLE/2)
Chip Enable. When EN pulls high, uP9625 enables the device.
When EN pulls low, the uP9625P will disable the device; but the
uP9625Q will keep the internal LDO output regulated at 5V
through VREG pin.
25
26
31
3
EN
Feedback Input. This pin is the inverting input to the error
amplifier. A resistor divider from output to GND is used to set
regulator voltage.
VFB
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3
Conceptual
uP9625
Functional Pin Description
Pin No.
PQMY/QQMY
Pin Name
Pin Function
QQMI
33
Switch Node. This pin is used as the sk for the upper
MOSFET gate driver. This pin is also mod by the shoot-
through protection circuitry to determne the upper
MOSFET has turned off. Connct this pin e source of the
upper MOSFET and the drain of thwer MOSFET
LX_Exposed
Pad I
27
Signal Ground. The exposead should be well soldered to
PCB with multiple vias to ground ne or optimal thermal
performance.
AGND_Exposed
Pad II
--
34
35
VIN_Exposed
Pad III
Power Supply Input. Input voltagthat supplies current to the
output voltage.
28
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Conceptual
uP9625
Functional Block Diagram
ar
VDD
Re
VDD OVP
VDD POR
VDD
VDD
VDRV/VREG
VIN
OV
1.0V x 120%
EN
BOOT
EN / SS
Control
LX_C
LX
VFB
EA
On-Time
Calculator
PWM
1.0V
XCON
COMP
Ramp
10µA
Generator
OCP
x(-1/8)
ZC
Control Logic
OCP
PSM/CCM
MODE
AGND
PGND
VOUT
UVP
2.4V
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5
Conceptual
uP9625
Functional Description
The uP9625 implements a unique RCOTTM control topology
for the synchronous buck. The RCOTTM supports extremely
low ESR output capacitors and makes the design easier
and robust. The output voltage ranges from 2.9V to 21V.
The conversion input voltage ranges from 6V to 32V.
to the internal 1Vreference voltage added with a ramp signal.
When both signals match, the PM comparator asserts a
set signal to terminate the off-time rn off the low-side
MOSFET and turn on high-side MOSFEThe set signal
is valid if the inductor current lel is w the OCP threshold,
otherwise the off-time is extndeil the current level
falls below the threshod.
The uP9625 implements adaptive on-time control and it
tracks the preset switching frequency over a wide input
and output voltage range while allowing the switching
frequency to increase at the step-up of the load.
Light Load Condition in M Operation
While the MODE pipulled low via RMODE, uP9625
automatically reduces thwitcing frequency at light load
conditions to maintain high efficiency. Detailed operation
is described as flows the output current decreases
from heavy load condition, the inductor current is also
reduced and evenlly comes to the point that its rippled
valley touches zero levl, which is the boundary between
continuouuction and discontinuous conduction
modes. Thchrnous MOSFET is turned off when this
zernductor t is detected.As the load current further
decreathe converter runs into discontinuous conduction
modThe on-time is kept almost the same as it
was ntinuous conduction mode so that it takes
longer o discharge the output capacitor with smaller
locurrent to the level of the reference voltage.
Enable and Soft Start
When the EN pin internal pull high voltage rises above the
enable threshold voltage (typically 1.4V), the converter
enters its start-up sequence. The internal LDO regulator
starts immediately and regulates to 5V at the VREG pin.
An internal DAC starts to ramp up the reference voltage
from 0V to 1V. Depending on the MODE pin setting, the
ramp-up time varies from 1ms to 8ms. Smooth and constant
ramp-up of the output voltage is maintained during start-up
regardless of load current.
When the EN pin pulls low, the uP9625P enters its off-
sequence and the internal LDO regulator stops immediately;
but the uP9625Q enters its off-sequence and the internal
LDO regulator starts immediately and regulates VRG
output at 5V.
The trasition point from discontinuous to continuous
nduction mode can be calculated as:
Table 1 Soft-Start and MODE Selection
1
V
OUT
UT
=
×VOUT ×(1−
)
2×fOSC ×LOUT
V
IN
MODE
Selection
Soft-Start
Time (ms)
Action
RMODE ()
Output Discharge Control
When EN is low, the uP9625 discharges the output
capacitor using internal MOSFET connected between
PHASE and GND while high side and low side MOSFETs
are kept off. The current capability of this MOSFET is limited
to discharge slowly.
1
2
4
200
75
Pull Down
to GND
Auto Skip
Over Current Limit
Connect to
VREG
Forced CCM
8
100
the uP9625 monitors the inductor valley current by low
side MOSFET RDS(ON) when it turns on. The over current
limit is triggered once the sensing current level is higher
than VOCSET. When triggered, the over current limit will keep
high side MOSFET off even the voltage loop commands it
to turn on.
PWM On-Time Control
The uP9625 does not have a deated oscillator that
determines switching fr. However, the device runs
with pseudo-constant fby feed-forwarding the input
and output voltages in-time one-shot timer. The
RCOTTM control adjusts on-time to be inversely
proportional to the inut voltagand proportional to the
output voltage. This makthe switching freuquency fairly
constant in steady state conitions over wide input voltage
range. The quasi-coant witching frequency is 100kHz.
The output voltage will decrease if the load continuously
demands more current than current limit level. The current
limit level is set at ILIM/2 if the output voltage is lower than
90% of its target level, VOUT decrease faster until UVP
occurs and the hiccup cycle time is set by an internal
counter .
The current limit threshold is set by connecting a resistor
from OCP toGND. The OCP pin will source a 10uAcurrent
The off-time is modulated by a PWM comparator. The VFB
node voltage (the mid-point of resistor divider) is compared
and create a voltage drop across ROCP as the VOCSET
.
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Conceptual
uP9625
Functional Description
VOCSET = 10uA x ROCP.
When the voltage drop across the low side MOSFET equals
the voltage across the setting resistor, the current limit will
be activated.
The voltage across LX andGNDpins is compared withVOCSET
for current limit. The current limit level is calculated as:
V
OCSET
I
+
RIPPLE
ILIM
=
8× RDS (ON )
2
where IRIPPLE is the peak-to-peak inductor ripple current at
steady state.
Input Over Voltage Protection
The uP9625 monitor Input voltage VDDto detect Input over
voltage protection. When Input voltage becomes higher than
35V of the target voltage, the Input OVP is triggered, then
LX stop switching. When the Input OVP condition
disappears, the converter will resume normal operation and
LX will start switching.
Output Over and Under Voltage Protection
The uP9625 monitors FB voltage to detect over voltage
and under voltage. When the FB voltage becomes highr
than 120% of the target voltage, the OVP is triggered, Te
uP9625 provides output short circuit protection function
Once the output loader short-circuits or the output voltage
becomes lower than 2.4V, the SCP will be triggered t
always hiccup, the hiccup cycle time is set by an intrnal
counter. When the SCP condition disappears, the conter
will resume normal operation and the hiccup status w
terminate.
UVLO Protection
The uP9625 uses VREG under voltage lockout tion
(UVLO). When the VREG voltage is wer than the UVLO
threshold voltage,the uP9625 will tuoff. This inon-latch
protection.
Over Temperature Protection
The uP9625 monitors the temperature of itself. If the
temperature exceeds typic130oC, the uP9625 will be
turned off. This is the non-latch protion. It will be recovered
once temperature is lown 110oC
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7
Conceptual
uP9625
Absolute Maximum Rating
(Note 1)
Supply Input Voltage, VINand VDD ---------------------------------------------------------------------------------------------------- -0.3V to +40V
LX Voltage to GND --------------------------------------------------------------------------------------------------------------0.3V to (VIN+ -0.3V)
BOOT Pin Voltage -------------------------------------------------------------------------------------------------------------------------- X-0.3V to VLX+6V
VDRV/VREGPin Voltage ------------------------------------------------------------------------------------------------------------ -0.3V to +6V
VOUT Pin Voltage ----------------------------------------------------------------------------------------------------------------- -0.3V to 32V
Other Pins toGND ------------------------------------------------------------------------------------------------------------------ -0.3V to +6V
Storage Temperature Range ---------------------------------------------------------------------------------------------------------- -55oC to +150oC
Lead Temperature (Soldering, 10 sec) ---------------------------------------------------------------------------------------------------- 260oC
ESD Rating (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------------------------------ 200V
Thermal Information
Package Thermal Resistance (Note 3)
WQFN4x4-26L θJA, controller ------------------------------------------------------------------------------------------------- 54oC/W
WQFN4x4-26L θJA, HS ---------------------------------------------------------------------------------------------------------- 42oC/W
WQFN4x4-26L θJA, LS --------------------------------------------------------------------------------------------------------------- 38oC/W
WQFN4x4-26L θJC, controller ----------------------------------------------------------------------------------------------- 21oC/W
WQFN4x4-26L θJC, HS----------------------------------------------------------------------------------------------------- 10oC/W
WQFN4x4-26L θJC, LS ----------------------------------------------------------------------------------------------------------- 6oC/W
WQFN4x4-32L θJA, controller ------------------------------------------------------------------------------------------------------- 54oC/W
WQFN4x4-32L θJA, HS ----------------------------------------------------------------------------------------------------------- 42oC/W
WQFN4x4-32L θJA, LS -------------------------------------------------------------------------------------------------------------- 38oC/W
WQFN4x4-32L θJC, controller --------------------------------------------------------------------------------------------------------- 21oC/W
WQFN4x4-32L θJC, HS ------------------------------------------------------------------------------------------------------------- 10oC/W
WQFN4x4-32L θJC, LS ---------------------------------------------------------------------------------------------------------------- 6oC/W
Power Dissipation, PD @ TA = 25°C
WQFN4x4-26L PD, controller -------------------------------------------------------------------------------------------------------- 1.85W
WQFN4x4-26L PD, HS ----------------------------------------------------------------------------------------------------------- 2.38W
WQFN4x4-26L PD, LS ----------------------------------------------------------------------------------------------------------------- 2.63W
WQFN4x4-32L PD, controller ----------------------------------------------------------------------------------------------------------------- 1.85W
WQFN4x4-32L PD, HS -------------------------------------------------------------------------------------------------------------------- 2.38W
WQFN4x4-32L PD, LS -------------------------------------------------------------------------------------------------------------------- 2.63W
Recommended Operation Conditions
(Note 4)
Input Voltage, VIN ------------------------------------------------------------------------------------------------------------------------------ 6V to 32V
Output Voltage, VOUT ----------------------------------------------------------------------------------------------------------------- 2.9V to 21V
Output Current, IOUTmax ---------------------------------------------------------------------------------------------------------------- 0A to 7A
Operating Junction TeRange --------------------------------------------------------------------------------------------- -40oC to +125oC
Operating Ambient TemperaRange --------------------------------------------------------------------------------------------- -40oC to +85oC
Note 1. Stresses listeas the abve Absolute Maximum Ratings may cause permanent damage to the device. These are
for stress ratings. nctional operation of the device at these or any other conditions beyond those indicated in the
operational sections the specifications is not implied. Exposure to absolute maximum rating conditions for
extended pds maremain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25oC on a low effective thermal conductivity test board of JEDEC
51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
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Conceptual
uP9625
Electrical Characteristics
(VIN = 12V, TA =25OC, unless otherwise specified)
Parameter
Supply Input Voltage
Input Voltage Range
Symbol
Test Conditions
Min
Max Units
VIN
--
--
--
32
--
V
V
V
VDD Rising
VDD Falling
VIN_OVP VDD_OVP Rising
.6
5.2
35
VDD POR Threshold
--
Input OVP Threshold
Supply Current
--
VDD Supply Current
IVDD
VEN = 5V, VFB =1.02V, IOUT = No Load
VEN = 0V, IOUT = No Load, (uP9625P)
EN = 0V, IOUT = No Load, (uP9625
--
--
--
420
--
590
30
uA
uA
VDD Shutdown Current
IVDD_SD
V
420
590
Internal Reference Voltage
Feedback Voltage
VFB
IFB
0.99
--
1.00
0.01
1.01
--
V
VFB Input Current
VFB =1.02V, Skip Mode, TA
∆IC = +10uA
uA
Error Amplifier
Transconductance
GEA
_
--
200
--
uA/V
Output Voltage Pin
VOUT Discharge Resistor
Power Switches
VIN = 12V. EN = 0VV= 5.0V
120
160
200
kΩ
Upper Switch Resistance
Lower Switch Resistance
Duty and Frequency Control
Minimum Off-ime
RUG,DSON
RLG,DSON
--
18
12
22
mΩ
mΩ
10.5
14.5
TOFF_MIN
200
325
450
ns
Soft Start
From VUT = 0% to 100%, RMODE = 39kΩ
From VT = 0% to 100%, RMODE = 100kΩ
From VOUT = 0% to 100%, RMODE = 200kΩ
From VOUT = 0% to 100%, RMODE = 470kΩ
--
--
--
--
1
2
4
8
--
--
--
--
Soft Start Time
TSS
ms
Logic Threshold and Setting Cotions
Enable
1.8
--
--
--
--
0.5
5
EN Pin Threshold Volta
VEN
V
Disable
EN Pull H Source Current
Switching Frequency
IEN
VEN = 0V
3.2
80
4
uA
FLX
VIN = 12V, VOUT = 5V, at CCM
100
120
kHz
Protection: Current Sense
OCP Source Current
ICS
9.5
10
10.5
uA
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9
Conceptual
uP9625
Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max Units
Protection: OVP and UVP
Measured at FB, with respect to reference
voltage
Output OVP Threshold Voltage
VOVP
11
--
120
4
125
--
%
V
Measured at VOUT, with respect to UVP
threshold voltage
VOUT UVP Threshold Voltage
VOUT
VREG LDO Voltage
Rising
3.8
0.27
4.95
4.95
--
4.0
0.30
5.0
5.0
--
4.2
0.33
5.15
5.15
50
VREG UVLO Threshold
LDO Output Voltage
VUVLOVREG
V
Hysteresis
EN pulls H for uP9625P
EN pulls H or L for uP9625Q
VREG
IREG
V
LDO Output Current
mA
Thermal Shutdown
Shutdown Temperature
Hysteresis
--
--
130
20
--
--
Thermal Shutdown Threshold
TSDN
oC
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Conceptual
uP9625
Typical Operation Characteristics
This page is intentionally left blank and will be updatehen data is available.
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11
Conceptual
uP9625
Application Information
Output Inductor Selection
The input capacitance needs to be higher than 88uF. The
best choice is the ceramic type d low ESR electrolytic
types may also be used provided that RMS ripple current
rating is higher than 50% of the output curnt.
In the case of electrolytic typesthan be further away if
a small parallel 10uF ceramic pas placed right close
to the IC. A 100uF elecolytic capr and 10uF ceramic
capacitor are recommendend placed close to the VINand
PGND pins, with the shortest tres possible.
Output inductor selection is usually based the
considerations of inductance, rated current value, size
requirements andDC resistance (DCR). The inductance is
chosen based on the desired ripple current. Large value
inductors result in lower ripple currents and small value
inductors result in higher ripple currents. Higher VIN or
VOUT also increases the ripple current as shown in the
equation below.Areasonable starting point for setting ripple
current is ∆IL=1500mA(30% of 5000mA).
Output Capacitor Setion
The ESR of the output capar etermines the output ripple
voltage and the initialtage drop following a high slew rate
load transient ede. Thoutput ripple voltage can be
calculated as:
1
V
OUT
⎛
⎞
⎟
⎠
∆IL
=
×VOUT 1−
⎜
f
OSC × LOUT
V
IN
⎝
Maximum current ratings of the inductor are generally
specified in two methods: permissible DC current and
saturation current. PermissibleDC current is the allowable
DC current that causes 40oC temperature raise. The
saturation current is the allowable current that causes 10%
inductance loss. Make sure that the inductor will not
saturate over the operation conditions including temperature
range, input voltage range, and maximum output current. If
possible, choose an inductor with rated current higher than
7.5A so that it will not saturate even under current limit
condition.
The size requirements refer to the area and heig
requirement for a particular design. For better efficiency
choose a low DC resistance inductor. DCR is usually
inversely proportional to size.
Different core materials and shapes will change the ize,
current and price/current relationship of an inductor. Tid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but genost
more than powdered iron core inductors with simal
characteristics. The choice of which style induse
often depends on the price vs. size reements and any
radiated field/EMI requirements.
⎛
⎞
1
⎟
⎟
∆VOUT = ∆I
SR +
8× fOSC ×COUT
⎠
Whee fOSC = ratig frequency, COUT = output capacitance
and ∆IC I= ripple current in the inductor. The ceramic
capaciow ESR value provides the low output ripple
and lofile.
In the clectrolytic capacitors, the ripple is dominated
bESR multiplied by the ripple current. Connect a 220uF
electric capacitor at output terminal for good performance
nd low output ripple and place output capacitors as close
as ssible to the device. When there is a ripple injection
circuit, it can support ceramic and OSCONoutput capacitors
low ESR application, in the case of ceramic or OSCON
output capacitors, RESR is very small and does not contribute
to the output ripple.
PCB Layout Considerations
High speed switching and relatively large peak currents in a
synchronous-rectified buck converter make the PCB layout
a very important part of design. Fast current switching from
one device to another in a synchronous-rectified buck
converter causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise that result
in overvoltage stress on devices. Careful component
placement layout and printed circuit board design minimizes
the voltage spikes induced in the converter.
Input Capacitor Selection
The input capacitor needs to be refully sected to
maintain sufficiently low ripple at the snput of the
converter. A low ESR capacitor is highly recommended.
Since large current flows in d out of this capacitor during
switching, its ESR also affects ciency.
Follow the layout guidelines for optimal performance of
uP9625.
12
uP9625-DS-C3100, Oct. 2017
www.upi-semi.com
Conceptual
uP9625
Application Information
Layout Guidelines:
1.Arrange the power components to reduce theAC loop
size consisting of CIN, VINand LX.
7.Apply copper plane to Exposed PadAGNDfor best heat
dissipation and noise immunityhe exposed pad is the
main path for heat convection and shld be well-soldered
to the PCB for best thermal performance
2.The input decoupling ceramic capacitor 10uF must be
placed closest to the VIN. PGNDandAGNDplane should 8.Use a short trace connectinthootstrap capacitor
be used through vias or a short and wide path.
3.The input decoupling ceramic capacitor 4.7uF must be
CBOOT to BOOT and LX_C foootstrap circuit.
9.Use a short trace conecting RX and PGNDPlane
placed closest to the VDD. PGNDplane andAGNDplane to form a Snubber Circuit eliminate the high frequency
should be used through vias or a short path. The VDD voltage spike at LX node.
connecting the Resistance 10Ω to VINto form a filter circuit. 10.The LX pad is the se node switching from VIN to
4.The 5V LDO Output andGateDrive Supply Voltage Input GND. LX node copper arehuld be minimized and wide
capacitor 1uF must be placed closest to the VDRV/VREG to reduce EMI and uld be isolated from the rest of circuit
pin.
for good EMI and ow nooperation.
5.AGNDand PGND(power ground) should be connected
together at a single point. Connect exposed pad ofAGND
to power ground copper area with copper and vias.
6.The 4-layered PCB layout can increase heat dissipation
area by taking advantage of the middle layers of theGND
plane. This may also lower the temperature of IC and its
peripheral components of the demo board such as inductor.
Via for GND
VOUT
CIN
Inductor
-
GND
COUT
16 PGND
LX_C 2
15
VIN 26
PGND
Pad III
OT 27
14 PGND
13 PGND
12 PGND
11 PGND
(VIN)
MODE
28
33
Exposed Pad I
(LX)
OCP 29
EN 31
Via for GND
34
Exposed PadII
(AGND)
PGND
10
9
VFB 32
VDRV/VREG
Via for GND
Via for VOUT
Via for LX
Via for VOUT
Via for GND
Via for VIN
CVDD
Via for GND
Layout Reference of WQFN4x4-32L
uP9625-DS-C3100, Oct. 2017
www.upi-semi.com
13
Conceptual
uP9625
Package Information
WQFN4x4 - 26L
1.35 BSC
0.55 BSC
0.45 BSC
0.325BSC
0.25BSC
1.30BSC
0.10 - 0.20
C
0.958 - 1.158
0.30BSC
1.225 - 1.425
15 - 0.25
1.225 - 1.425
0.10 - 0.20
5 - 0.25
0.50 BSC
0.15 - 0.25
3.90 - 4.10
0.25 - 0.45
Pin 1mark
- Exd Pad
0.70 - 0.80
0.00 - 0.05
0.20 REF
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dor dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specifie
REF: Reference. Represents dimnsion for reference use only. This value is not a device specification.
TYP. Typical. Provided as a genel value. Thvalue is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
14
uP9625-DS-C3100, Oct. 2017
www.upi-semi.com
Conceptual
uP9625
Package Information
WQFN4x4 - 32L
0.00 - 0.10
0.20 - 0.35
0.20 -
0.96 - 1.16
0.10 - 0.20
0.25 - 0.35
5
3.90 - 4.10
0.25 - 0.35
0.40 BSC
0.35
0.95 - 1.21
0.20 - 0.35
Pin 1 mark
Bottom View - Exposed Pad
0.70 - 0.80
0.0 - 0.05
0.20 REF
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dor dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specifie
REF: Reference. Represents dimnsion for reference use only. This value is not a device specification.
TYP. Typical. Provided as a genel value. Thvalue is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
uP9625-DS-C3100, Oct. 2017
www.upi-semi.com
15
Conceptual
uP9625
Important Notice
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changes to its products and services at any time and to discontinue any product or servicwit notice. Customers
should obtain the latest relevant information before placing orders and should verify that sh iation is current and
complete.
uPI products are sold subject to the taerms and conditions of sale supplied at the tiof order acknowledgment.
However, no responsibility is assumed by uPI or its subsidiaries for its use or appliation of y product or circuit; nor
for any infringements of patents or other rights of third parties which may result frouse or application, including but
not limited to any consequential or incidental damages. No uPI components are designintended or authorized for
use in military, aerospace, automotive applications nor in systems for surgical imtation or life-sustaining. No license
is granted by implication or otherwise under any patent or patent rights of uPor its ssidiaries.
COPYRIGHT (C) 2017, UPI SEMICONDUCTOR CORP.
uPI Semiconductor Corp.
Sales Branch Office
uPI Semiconductor Cor
Headquarter
12F-5, No. 408, Ruiguang Rd. NeihuDistrict,
Taipei Taiwan, R.O.C.
TEL : 886.2.8751.2062 FAX : 886.2.8751.5064
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16
uP9625-DS-C3100, Oct. 2017
www.upi-semi.com
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