UR5596-S08-T [UTC]

MOS IC; MOS IC


型号：	UR5596-S08-T
厂家：	Unisonic Technologies
描述：	MOS IC MOS IC
文件：	总11页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UNISONIC TECHNOLOGIES CO.,LTD

UR5596

MOS IC

DDR TERMINATION

REGULATOR

ꢀ

DESCRIPTION

The UTC UR5596 is a linear bus termination regulator and

designed to meet JEDEC SSTL-2(Stub-Series Terminated

Logic) specifications for termination of DDR-SDRAM. It also can

be used in SSTL-3 or HSTL(High-Speed Transceiver Logic)

scheme. The device contains a high-speed OP AMP to provide

excellent response to the load transients, and can deliver 1.5A

continuous current and transient peaks up to 3A in the

application as required for DDR-SDRAM termination.

SOP-8

The UTC UR5596 also incorporates a V_SENSEpin to provide

superior load regulation and a V_REFoutput as a reference for the

chipset and DIMMs. Besides, an active low shutdown (SHDN)

pin provides Suspend To RAM (STR) functionality. When SHDN

is pulled low the V_TToutput will tri-state providing a high

impedance output, but, V_REFwill remain active. A power savings

advantage can be obtained in this mode through lower

quiescent current.

*Pb-free plating product number: UR5596L

Regarding the output, V_TTis capable of sinking and sourcing

current while regulating the output voltage equal to V_DDQ/2. The

output stage has been designed to maintain excellent load

regulation while preventing shoot through. The UTC UR5596

also incorporates two distinct power rails that separates the

analog circuitry from the power output stage. This allows a split

rail approach to be utilized to decrease internal power

dissipation and permits UTC UR5596 to provide a termination

solution for DDRII SDRAM.

ꢀ

FEATURES

* Source and sink current

* Low output voltage offset

* No external resistors required

* Linear topology

* Suspend To Ram (STR) functionality

* Low external component count

* Thermal shutdown protection

ꢀ ORDERING INFORMATION

Ordering Number

Package

Packing

Normal

Lead Free Plating

UR5596-S08-R

UR5596-S08-T

UR5596L-S08-R

UR5596L-S08-T

SOP-8

Tape Reel

Tube

www.unisonic.com.tw

QW-R502-045,A

UR5596

MOS IC

ꢀ

PIN CONFIGURATION

V_TT

GND

SHDN

V_SENSE

PVIN

AVIN

V_REF

V_DDQ

ꢀ

PIN DESCRIPTION

PIN NO.

PIN NAME

GND

PIN FUNCTION

Ground

SHDN

V_SENSE

V_REF

Shutdown

Feedback pin for regulating V_TT.

Buffered internal reference voltage of V_DDQ/2

Input for internal reference equal to V_DDQ/2

Analog input pin

V_DDQ

AV_IN

PV_IN

Power input pin

V_TT

Output voltage for connection to termination resistors

ꢀ

BLOCK DIAGRAM

AVIN

PVIN

VDDQ

SHDN

50k

VREF

VTT

VSENSE

GND

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QW-R502-045,A

UR5596

MOS IC

ꢀ

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

V_DD

RATINGS

-0.3 ~ +6

2.2 ~ 5.5

125

UNIT

PV_IN, AV_IN, V_DDQto GND

AV_INto GND(Note 1)

Supply Voltage

V_DD

℃

Junction Temperature

T_J

℃

T_OPR

T_STG

θ_JA

Operation Temperature(Note 2)

Storage Temperature

-20 ~ +85

-40 ~ +150

150

℃

Thermal Resistance Junction-Ambient

℃/W

Note: 1.Signified recommend operating range that indicates conditions for which the device is intended to be

functional, but does not guarantee specific performance limits.

2.The device is guaranteed to meet performance specification within 0℃~70℃ operating temperature range

and assured by design from –20℃~+85℃.

3.Absolute maximum ratings indicate limits beyond which damage to the device may occur.

ꢀ

ELECTRICAL CHARACTERISTICS

(T_J=25°C, V_IN=AV_IN=PV_IN=2.5V, V_DDQ=2.5V, unless otherwise specified).

PARAMETER

SYMBOL

TEST CONDITIONS

V_IN= V_DDQ= 2.3V

MIN

1.135

1.235

1.335

1.125

1.225

1.325

1.125

1.225

1.325

1.9

TYP

MAX

UNIT

1.158 1.185

1.258 1.285

1.358 1.385

1.159 1.190

1.259 1.290

1.359 1.390

1.159 1.190

1.259 1.290

1.359 1.390

V_REFVoltage

V_REF

_IN= V_DDQ= 2.5V

_IN= V_DDQ= 2.7V

V_IN= V_DDQ= 2.3V

I_OUT= 0A

V_IN= V_DDQ= 2.5V

V_IN= V_DDQ= 2.7V

V_IN= V_DDQ= 2.3V

V_IN= V_DDQ= 2.5V

V_IN= V_DDQ= 2.7V

V_TTOutput Voltage

V_TT

I_OUT= ±1.5A

High

Low

V_IH

V_IL

Minimum Shutdown Level

0.8

_OUT= 0A

_OUT= -1.5A

_OUT= +1.5A

-20

-25

Vos_TT

V_TT

V_TTOutput Voltage Offset (V_REF- V_TT)

Quiescent Current

I_Q

I_SD

I_OUT= 0A

SD = 0V

320

115

500

150

µA

Quiescent Current in Shutdown

Shutdown Leakage Current

I_{Q_SD}

V_TTLeakage Current in Shutdown

I_V

µA

V_TT= 1.25V

V_SENSEInput Current

I_SENSE

2.5

100

165

kΩ

℃

V_REFOutput Impedance

V_DDQInput Impedance

Thermal Shutdown

Z_VREFI_REF= -30 ~ +30 µA

Z_VDDQ

T_SD

℃

Thermal Shutdown Hysteresis

T_SD-HYS

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QW-R502-045,A

UR5596

MOS IC

ꢀ

PIN DESCRIPTIONS

AV_IN, PV_IN

Input supply pins. AV_INis used to supply all the internal analog circuits and PV_INis used to provide the output stage

to create V_TT. These pins have the capability to work off separate supplies depending on the application. Higher

voltages on PV_INwill increase the maximum continuous output current because of output RDSON limitations at

voltages close to V_TT. But the internal power loss will also increase, thermally limiting the design. If the junction

temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual

shutdown where V_TTis tri-stated and V_REFremains active.

For SSTL-2 applications, a good compromise would be to connect the AV_INand PV_INdirectly together at 2.5V. This

eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is

that PV_INmust be equal to or lower than AV_IN. It is recommended to connect PV_INto voltage rails equal to or less

than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation.

V_DDQ

The input pin used to create the internal reference voltage from a resistor divider of two internal 50kΩ resistors for

regulating V_TTand to guarantee V_TTwill track V_DDQ/2 precisely. As a remote sense by connecting V_DDQdirectly to the

2.5V rail for SSTL-2 applications is an optimal implementation of V_DDQat the DIMM. This ensures that the reference

voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines.

V_SENSE

The sense pin supply improved remote load regulation, if remote load regulation is not used then the V_SENSEpin

must still be connected to V_TT. A long trace will cause a significant IR drop resulting in a termination voltage lower at

one end of the bus than the other. Connect V_SENSEpin to the middle of the bus to provide a better distribution across

the entire termination bus then DDR performance will be improved. Take notice of when a long V_SENSEtrace is

implemented in close proximity to the memory, noise pickup in the V_SENSEtrace can cause problems with precise

regulation of V_TT. A ceramic capacitor of 0.1uF is placed to next the V_SENSEpin can help filter any high frequency

signals and preventing errors.

V_REF

V_REFsupply the buffered output of the internal reference voltage V_DDQ/2. This output delivers the reference voltage

for the Northbridge chipset and memory. Since these inputs are typically extremely high impedance, there should be

little current drawn from V_REF. A 0.1µF~0.01µF ceramic capacitor could be used to acquire better performance,

located close to the pin to help with noise. This output remains active during the shutdown state and thermal

shutdown events for the suspend to RAM functionality.

V_TT

V_TTis a regulated output for the bus resistors termination of DDR-SDRAM. It can track precisely the V_DDQ/2

voltage with the sinking and sourcing current capability. The UTC UR5596 is designed to handle peak transient

currents of up to ± 3A with a fast transient response. If a transient is expected to remain above the maximum

continuous current rating for a significant amount of time then the output capacitor size should be large enough to

prevent an excessive voltage drop.

Although UTC UR5596 can handle large transient output currents, but it can not handling these for long durations

since the limited thermal dissipation capability of SOP-8 package. If large currents are required for longer durations,

then must ensure the maximum junction temperature is not exceeded, otherwise, the maximum output current will be

degraded with heating. Proper thermal de-rating should always be used. While the temperature beyond the junction

temperature, the thermal shutdown protection will be functioned, then V_TTwill tri-state until the part returns below the

hysteretic trigger point.

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QW-R502-045,A

UR5596

MOS IC

ꢀ

CAPACITOR SELECTION

A capacitor is recommended for improve performance during large load transients to prevent the input rail from

dropping, even though UR5596 does not require for input stability. The input capacitor should be located as close as

possible to the PV_INpin. The typical recommended value for AL electrolytic capacitors is 50 µF and 10 µF with X5R

or better for Ceramic capacitors. If AV_INand PV_INare separated, the 47µF capacitor should be placed as close to

possible to the PV_INrail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive

noise from coupling into the device.

UTC UR5596 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).

The choice for output capacitor depends on the application and the requirements for load transient response of V_TT.

As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL

applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected

and the extent at which the output voltage is allowed to droop.

ꢀ

THERMAL DISSIPATION

The UR5596 will generate heat result from internal power dissipation when current flow working. The device might

be damaged any beyond maximum junction temperature rating. The maximum allowable internal temperature rise

(T_Rmax) can be calculated given the maximum ambient temperature (T_Amax) of the application and the maximum

allowable junction temperature (T_Jmax).

T_Rmax= T_Jmax− T_Amax

From this equation, the maximum power dissipation (P_Dmax) of the part can be calculated:

P_Dmax= T_Rmax/ θ_JA

The θ_JAof UR5596 can be calculated (refer to JEDEC standard) and will depend on several package type,

materials, ambient air temperature and so on.

UNISONIC TECHNOLOGIES CO., LTD

www.unisonic.com.tw

QW-R502-045,A

UR5596

MOS IC

ꢀ

TYPICAL APPLICATION CIRCUITS

Following demonstrate several different application circuits to illustrate some of the options that are possible in

configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance

Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AV_INand PV_IN.

STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME

SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination

scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered

with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one

R_Sseries resistor from the chipset to the memory and one R_Ttermination resistor (refer to Figure 1). R_Sand R_Tare

changeable to meet the current requirement from UR5596, the recommended values both R_Sand R_Tare 25Ω.

VTT

VDD

MEMORY

CHIPSET

VREF

Figure 1. SSTL-Termination Scheme

FOR SSTL-2 APPLICATIONS

For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all

the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and

component count and selection.

UTC UR5596

REF=1.25V

SHDN

V_DDQ

V_REF

REF

DDQ=2.5V

AVIN

PVIN

V_SENSE

V_TT

DD=2.5V

VTT=1.25V

GND

OUT

Figure 2. Recommended SSTL-2 Implementation

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QW-R502-045,A

UR5596

MOS IC

Figure 3 illustrate another application that the power rails are split when power dissipation or efficiency are

concerned. The output stage (PV_IN) can be as lower as 1.8V, and the analog circuitry (AV_IN) can be connected to a

higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current

from V_TT, but the disadvantage of this circuit is the maximum continuous current is reduced.

UTC UR5596

REF=1.25V

SHDN

V_DDQ

V_REF

REF

DDQ=2.5V

AVIN

PVIN

V_SENSE

V_TT

AV^IN=2.2V ~ 5.5V

PV^IN=1.8V

VTT=1.25V

GND

OUT

Figure 3. Lower Power Dissipation SSTL-2 Implementation

The third optional application is that PV_INconnect to 3.3V and AV_INwill be always limited to operation on the 3.3V

or 5V to always equal or higher than PV_IN. This configuration has the ability to provide the maximum continuous

output current at the downside of higher thermal dissipation. The power dissipation increasing problem must be

careful to prevent the junction temperature to exceed the maximum ranting. Because of this risk it is not

recommended to supply the output stage with a voltage higher than a nominal 3.3V rail.

UTC UR5596

REF=1.25V

SHDN

V_DDQ

V_REF

REF

DDQ=2.5V

AVIN

PVIN

V_SENSE

V_TT

AV^IN=3.3V or 5.5V

PV^IN=3.3V

VTT=1.25V

GND

OUT

Figure 4. SSTL-2 Implementation with higher voltage rails

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QW-R502-045,A

UR5596

MOS IC

FOR DDR-II APPLICATIONS

As a result of the separate V_DDQpin and an internal resistor divider, UR5596 can be utilized in DDR-II system,

figure 5 and 6 show two recommended circuits in DDR-II SDRAM application. The output stage is connected to the

1.8V rail and the AV_INpin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is

possible to connect the output stage to a 3.3V rail. The power dissipation increasing concern must be careful as well

SSTL-II application. The advantage of configuration of figure 6 is that it has the ability to source and sink a higher

maximum continuous current.

UTC UR5596

REF=0.9V

SHDN

V_DDQ

V_REF

REF

DDQ=1.8V

AVIN

PVIN

V_SENSE

V_TT

AV^IN=2.2V ～ 5.5V

PV^IN=1.8V

VTT=0.9V

GND

OUT

Figure 5. Recommended DDR-II Termination

UTC UR5596

REF=0.9V

SHDN

V_DDQ

V_REF

REF

DDQ=1.8V

AVIN

PVIN

V_SENSE

V_TT

AV^IN=3.3V or 5.5V

PV^IN=3.3V

TT=0.9V

GND

OUT

Figure 6. DDR-II Termination with higher voltage rails

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QW-R502-045,A

UR5596

MOS IC

ꢀ

TYPICAL PERFORMANCE CHARACTERISTICS

V_IHand V

V_REFvs I_REF

1.40

3.5

1.35

1.30

2.5

1.25

1.20

1.5

1.15

1.10

0.5

2.5

3.5

4.5

5.5

-30

-20

-10

_REF(μA)

AV_IN(V)

V_REFvs V_DDQ

V_TTvs I_OUT

2.5

1.275

1.270

1.265

1.260

1.255

1.5

0.5

1.250

1.245

-100 -75 -50 -25

25 50 75 100

V_DDQ(V)

_OUT(mA)

V_TTvs V_DDQ

Maximum Sourcing Current vs AV

2.5

1.4

1.2

(V_DDQ=2.5V, PV_IN=1.8V)

0.8

1.5

0.6

0.4

0.2

0.5

2.5

3.5

4.5

5.5

_DDQ(V)

AV_IN(V)

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QW-R502-045,A

UR5596

MOS IC

ꢀ

TYPICAL PERFORMANCE CHARACTERISTICS(cont.)

Maximum Sourcing Current vs AV

2.8

2.6

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

(V_DDQ=2.5V, PV_IN=2.5V)

(V_DDQ=2.5V, PV_IN=3.3V)

2.4

2.2

2.5

3.5

4.5

5.5

3.5

4.5

AV_IN(V)

5.5

AV_IN(V)

Maximum Sinking Current vs AV

Maximum Sourcing Current vs AV

(V_DDQ=2.5V)

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

V_DDQ=2.5V

(V_DDQ=1.8V, PV_IN=1.8V)

0.8

0.6

0.4

0.2

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

AV_IN(V)

Maximum Sourcing Current vs AV

Maximum Sinking Current vs AV

(V_DDQ=1.8V, PV_IN=3.3V)

(V_DDQ=1.8V)

2.8

2.6

2.4

V_DDQ=1.8V

(V_DDQ=1.8V, PV_IN=3.3V)

2.2

1.8

1.6

1.4

1.2

2.4

2.2

3.5

4.5

AV_IN(V)

5.5

2.5

3.5

4.5

5.5

AV_IN(V)

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QW-R502-045,A

UR5596

MOS IC

UTC assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or

other parameters) listed in products specifications of any and all UTC products described or contained

herein. UTC products are not designed for use in life support appliances, devices or systems where

malfunction of these products can be reasonably expected to result in personal injury. Reproduction in

whole or in part is prohibited without the prior written consent of the copyright owner. The information

presented in this document does not form part of any quotation or contract, is believed to be accurate

and reliable and may be changed without notice.

UNISONIC TECHNOLOGIES CO., LTD

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QW-R502-045,A

UR5596-S08-T [UTC]

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