3511 [UTC]
CMOS IC; CMOS IC
| 型号： | 3511 |
| 厂家： | 
Unisonic Technologies |
| 描述： | CMOS IC |
| 文件： | 总7页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTC 3511
CMOS IC
PC POWER SUPPLY
SUPERVISORS
DESCRIPTION
The UTC 3511 provides protection circuits, power
good output (PGO), fault protection latch (FPL_N),
and protection detector function (PDON_N) control.
It can minimize external components of switching
power supply systems in personal computer.
The Over Voltage Detector (OVD) monitors 3.3V,
5V, 12V input voltage level. The Under Voltage
Detector (UVD) monitors 3.3V, 5V input voltage level.
When OVD or UVD detect the fault voltage level, the
FPL_N is latched HIGH and PGO goes LOW. The
latch can be reset by PDON_N going HIGH. There is
2.4ms delay time for PDON_N turning off FPL_N.
When OVD and UVD detect the right voltage level,
the power good output (PGO) will be issue.
SOP-8
DIP-8
FEATURES
* The Over Voltage Detector (OVD) monitors
3.3V, 5V, 12V input voltage level.
* The Under Voltage Detector (UVD) monitors 3.3V,
5V input voltage level.
* Both of the power good output (PGO) and the fault
protection latch (FPL_N) are Open Drain Output.
* 75 ms time delay for UVD.
* 300 ms time delay for PGO.
* 38 ms for PDON_N input signal De-bounce.
* 73 us for internal signal De-glitches.
* 2.4 ms time delay for PDON_N turn-off FPL_N.
PIN CONFIGURATION
8
1
2
3
4
PGI
PGO
7
6
5
GND
FPL_N
VDD
V5
PDON_N
V33
UTC
UNISONIC TECHNOLOGIES CO., LTD. 1
QW-R502-015,B
UTC 3511
CMOS IC
PIN DESCRIPTION
PIN No.
PIN NAME
TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
PGI
I
P
O
I
Power good input pin
Ground
GND
FPL-N
PDON-N
V33
Fault protection latch output pin (open drain output)
Protection detector function ON/OFF control input pin
3.3V input pin
I
V5
I
5V input pin
VDD
I
Supply voltage/12V input pin
Power good output pin(open drain output)
PGO
O
BLOCK DIAGRAM
POR
VDD
Power On Reset
Vcc Low Voltage
CLK
Clock
LVRST
Generator
150uA
PWR
CLK
3.6V
CLK
PWR
PWR
RST
38ms
debounce
2.4ms
delay
PDON_N
CLR
-
UN
V33
CLK
RWR
+
-
75ms
delay
CLR
OV
+
-
UN
V5
+
CLK
RST
FPL_N
R
S
-
73us
debounce
Q
OV
+
VDD
-
OV
+
VDD
CLK RST
CLK
CLR
PGO
73us
debounce
300ms
delay
-
UN
PGI
+
1.2V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage
SYMBOL
VDD
Vin
RATINGS
-0.3 ~ 16
-0.3 ~ 7
UNIT
V
V
Input Voltage
PDON_N,V5,V33,PGI
Output Voltage
FPL_N
PGO
-0.3 ~ 16
-0.3 ~ 7
VOUT
V
Operating temperature
Storage temperature
Topr
Tstg
-40 ~ 125
-55 ~ 150
°C
°C
Note:Stresses above those listed may cause permanent damage to the devices
UTC
UNISONIC TECHNOLOGIES CO., LTD. 2
QW-R502-015,B
UTC 3511
CMOS IC
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
3.8
TYP
12
MAX
15
7
UNIT
V
Supply Voltage
Input Voltage
Output Voltage
VDD
Vin
PDON_N,V5,V33,PGI
V
FPL_N
PGO
15
7
V
VOUT
V
Output Sink Current
FPL_N
PGO
30
10
mA
mA
ms
Iosink
Trs
Supply Voltage Rising Time
1
ELECTRICAL CHARACTERISTICS (Ta=25℃, VDD=5V)
Over Voltage Detection
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP.
MAX
UNIT
Over voltage threshold
V33
V5
3.7
5.7
3.9
6.1
13.4
5
4.1
6.5
V
VDD/ V12
12.8
13.9
Leakage current (FPL_N)
Low level output voltage
(FPL_N)
ILEAKAGE FPL_N=5V
uA
V
Isink=10mA
VOL
0.3
0.7
Isink=30mA
PGI and PGO
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP.
MAX
UNIT
V
Under voltage threshold
V33
2.55
4.1
2.69
4.3
1.20
5
2.83
4.47
1.24
V5
VPGI
Input threshold voltage (PGI)
Leakage current (PGO)
1.16
ILEAKAGE PGO=5V
uA
V
Low level output voltage (PGO)
VOL
Isink=10mA
0.4
PDON_N
PARAMETER
SYMBOL
TEST CONDITIONS
PDON_N=0V
MIN
2.4
TYP.
150
MAX
1.2
UNIT
Il
Input pull-up current
uA
V
VIH
VIL
High-level input voltage
Low-level input voltage
V
TOTAL DEVICE
PARAMETER
SYMBOL
TEST CONDITIONS
PDON_N=5V
MIN
TYP.
3
MAX
1
UNIT
Supply current
low voltage
Icc
mA
V
VDD
UTC
UNISONIC TECHNOLOGIES CO., LTD. 3
QW-R502-015,B
UTC 3511
CMOS IC
SWITCHING CHARACTERISTICS, VDD=5V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP.
MAX
UNIT
De-bounce time (PDON_N)
Delay time (PGI to PGO)
De-bounce time (PDON_N)
De-glitch time
tdb1
tdelay
tdb2
32
200
32
38
300
38
61
490
61
ms
ms
ms
us
Ta=-40°C ~ 125°C
tg
63
73
120
PDON_N to FPL_N delay time
Internal UVD delay time
tdelay2
tdelay3
Tdb2+2.0 Tdb2+2.4 Tdb2+3.8
ms
FPL_N go low & every
Time PGI>1.2V
65
75
122
ms
APPLICATION CIRCUIT
5V
5V
0.01uF
1
2
3
4
PGO
VDD
V5
8
7
6
5
PGI
PGI
GND
12V
VSB
FPL_N
5V
3.3V
470
V33
PDON_N
PDON_N
3511
0.01uF
UTC
UNISONIC TECHNOLOGIES CO., LTD. 4
QW-R502-015,B
UTC 3511
CMOS IC
APPLICATION TIMMING
1. PGI (UNDER_VOLTAGE):
PDON_N
tdelay2
FPL_N
tdb1
tdelay1+tg
PGO
PGI
tdb2
PDON_N
FPL_N
tdelay2
tdb1
tdelay1+tg
tdelay1+tg
PGO
PGI
tdb2
UTC
UNISONIC TECHNOLOGIES CO., LTD. 5
QW-R502-015,B
UTC 3511
CMOS IC
2. V33,V5 (UNDER_VOLTAGE):
PDON_N
tdelay2
FPL_N
tdb1
tdelay1+tg
PGO
tdb2
V33 / V5
PDON_N
FPL_N
tdelay3=75mS
tdelay3+tg
tdelay2
tdb1
tdb1
tdelay1+tg
PGO
PGI
tdb2
V33 / V5
UTC
UNISONIC TECHNOLOGIES CO., LTD. 6
QW-R502-015,B
UTC 3511
CMOS IC
3. V33,V5,V12 (OVER_VOLTAGE):
PDON_N
tdelay2
FPL_N
tdb1
tdelay1+tg
PGO
tdb2
V33 / V5 / V12
PDON_N
tg
tdelay2
FPL_N
tdb1
tdb1
tdelay1+tg
PGO
tdb2
V33 / V5 / V12
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
UTC
UNISONIC TECHNOLOGIES CO., LTD. 7
QW-R502-015,B
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