4052-D16-T [UTC]
DIFFERENTIAL 4-CHANNEL ANALOG MULTIPLEXERS/ DEMULTIPLEXERS; 差动4通道模拟多路复用器/多路解复用器
| 型号： | 4052-D16-T |
| 厂家： | 
Unisonic Technologies |
| 描述： | DIFFERENTIAL 4-CHANNEL ANALOG MULTIPLEXERS/ DEMULTIPLEXERS |
| 文件： | 总6页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
4052
CMOS IC
DIFFERENTIAL 4-CHANNEL
ANALOG MULTIPLEXERS/
DEMULTIPLEXERS
DESCRIPTION
The UTC 4052 is differential 4-channel analog multiplexers/
demultiplexers for application as digitally–controlled analog switches.
The device has two binary control inputs and an inhibit input. It
feature low ON impedance and very low OFF leakage current.
Control of analog signals up to the complete supply voltage range
can be achieved.
FEATURES
* Wide Analog Voltage Range: VDD–VEE = 3V~18V.
(Note: VEE must be≦VSS
)
* Break-Before-Make Switching Eliminates Channel Overlap.
* Linearized Transfer Characteristics
* Implement an DP4T Switch Effectively.
* Pin to Pin Replacement for CD4052
ORDERING INFORMATION
Ordering Number
Package
Packing
Tube
Normal
Lead Free Plating
4052L-D16-T
4052L-P16-R
4052L-S16-T
4052L-S16-R
Halogen Free
4052G-D16-T
4052G-P16-R
4052G-S16-T
4052G-S16-R
4052-D16-T
4052-P16-R
4052-S16-T
4052-S16-R
DIP-16
TSSOP-16
SOP-16
Tape Reel
Tube
SOP-16
Tape Reel
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CMOS IC
PIN CONFIGURATION
PIN DESCRIPTION
PIN No.
SYMBAL
NAME AND FUNCTION
13, 3
X,Y
INH
Commons Input/Output
Inhibit Input
6
7
8
VEE
Supply Voltage
VSS
Ground
10,9
A,B
Binary Control Inputs
X Channel Inputs/Outputs
Y Channel Inputs/Outputs
Positive Supply Voltage
12,14,15,11
1,5,2,4
16
X0~X3
Y0~Y3
VDD
Note: Control Inputs referenced to VSS. Analog Inputs and Outputs reference to VEE. VEE must be ＜VSS.
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CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
DC Supply Voltage (Referenced to VEE, VSS≧VEE
SYMBOL
VDD
RATINGS
-0.5 ~ +18
UNIT
V
)
Input or Output Voltage (DC or Transient)
VIN, VOUT
-0.5 ~ VDD +0.5
V
(Referenced to VSS for Control Inputs and VEE for Switch I/O)
Input Current (DC or Transient), per Control Pin
Switch Through Current
IIN
±10
±25
mA
mA
ISW
Power Dissipation
Derating above 65°C
700
mW
mW/°C
°C
PD
7
Junction Temperature
TJ
125
Operating Temperature Range
Storage Temperature Range
TOPR
TSTG
-40 ~ +125
-40 ~ +150
°C
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS (Ta=25°C, unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY REQUIREMENTS (Voltages Referenced to VEE
)
VDD – 3≧VSS≧VEE
Power Supply Voltage Range
VDD
IQ
3
18
5
V
VDD=5V
0.005
0.010
0.015
µA
µA
µA
µA
µA
µA
Control Inputs: VIN = VSS or VDD
Switch I/O: VEE ≦VI/O ≦VDD, and
ΔVsw≦500mV(Note 2)
Quiescent Current per
Package
VDD=10V
10
20
V
DD=15V
VDD=5V
Ta=25°C only (The channel
component, (VIN-VOUT)/RON, is
excluded.)
(0.07 µA/kHz) f + IQ
(0.20 µA/kHz) f + IQ
(0.36 µA/kHz) f + IQ
Total Supply Current
(Dynamic Plus Quiescent,
ID(AV)
VDD=10V
Per Package)
V
DD=15V
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE
)
Recommended Peak to Peak Voltage
Into or Out of the Switch
VI/O
Channel On or Off
0
0
VDD VPP
Recommended Static or Dynamic
Voltage Across the Switch (Note2)
Output Offset Voltage
ΔVsw Channel On
600 mV
µV
VO(OFF) VIN = 0V, No Load
10
250
120
80
ΔVsw≦500mV (Note2)
VDD=5V
VDD=10V
DD=15V
1050
500
280
70
Ω
Ω
Ω
Ω
Ω
Ω
ON Resistance
RON
ΔRON
IOFF
VIN = VIL or VIH (Control), and
IN = 0 to VDD (Switch)
V
V
ΔON Resistance Between
Any Two Channels in the
Same Package
VDD=5V
25
VDD=10V
10
50
VDD=15V
10
45
VIN = VIL or VIH (Control) Channel to
Channel or Any One Channel,
Off Channel Leakage Current
±0.05
±100 nA
VDD=15V
Capacitance, Switch I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
CI/O
CO/I
Inhibit = VDD
10
17
pF
pF
Inhibit = VDD
Pins Not Adjacent
Pins Adjacent
0.15
0.47
CI/O
pF
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to VSS
)
VDD=5V
2.25
4.50
6.75
2.75
5.50
8.25
1.5
3.0
4.0
V
V
V
V
V
V
Low Level Input Voltage
High Level Input Voltage
VIL
VIH
RON= per spec, IOFF = per spec
RON= per spec, IOFF = per spec
VDD=10V
VDD=15V
VDD=5V
3.5
7.0
11
VDD=10V
VDD=15V
Input Leakage Current
Input Capacitance
ILEAK VIN= 0 or VDD, VDD=15V
CIN
±0.00001 ±0.1 µA
5.0 7.5 pF
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CMOS IC
DYNAMIC ELECTRICAL CHARACTERISTICS
(CL = 50pF, Ta=25°C, VEE≦VSS, unless otherwise specified)
V
DD–VEE
Vdc
5
10
15
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
Propagation Delay Times
Switch Input to Switch
Output (RL = 10 kΩ)
t
t
t
PLH, tPHL =(0.17 ns/pF)CL + 21.5ns
PLH, tPHL =(0.08 ns/pF)CL + 8.0ns
PLH, tPHL =(0.06 ns/pF)CL + 7.0ns
ns
ns
ns
ns
ns
ns
30
12
75
30
t
PLH, tPHL
10
25
5
10
15
(RL=10kΩ, VEE=VSS
)
300
155
125
600
310
250
t
t
PHZ, tPLZ
PZH, tPZL
Output “1” or “0” to High Impedance,
or High Impedance to “1” or “0” Level
Inhibit to Output
ns
ns
ns
%
325
130
90
650
260
180
5
Control Input to Output
tPLH, tPHL
RL = 10 kΩ, VEE = VSS
10
15
10
Total Harmonic Distortion
Bandwidth
THD
BW
RL = 10KΩ, f = 1 kHz, VIN = 5 VPP
RL = 1kΩ, VIN = 1/2 (VDD–VEE) p–p,
CL = 50pF, 20 Log (VOUT/VIN) = -3dB)
RL=1KΩ, VIN = 1/2 (VDD–VEE) p–p
0.07
10
10
10
10
17
-50
-50
75
MHz
dB
Off Channel Feedthrough
Attenuation
f
IN = 30MHz
RL = 1kΩ, VIN = 1/2 (VDD–VEE) p–p
IN = 3MHz
R1 = 1kΩ, RL = 10kΩ Control
TLH = tTHL = 20ns, Inhibit = VSS
Channel Separation
dB
f
Crosstalk, Control Input to
Common O/I
mV
t
Note: 1. Data of “TYP” is intended as an indication of the IC’s potential performance.
2. For voltage drops across the switch(ΔVsw)>600mV (>300mV at high temperature), excessive VDD current
may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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CMOS IC
TEST CIRCUIT
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
OUT/IN
IN/OUT
CONTROL
CONTROL
VEE
Switch Circuit Schematic
TRUTH TABLE
16
VDD
INH
A
6
10
9
BINARY TO 1-OF-4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
TRUTH TABLE
Control Inputs
B
Select
ON Switches
8
Vss
7
VEE
Inhibit
B
0
0
1
1
A
X0 12
X1 14
X2 15
0
0
0
0
0
1
0
1
Y0
Y1
Y2
Y3
X0
X1
X2
X3
X
Y
13
X
X
1
None
11
X3
Y0
Y1
Y2
Y3
* X=Don't Care
1
5
2
4
3
UTC 4052 Functional Diagram
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4052
CMOS IC
TYPICAL CHARACTERISTICS
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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