CD4014BG-S16-R [UTC]
CMOS 8-STAGE STATIC SHIFT REGISTERS; CMOS 8级静态移位寄存器
| 型号： | CD4014BG-S16-R |
| 厂家： | 
Unisonic Technologies |
| 描述： | CMOS 8-STAGE STATIC SHIFT REGISTERS |
| 文件： | 总9页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
CD4014B
Preliminary
CMOS IC
CMOS 8-STAGE STATIC SHIFT
REGISTERS
DESCRIPTION
The UTC CD4014 is a 8-stage synchronous parallel or serial
input/serial output registers having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and
individual parallel inputs to each register stage. Each register is a
D-type master-slave flip-flop. Q6, Q7, and Q8 are outputs. With the
positive clock line transition in the CD4014 parallel/serial entry is
made into the register synchronously.
SOP-16
In CD4014 serial entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL CONTROL input is
low, data is serially shifted into the 8-stage register synchronously with
the positive transition of the clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed into the 8-stage register via
the parallel input lines and synchronous with the positive transition of
the clock line.
FEATURES
* Up to 20V operation voltage
* 12MHz (typ.) clock rate at 10V
* Maximum input current of 1μA at 18V
* Fully static operation
* 8 master-slave flip-flops plus output buffering and control gating
APPLICATIONS
* General-purpose register
* Parallel input/serial output data queueing
* Parallel to serial data conversion
ORDERING INFORMATION
Ordering Number
Package
SOP-16
Packing
Lead Free
Halogen Free
CD4014BG-S16-R
CD4014BL-S16-R
Tape Reel
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Copyright © 2011 Unisonic Technologies Co., Ltd
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CD4014B
Preliminary
CMOS IC
PIN CONFIGURATION
LOGIC DIAGRAM
Fig.1 logic diagram
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CD4014B
Preliminary
CMOS IC
TRUE TABLE
PAR SER
CONTROL
Q1
CL
SER IN
P1
0
Pn
0
Qn
(INTERNAL)
X
X
X
X
0
1
1
1
1
0
0
X
0
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
0
1
Qn-1
Qn-1
QN (NC)
1
X
Q1 (NC)
Note: X = Don’t Care Case, NC = No Change
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CD4014B
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
VCC
RATINGS
-0.5 ~ 20
-0.5 ~ VCC + 0.5
-0.5 ~ VCC + 0.5
±10
UNIT
V
Supply Voltage
Input Voltage
Output Voltage
VIN
V
VOUT
IIK
V
Input Clamp Current (VIN<0, or VIN>VCC
)
mA
mW
mW
°C
TA=-55°C to +100°C
TA=+100°C to +125°C
500
PD
Power Dissipation
200
Storage Temperature
TSTG
-65 ~ +150
Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING COMDITIONS
PARAMETER
Supply Voltage
SYMBOL
VCC
CONDITIONS
MIN
3
MAX
UNIT
V
18
-
VCC = 5V
180
80
50
-
Clock Pulse Width
tW
ns
MHz
μs
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
-
-
3
6
8.5
15
15
15
-
Clock Frequency
fCL
-
-
-
Clock Rise and Fall Time
Set-up Time, Serial Input
Set-up Time, Parallel Input
Set-up Time, Parallel/Serial Control
tr, tf
-
-
120
80
60
80
50
40
180
80
60
ns
-
-
-
tS
ns
-
-
-
ns
-
-
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CD4014B
Preliminary
CMOS IC
ELECTRICAL CHARACTERISTICS (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
VIN = 0, 5 V, VCC = 5 V
MIN TYP MAX UNIT
0.04
0.04
0.04
5
VIN = 0, 10V, VCC = 10V
VIN = 0, 15V, VCC = 15V
10
20
Quiescent Supply Current
Output Low (Sink) Current
Output High (Source) Current
ICC
μA
mA
mA
VIN = 0, 20V, VCC = 20V
0.08 100
VOUT = 0.4V, VIN = 0, 5V, VCC = 5V
VOUT = 0.5V, VIN = 0, 10V, VCC = 10V
VOUT = 1.5V, VIN = 0, 15V, VCC = 15V
VOUT = 4.6V, VIN = 0, 5V, VCC = 5V
VOUT = 2.5V, VIN = 0, 5V, VCC = 5V
VOUT = 9.5V, VIN = 0, 10V, VCC = 10V
0.51
1.3
1
IOL
2.6
6.8
3.4
-0.51 -1
-1.6 -3.2
IOH
-1.3 -2.6
VOUT = 13.5V, VIN = 0, 15V, VCC = 15V
-3.4 -6.8
VIN = 0, 5V, VCC = 5V
0
0
0
0.05
0.05
0.05
Output Voltage: Low-Level
Output Voltage: High-Level
Input Low Voltage
VOL
VOH
VIL
V
V
V
V
VIN = 0, 10V, VCC = 10V
VIN = 0, 15V, VCC = 15V
VIN = 0, 5V, VCC = 5V
4.95
5
VIN = 0, 10V, VCC = 10V
9.95 10
14.95 15
VIN = 0, 15V, VCC = 15V
VOUT = 0.5, 4.5V, VCC = 5V
VOUT = 1, 9V, VCC = 10V
1.5
3
VOUT = 1.5, 13.5V, VCC = 15V
4
VOUT = 0.5, 4.5V, VCC = 5V
VOUT = 1, 9V, VCC = 10V
3.5
7
Input High Voltage
VIH
V
OUT = 1.5, 13.5V, VCC = 15V
11
Input Leakage Current
II(LEAK) VIN = 0, 18 V, VCC = 18V
±10-5 ±0.1 μA
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CD4014B
Preliminary
CMOS IC
SWITCHING CHARACTERISTICS (TA =25°C, Input tr, tf =20ns, CL =50Pf, RL = 200KΩ)
PARAMETER
SYMBOL
TEST CONDITIONS
VCC=5V
MIN TYP MAX UNIT
160
80
60
100
50
40
6
320
160
120
200
100
80
Propagation Delay Time
tPLH / tPHL
ns
ns
VCC=10V
VCC=15V
VCC=5V
Transition Time
tTHL/ tTLH
VCC=10V
VCC=15V
VCC=5V
3
6
Maximum Clock Input Frequency
Minimum Clock Pulse Width
Clock Rise and Fall Time
fCL
MHz
ns
VCC=10V
VCC=15V
VCC=5V
12
17
90
40
25
8.5
180
80
50
15
15
15
120
80
60
80
50
40
0
tW
VCC=10V
VCC=15
VCC=5V
tr / tf
μs
VCC=10V
VCC=15V
VCC=5V
60
40
30
40
25
20
Minimum Setup Time, Serial Inputs
Minimum Setup Time, Parallel Inputs
tS
ns
VCC=10V
VCC=15V
VCC=5V
tS
ns
VCC=10V
VCC=15V
VCC=5V
Minimum Hold Time, Serial In,
Parallel In, Parallel/Serial Control
tH
ns
VCC=10V
VCC=15V
Any Input
0
0
Average Input Capacitance
CI
5
7.5
pF
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CD4014B
Preliminary
CMOS IC
TEST CIRCUITS AND WAVEFORMS
Test
tPLH/tPHL
S1
GND
Inputs
VM
VCC/2
VLOAD
VCC
CL
RL
VIN
tr, tf
VCC
20 ns
50 pF
200 KΩ
VCC
0V
90%
90%
Input
10%
10%
tR
tF
Fig 2. Voltage Waveforms Input Rise and Fall Times
VIN
0V
Input
VM
VM
tPHL
tPLH
VOH
90%
VM
90%
Output
VM
10%
10%
VOL
tR
tF
tPHL
tPLH
VOH
90%
VM
90%
Output
VM
10%
10%
VOL
tR
tF
Fig 3. Voltage Waveforms Propagation Delay and Output Transition Times
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤1MHz, ZO = 50Ω.
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CD4014B
Preliminary
CMOS IC
TEST CIRCUITS AND WAVEFORMS(Cont.)
500uF
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
CL
CL
0.1uF
CL
CK
SER.DATA
(¼ fCK
)
Fig 4. Dynamic power dissipation test circuit
V
CC
VCC
GND
INPUTS
I
GND
Fig 5. Quiescent device current test circuit
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CD4014B
Preliminary
CMOS IC
TEST CIRCUITS AND WAVEFORMS(Cont.)
V
CC
INPUTS
OUTPUTS
VIH
VIL
+
-
GND
GND
Fig 6. Input voltage test circuit
Fig 7. Input current test circuit
Note：measure inputs sequentially, to both VCC and GND; connect all unused inputs to either VCC or GND.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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