CD4066G-D14-T [UTC]
QUAD BILATERAL SWITCH; 四路双向开关
| 型号： | CD4066G-D14-T |
| 厂家： | 
Unisonic Technologies |
| 描述： | QUAD BILATERAL SWITCH |
| 文件： | 总8页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
CD4066
CMOS IC
QUAD BILATERAL SWITCH
DESCRIPTION
The UTC CD4066 is a quad bilateral switch which can be applied
for switching of analog signals and digital signals. When control
input CONT is set to “H” level, the impedance between input and
output of the switch becomes low and when it is set to “L” level, the
impedance becomes high. It has a much lower “ON” resistance,
and “ON” resistance is relatively constant over the input-signal
range.
DIP-14
FEATURES
* 15V Digital or ±7.5V Peak-to-Peak Switching
* 85-Ω Typical On-State Resistance for 15V Operation
* High noise immunity 0.45 VDD (typ.)
* Matched “ON” resistance ∆RON=5ꢀ (typ.) over 15V signal input
* High degree linearity 0.1% distortion (typ.)
@ fIS=1kHz, VIS=5VP-P, VDD-VSS=5V, RL=10kꢀ
* Extremely low “OFF” 0.1nA (typ.)
switch leakage: @ VDD-VSS=10V, TA=25°C
* Extremely high control input impedance 1012ꢀ (typ.)
* Frequency response, switch “ON” 40 MHz (typ.)
ORDERING INFORMATION
Ordering Number
Lead Free
Package
DIP-14
Packing
Tube
Halogen Free
CD4066G-D14-T
CD4066L-D14-T
www.unisonic.com.tw
Copyright © 2012 Unisonic Technologies Co., Ltd
1 of 8
QW-R502-739.A
CD4066
CMOS IC
PIN CONFIGURATION
IN/OUT
1
VDD
14
13
OUT/IN
OUT/IN
2
3
CONTROL A
12 CONTROL D
11
10
IN/OUT
OUT/IN
IN/OUT
4
5
CONTROL B
6
7
CONTROL C
VSS
OUT/IN
IN/OUT
9
8
PIN DESCRIPTION
PIN NO.
PIN NAME
IN/OUT
OUT/IN
OUT/IN
IN/OUT
DESCRIPTION
1
2
Signal IN/OUT A
Signal OUT/IN A
Signal OUT/IN B
Signal IN/OUT B
3
4
5
CONTROL B CONTROL B
CONTROL C CONTROL C
6
7
VSS
Ground
8
IN/OUT
OUT/IN
OUT/IN
IN/OUT
Signal IN/OUT C
Signal OUT/IN C
Signal OUT/IN D
Signal IN/OUT D
9
10
11
12
13
14
CONTROL D CONTROL D
CONTROL A CONTROL A
VDD
Power supply
UNISONIC TECHNOLOGIES CO., LTD
2 of 8
QW-R502-739.A
www.unisonic.com.tw
CD4066
CMOS IC
BLOCK DIAGRAM
1
VDD
IN/OUT
SW A
14
CONTROL A
CONTROL D
2
3
13
12
OUT/IN
OUT/IN
SW D
SW B
4
5
IN/OUT
11
10
IN/OUT
OUT/IN
CONTROL B
6
7
9
8
CONTROL C
VSS
OUT/IN
IN/OUT
SW C
SCHEMATIC DIAGRAM
UNISONIC TECHNOLOGIES CO., LTD
3 of 8
QW-R502-739.A
www.unisonic.com.tw
CD4066
CMOS IC
ABSOLUTE MAXIMUM RATING (VSS=0V unless otherwise specified.)
PARAMETER
SYMBOL
VDD
RATINGS
-0.5~+18
-0.5~ VCC+0.5
700
UNIT
V
Supply Voltage
Input Voltage
VIN
V
Power Dissipation
Storage Temperature
PD
mW
°C
TSTG
-65~+150
RECOMMENDED OPERATING CONDITIONS (VSS=0V unless otherwise specified.)
PARAMETER
SYMBOL
VDD
RATINGS
3~15
UNIT
V
Supply Voltage
Input Voltage
VIN
0~VDD
V
Operating Temperature
TA
-40~+85
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
DC ELECTRICAL CHARACTERISTICS (TA=+25°C, VSS=0V unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=5V
MIN TYP MAX UNIT
0.01 1.0
Quiescent Device Current
SINGAL INPUTS AND OUTPUTS
“ON” Resistance
IDD
VIN=VDD
VDD=10V
VDD=15V
0.01 2.0
0.01 4.0
µA
VDD=5V
240 1050
120 400
RL=10kꢀ~(VDD-VSS/2),
RON
VDD=10V
VDD=15V
VDD=10V
VDD=15V
ꢀ
ꢀ
VCON=VDD,VSS~VDD
80
10
5
240
∆“ON” Resistance Between
Any 2 of 4 Switches
RL=10kꢀ~(VDD-VSS/2),
CC=VDD, VIS=VSS~VDD
∆RON
V
Input or Output Leakage Switch “OFF”
CONTROL INPUTS
IIS
VCON=0
±0.1 ±50 nA
VDD=5V
2.25 1.5
VIS=V SS and VDD,
VOS=VDD and VSS,
IIS=±10µA
LOW Level Input Voltage
VILC
VDD=10V
VDD=15V
4.5
6.75 4.0
3.5 2.75
7.0 5.5
11.0 8.25
3.0
V
V
VDD=5V
HIGH Level Input Voltage
Input Current
VIHC
VDD=10V (Note 5)
VDD=15V
V
DD-VSS=15V, VDD≥VIS≥VSS,
IIN
±10-5 ±0.3 µA
VDD≥VCON≥VSS
UNISONIC TECHNOLOGIES CO., LTD
4 of 8
QW-R502-739.A
www.unisonic.com.tw
CD4066
CMOS IC
AC ELECTRICAL CHARACTERISTICS
(TA=25°C, tR=tF=20nS and VSS=0V, unless otherwise specified) (Note 1)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
V
DD=5V
25
15
10
55
35
25
ns
ns
ns
VCON=VDD, CL=5pF,
RL=200kꢀ (Fig. 1)
Propagation Delay Time Signal
tPHL, tPLH
VDD=10V
VDD=15V
V
DD=5V
125 ns
Propagation Delay Time
Control Input to Signal
Output High Impedance to Logical Level
RL=1kꢀ, CL=50pF,
(Fig. 2, 3)
t
PZH, tPZL
VDD=10V
VDD=15V
60
50
ns
ns
V
DD=5V
125 ns
Propagation Delay Time
Control Input to Signal
Output Logical Level to High Impedance
RL=1kꢀ, CL=50pF,
(Fig. 2, 3)
t
PHZ, tPLZ
VDD=10V
VDD=15V
60
50
ns
ns
V
CON=VDD=5V, VSS=-5V, RL=10kꢀ,
VIS=5Vp-p, f=1kHz (Fig. 4)
CON=VDD=5V, VSS=-5V, RL=1kꢀ,
Sine Wave Distortion
0.1
40
%
V
Frequency Response-Switch “ON”
(Frequency at -3dB)
20 Log10(VOS/VIS)=-3dB,
MHz
VIS=5.0Vp-p (Fig. 4)
V
DD=5.0V, VCC=VSS=-5.0V,
RL=1kꢀ, VIS=5.0Vp-p
20 Log10(VOS/VIS)=-50dB (Fig. 4)
Feedthrough - Switch “OFF”
(Frequency at -50dB)
,
1.25
0.9
MHz
MHz
VDD=VCON(A)=5.0V, RL=1kꢀ,
Crosstalk Between Any Two Switches
(Frequency at -50dB)
VSS=VCON (B)=5.0V, VIS(A)=5.0Vp-p
,
20 Log10(VOS(B)/VIS(A))=-50dB(Fig. 5)
VDD=10V, RL=10kꢀ, RIN=1kꢀ,
mVP-
Crosstalk, Control Input to Signal Output
Maximum Control Input
VCC=10V Square Wave,
150
P
CL=50pF (Fig. 6)
VDD=5V
6
MHz
MHz
MHz
pF
RL=1kꢀ, CL=50pF,
VOS(f)=½ VOS(1kHz)
VDD=10V
VDD=15V
8
(Fig. 7)
8.5
8.0
8.0
0.5
Signal Input Capacitance
Signal Output Capacitance
Feedthrough Capacitance
Control Input Capacitance
CIS
COS
CIOS
CIN
VDD=10V
VCON=0V
pF
pF
5.0 7.5 pF
Notes:1. AC Parameters are guaranteed by DC correlated testing.
2. These devices should not be connected to circuits with the power “ON”.
3. In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this
capacitance is included in CL wherever it is specified.
4. VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VCON is the voltage at the control
input.
5. Conditions for VIHC
:
a) VIS=VDD, IOS=standard B series IOH
b) VIS=0V, IOL= standard B series IOL
UNISONIC TECHNOLOGIES CO., LTD
5 of 8
QW-R502-739.A
www.unisonic.com.tw
CD4066
CMOS IC
SPECIAL CONSIDERATION
Using continuously under heavy loads may cause UTC CD4066 to decrease in the reliability even if the operating
conditions are within the absolute maximum ratings and the operating ranges.
In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability
should exceed VDD/RL. This provision avoids any permanent current flow or clamp action of the VDD supply when
power is applied or removed from UTC CD4066.
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
VDD
tr
tf
VDD
90%
50%
10%
VDD
CONTROL
VIS
VCON=VDD
VIS
0V
OUT/IN
VOS
tPLH
tPHL
CL
50pF
VDD
IN/OUT
RL
200kΩ
VSS
VOS
50%
0V
Fig. 1 tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
VDD
VDD
RL
tPZL
tPLZ
VDD
VDD
VDD
CONTROL
1kΩ
50%
tPLZ
VCON
VIS=0V
50%
tPZL
0V
0V
OUT/IN
VOS
CL
50pF
IN/OUT
VDD
VDD
90%
VSS
10%
VOL
VOL
Fig. 3 tPZL, tPLZ Propagation Delay Time Control to Signal Output
UNISONIC TECHNOLOGIES CO., LTD
6 of 8
QW-R502-739.A
www.unisonic.com.tw
CD4066
CMOS IC
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS(Cont.)
5V
VDD
CONTROL
2.5V
0V
VCON(1)=VDD
VIS(1)
OUT/IN
VOS(1)
VIS(1)
IN/OUT
RL
VSS
1kꢀ
-2.5V
1/f
-5V
5V
VDD
CONTROL
VCON(2)=VSS
VIS(2)=0V
VOS(2)
OUT/IN
IN/OUT
VSS
RL
1kꢀ
-5V
Fig. 5 Crosstalk Between Any Two Switches
UNISONIC TECHNOLOGIES CO., LTD
7 of 8
QW-R502-739.A
www.unisonic.com.tw
CD4066
CMOS IC
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS(Cont.)
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
UNISONIC TECHNOLOGIES CO., LTD
8 of 8
QW-R502-739.A
www.unisonic.com.tw
相关型号：
©2020 ICPDF网 联系我们和版权申明