L8002 [UTC]
FET BIAS CONTROLLER;
| 型号： | L8002 |
| 厂家： | 
Unisonic Technologies |
| 描述： | FET BIAS CONTROLLER |
| 文件： | 总6页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
L8002
Preliminary
CMOS IC
FET BIAS CONTROLLER
DESCRIPTION
The UTC L8002 is specially designed integrated circuit for
satellite receiver front-end block. It provides stable drain and gate
bias conditions for GaAs or HEMT FETs.
The UTC L8002, provide six FETs bias control respectively.
By adjusting two internal resistors, it can change the FET’s bias
current to optimize the satellite receiver front end block
performances.
It generates the required negative voltage to bias the gate of
GaAs FET, and internally provides protection circuit that can
protect the FET devices during supply voltage transient. So it is
very popular in satellite receiver front end block.
FEATURES
* Built in FET device protection circuit
* Stable bias control for GaAs and HEMT FETs
* Drive up to six FETs
* 2.5V supply voltage
ORDERING INFORMATION
Ordering Number
Package
SSOP-20
Packing
Tape Reel
Lead Free
Halogen Free
L8002G-R20-R
L8002L-R20-R
MARKING
www.unisonic.com.tw
Copyright © 2017 Unisonic Technologies Co., Ltd
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L8002
Preliminary
CMOS IC
PIN CONFIGURATION
VD1
VG1
VD2
1
20
VCC
VD4
VG4
2
3
4
5
6
19
18
17
16
15
VG2
VD3
VD5
VG5
VD6
VG6
NC
VG3
GND
NC
7
8
14
13
12
11
CNB1
CNB2
9
NC
CSUB
10
PIN DESCRIPTION
PIN NO.
PIN NAME
VD1
VG1
VD2
VG2
VG3
VD3
GND
NC
DESCRIPTION
1
2
1st Drain output voltage
1st Gate output voltage
2nd Drain output voltage
2nd Gate output voltage
3rd Gate output voltage
3rd Drain output voltage
Ground
3
4
5
6
7
8
No connect
9
CNB1
CNB2
CSUB
NC
OSC output
10
11
12
13
14
15
16
17
18
19
20
Rectifier Input
Negative voltage output
No connect
NC
No connect
VG6
VD6
VG5
VD5
VG4
VD4
VCC
6th Gate output voltage
6th Drain output voltage
5th Gate output voltage
5th Drain output voltage
4th Gate output voltage
4th Drain output voltage
Supply voltage
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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L8002
Preliminary
CMOS IC
BLOCK DIAGRAM
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QW-R502-B55a
L8002
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
VCC
RATINGS
-0.6 ~ 3
100
UNIT
V
Supply Voltage
Supply Current
ICC
mA
mA
uA
Maximum Drain Current
Maximum CSUB Sink Current
Operating Temperature
Storage Temperature
ID
15
ICSUB
TOPR
TSTG
-500
-40 ~ +85
-50 ~ +125
°C
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(VCC=2.5V, ID=9.5mA, TA=25°C, unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
VCC
TEST CONDITIONS
MIN
TYP MAX UNIT
2.375
2.5
6
2.625
10
V
mA
V
Supply Current
ICC
No FET
ISUB=0uA, VCC=2.5V
ISUB=-200uA
-2
-1
Negative Voltage
VSUB
-1
V
Oscillator Freq.
fO
ID
300
8
450
9.5
2
800
12
KHz
mA
%/V
Drain Current
Drain Current Change with VCC
VD1/VD2/VD3/VD4/VD5/VD6 Drain
Offset Current
∆IDV
VCC=2.375V~2.625V
∆IDC
0.5
mA
Drain Current Change with Temp.
Drain Voltage
∆IDT
VD
T=-40~85°C
0.5
2
%/°C
V
ID=9.5mA
1.8
-2
2.2
Drain Voltage Change with VCC
Drain Voltage Change
∆VDV
∆VDT
VG
VCC=2.375V~2.625V
T=-40~85°C
0.5
100
%/V
ppm/°C
V
Dynamic Gate Voltage Range
Drain Output Noise Voltage
Gate Output Noise Voltage
Csub without loading
With drain bypass capacitor=10nF
With gate bypass capacitor=10nF
0.7
Vdn
0.05
0.03
VPP
VPP
VGN
UNISONIC TECHNOLOGIES CO., LTD
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L8002
Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT
There are three major functions provided by UTC L8002: support negative voltage, bias control circuit, and FET
protesting circuit.
The negative voltage is generated using internal oscillator. It only needs an ac coupled capacitor CNB 47nF and a
negative voltage bypass capacitor CSUB 47nF.
The UTC L8002 devices have been designed to protect the external FETs from adverse operating conditions. With
a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -2V to 0.7V,
under any conditions including powerup and powerdown transients. Should the negative bias generator be shorted
or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is
shut down to avoid damage to the FETs by excessive drain current. The following diagrams show the L8002 in
typical LNB applications. Within each FET gain stage the numbering system indicates how the bias stages relate to
the application circuits.
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www.unisonic.com.tw
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L8002
Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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www.unisonic.com.tw
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