L8400G-R16-T [UTC]
Analog Circuit, PDSO16;
| 型号： | L8400G-R16-T |
| 厂家： | 
Unisonic Technologies |
| 描述： | Analog Circuit, PDSO16 光电二极管 |
| 文件： | 总6页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO.,LTD
L8400
LINEAR INTEGRATED CIRCUIT
FET BIAS CONTROLLER
DESCRIPTION
The UTC L8400 is designed to bias the MOSFETs that
are commonly used in LNBs that can implies minimum
external components requires.
FEATURES
* Can Bias up to 4 FETs
* Drain Current Adjustable by Two External Resistors.
* Two Sets of Drain Current can be Setted.
ORDERING INFORMATION
Ordering Number
Package
Packing
Lead Free
Halogen Free
L8400G-R16-R
L8400G-R16-T
L8400L-R16-R
L8400L-R16-T
SSOP-16
SSOP-16
Tape Reel
Tube
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Copyright © 2011 Unisonic Technologies Co.,LTD
QW-R123-010,B
L8400
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
FUNCTIONAL DESCRIPTION
The UTC L8400 includes one negative supply required for gate biasing from the single supply voltage, and all the
other bias requirements for external FETs. As fig.1
A low current negative supply voltage includes an internal OSC and two 47nF external cap. The negative rail
generator is common to all devices. This negative supply voltage used to drive the FET’s gate to obtain the required
drain current because of he FET is a depletion mode transistor.
There are for stages in the IC to baising the four external FETS. The drain voltage of the external FET FET1~4 is
2.2 volts set by the UTC L8400.
The drain current of external FET is determined by the external resist RCAL1 or RCAL2. External resistor RCAL1 sets
the drain current of FET1 and FET 2, and resistor RCAL2 sets the drain current of FET3 and FET4.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R123-010,B
L8400
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VCC
ICC
RATINGS
-0.6 ~ 15
100
UNIT
V
Supply Voltage
Supply Current
mA
mA
mA
mW
°C
Drain Current (per FET)(set by RCAL1 and RCAL2
Output Current
Power Dissipation(TA=25℃)
)
ID
0 ~ 15
Io
100
PD
500
Operating Temperature
Storage Temperature
TOPR
TSTG
-40 ~ +70
-50 ~ +85
°C
ELECTRICAL CHARACTERISTICS
(TA=25°C, VCC=5V, ID=10mA, RCAL1= RCAL2 =33KΩ, unless otherwise specified.)
PARAMETER
Supply Voltage
SYMBOL
VCC
TEST CONDITIONS
MIN TYP MAX UNIT
5
12
15
V
ID1 to ID4=0
Supply Current
ICC
mA
ID1 to ID4=10mA
ISUB =0
75
-3.5
-3
-2
Substrate Voltage
(Internally generated)
VSUB
V
ISUB = -200A
-2
Gate Voltage
Drain Voltage
ENG
END
fO
CG=4.7nF, CD=10nF
CG=4.7nF, CD=10nF
0.005
0.02
800
Output Noise
VPKPK
kHz
Oscillator Freq.
200
350
GATE CHARACTERISTICS
PARAMETER
Output Current Range
SYMBOL
TEST CONDITIONS
D1 to ID4=12mA
MIN TYP MAX UNIT
IGO
-30
2000 μA
I
-3.5
-2
IG1 to IG4=0
V
Output Low
VOL
ID1 to ID4=12mA
IG1 to IG4= -10μA
-3.5
0
-2
Output Voltage
I
D1 to ID4=8mA
1
V
Output High
VOH
IG1 to IG4=0
Note: Noise voltage measurement would be ignored in production.
DRAIN CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
Current
ID
△IDV
△IDT
8
10
0.02
0.05
2.2
12
mA
%/V
%/℃
With VCC
With TJ
V
CC=5 ~ 12V
Current Change
Voltage
TJ=-40 ~ +70℃
VD
2
2.4
V
△VDV
△VDT
With VCC
With TJ
V
CC=5 ~ 12V
0.5
%/V
ppm
Voltage Change
TJ=-40 ~ +70℃
50
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www.unisonic.com.tw
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QW-R123-010,B
L8400
LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION CIRCUIT
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QW-R123-010,B
L8400
LINEAR INTEGRATED CIRCUIT
APPLICATIONS INFORMATION
It is application circuit of UTC L8400 in figure 2, the bias circuits is stable fully in -40°C ~70°C.
CNB and CSUB are used to generated the negative supply on pin CSUB (about -3V), which can be used to power
other external circuits, but it is low load current is noticeable.
C1 and C2 are used to suppress noise or RF interference in each stage of the IC or other external circuits in
application circiut system. Value of C1 and C2 could be used in 1nF to 100nF as design dependent.
RCAL1 and RCAL2 are used to set the drain current of FETs 1 & 2 and FETS 3 & 4. If the same drain current is
required for all FETs on UTC L8400, then the pin RCAL1 and RCAL2 can be connected to GND through only one res of
half normal value.
There are full protection for external FETs on chip: The gate output voltage is limitted in -3.5V~0.7V in any
conditions including powerup and powerdown transients; If the negative bias generator be shorted or overloaded, the
drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current.
The fig.3 is typical applications of UTC L8400 in LNB.
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www.unisonic.com.tw
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QW-R123-010,B
L8400
LINEAR INTEGRATED CIRCUIT
TYPICAL CHARACTERISTICS
JFET Drain Current vs Rcal
JFET Drain Voltage vs Drain Current
16
14
12
10
8
2.4
2.3
2.2
2.1
6
4
10V
8V
2
0
5V
Vcc =5V
20
2
4
6
8
10
12
14
16
0
40
60
Rcal (k)
80
100
Drain Current (mA)
Vsub vs External Load
-1.0
-1.5
5V
-2.0
-2.5
-3.0
8V
10V
0
0.2
0.4
0.6
0.8
1.0
External Vsub Load (mA)
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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www.unisonic.com.tw
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QW-R123-010,B
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