LS3718L-S28-R [UTC]
20-BIT SERIAL TO PARALLEL CONVERTER; 20位串行到并行转换型号: | LS3718L-S28-R |
厂家: | Unisonic Technologies |
描述: | 20-BIT SERIAL TO PARALLEL CONVERTER |
文件: | 总8页 (文件大小:86K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
LS3718
CMOS IC
20-BIT SERIAL TO PARALLEL
CONVERTER
DESCRIPTION
The UTC LS3718 is a 20-bit serial to parallel converter utilizing
CMOS Technology. It is incorporates control circuit, shift register,
latch and driver into a single ship. It is suitable for MCU interface.
The effective interface assignment of MPU is available as the
connection between UTC LS3718 and MPU is required only 4
lines.
The device is designed to operate up to 5MHz. When the serial
data input to the DATA terminal and the data is output from parallel
output buffer through serial in parallel out shift register and parallel
data latches.
The data can through the shift register serial output to the SO
terminal. Therefore the UTC LS3718 can cascade connection to
expand the output data number.
*Pb-free plating product number: LS3718L
The hysteresis input circuit realizes wide noise margin and the
high drive-ability output buffer (25mA) can drive LED directly.
FEATURES
* 20-Bit serial in parallel out
* Cascade connection
* Operating voltage
* Hysteresis input
* Output current
5V±10%
0.5V typ
25mA
* Operating frequency
5MHz or more
ORDERING INFORMATION
Ordering Number
Package
Packing
Normal
Lead Free Plating
LS3718-S28-R
LS3718-S28-T
LS3718L-S28-R
LS3718L-S28-T
SOP-28
SOP-28
Tape Reel
Tube
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Copyright © 2007 Unisonic Technologies Co., Ltd
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LS3718
CMOS IC
PIN CONFIGURATION
P9
P10
P11
1
2
3
28
27
26
25
24
23
VDD
P8
P7
P12
P13
4
5
6
P6
P5
P14
P4
VSS
P15
P16
P17
7
8
9
10
22
21
20
P3
VSS
P2
P1
19
P18
P19
P20
11
12
13
18
17
16
15
CLR
STB
CLK
DATA
SO
14
PIN DESCRIPTION
PIN NO PIN NAME
I/O
DESCRIPTION
1
P9
P10
P11
P12
P13
P14
VSS
P15
P16
P17
P18
P19
P20
SO
O
O
O
O
O
O
Parallel Data Output Pin 9
Parallel Data Output Pin 10
Parallel Data Output Pin 11
Parallel Data Output Pin 12
Parallel Data Output Pin 13
Parallel Data Output Pin 14
GND
2
3
4
5
6
7
8
O
O
O
O
O
O
O
I
Parallel Data Output Pin 15
Parallel Data Output Pin 16
Parallel Data Output Pin 17
Parallel Data Output Pin 18
Parallel Data Output Pin 19
Parallel Data Output Pin 20
Serial Data Output Pin
Serial Data Input Pin
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DATA
CLK
STB
CLR
P1
I
Clock Signal Input Pin
Data Strobe, Low Actived
Data Reset, Low Actived
Parallel Data Output Pin 1
Parallel Data Output Pin 2
GND
I
I
O
O
P2
VSS
P3
O
O
O
O
O
O
Parallel Data Output Pin 3
Parallel Data Output Pin 4
Parallel Data Output Pin 5
Parallel Data Output Pin 6
Parallel Data Output Pin 7
Parallel Data Output Pin 8
Power Supply
P4
P5
P6
P7
P8
VDD
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LS3718
CMOS IC
BLOCK DIAGRAM
P1~P20
driver
STB
CLR
control
latch
CLK
SO
shift register
DATA
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LS3718
CMOS IC
ABSOLUTE MAXIMUM RATINGS (Ta=25℃)
PARAMETER
SYMBOL
VDD
RATINGS
-0.5~+7.0
VSS-0.5~VDD+0.5
VSS-0.5~VDD+0.5
±25
UNIT
V
Supply Voltage
Input Voltage
VIN
V
Output Voltage
VOUT
IOUT
V
Output Current
mA
mW
℃
Power Dissipation
Junction Temperature
Operating Temperature
Storage Temperature
PD
500
TJ
+125
TOPR
TSTG
-25 ~ +85
-40 ~ +150
℃
℃
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS (VDD=4.5~5.5V, VSS=0V, Ta=25℃)
PARAMETER
SYMBOL
VDD
TEST CONDITIONS
MIN
4.5
TYP
MAX
5.5
UNIT
V
Operating Voltage
Operating Current
Input Leakage Current
IS
VIH=VDD, VIL=VSS
0.1
mA
µA
II(LEAK)
VIH
VIN=0~VDD
-10
0.7VDD
VSS
10
High-Level
VDD
Input Voltage
V
V
Low-Level
High-Level
Low-Level
VIL
0.3 VDD
VDD
VOH
IOH=-0.4mA
IOL=+3.2mA
IOH=-25mA
IOH=-15mA
IOH=-10mA
IOL=+25mA
IOL=+15mA
IOL=+10mA
4.0
4.97
0.11
Output Voltage
SO Terminal
VOL
VSS
0.4
VDD-1.5 VDD-0.5 VDD
VDD-1.0 VDD-0.3 VDD
VDD-0.5 VDD-0.2 VDD
High-Level
Low-Level
VOHP
V
V
P1~P20
Terminals (Note)
Output Voltage
VSS
VSS
VSS
0.5
0.3
0.2
1.5
0.8
0.4
VOLP
Note: Specified value represent output current per pin. When use, total current consideration and less than power
dissipation rating operation should be required.
SWITCHING CHARACTERISTICS (VDD=4.5~5.5V, VSS=0V, Ta=-20~75℃)
PARAMETER
SYMBOL
tSD
TEST CONDITIONS
DATA-CLK
MIN
20
TYP
MAX
UNIT
ns
Data Set-up Time
Data Hold Time
Set-up Time
tHD
CLK-DATA
STB-CLK
CLK-STB
CLK-SO
20
ns
tSSTB
tHSTB
tPD
30
ns
Hold Time
30
ns
O
70
100
80
ns
tPD PCK CLK-P1~P20
tPD PSTB STB-P1~P2
ns
Output Delay Time
ns
t
PD PCLR CLR-P1~P20
fMAX
80
ns
Max. Operating Frequency
Note: COUT=50pF
5
MHz
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LS3718
CMOS IC
SWITCHING CHARACTERISTICS TEST WAVEFORM
fMAX
CLK
tSD
DATA
STB
tHD
tHSTB
tSSTB
CLK
SO
tPD
o
CLK
tPD pck
STB
P1~P 20
H
CLK
STB
tPD STB
P1~P 20
CLR
DATA
tPD PCLR
P1~P 20
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LS3718
CMOS IC
FUNCTION DESCRIPTION
RESET
When the CLR terminal is "L" level, all latches are reset and all of parallel output are "L" level.
Normally, the CLR terminal should be "H" level.
DATA TRANSMISSION
When the STB terminal is "H" level and input the clock signal to the CLK terminal, the serial data input the DATA
terminal and shift in the shift register by synchronizing at rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latch.
Even if the STB terminal is "L" level, the input clock signal shift the data in the shift register, therefore, the clock
signal controlled is needed.
CASCADE CONNECTION
The serial data input from DATA terminal and output from the SO terminal through internal shift register
unrelated to the CLR and STB status.
Furthermore, the 4 input terminals have a hysteresis characteristic by using the schmitt trigger structure to
decrease the noise.
CLK
X
STB
X
CLR
L
DESCRIPTION
All latch are reset (the data in the shift register is not change). All of
parallel outputs are "L".
The serial data input from DATA terminal to the shift register (the data in
the latch is not change).
H
H
L
The data in the shift register transfer to the latch. And the data in the
latch output from the parallel output.
H
L
H
The CLK input in the STB="L" and CLR="H" state, the data shift in the
shift register and latched data also change in accordance with the shift
register.
Note: X: Don’t care
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LS3718
CMOS IC
TIMING CHART
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LS3718
CMOS IC
TYPICAL APPLICATION CIRCUIT
Cascade Connection
P1~P20
P1~P20
SO
SO
UTC
UTC
LS3718
LS3718
STB
DATA CLK
CLR
STB
DATA CLK
CLR
MPU
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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