PA3312-N24-R [UTC]
Audio Amplifier, 2.6W, 2 Channel(s), 1 Func, CMOS, PDSO24, HTSSOP-24;
| 型号： | PA3312-N24-R |
| 厂家： | 
Unisonic Technologies |
| 描述： | Audio Amplifier, 2.6W, 2 Channel(s), 1 Func, CMOS, PDSO24, HTSSOP-24 放大器 光电二极管 商用集成电路 |
| 文件： | 总10页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
PA3312
CMOS IC
DUAL 2.6W AUDIO POWER
AMPLIFIER WITH FOUR
SELECTABLE GAIN SETTINGS
AND INPUT-MUX CONTROL
DESCRIPTION
The UTC PA3312 is a monolithic integrated circuit that stereo
bridged audio power amplifiers capable of producing 2.6W into 3Ω
with less than 10% THD+N or 1W into 8Ω with less than 0.65%
THD+N. This device minimizes the number of external components
needed, simplifying the design, and freeing up board space for
other features. Both of the depop circuitry and the thermal
shutdown protection circuitry are integrated in UTC PA3312, that
reduce pops and clicks noise during power up or shutdown mode
operation .
*Pb-free plating product number: PA3312L
Amplifier gain is internally configured and controlled by way of
two terminals (GAIN0 and GAIN1). BTL gain setting of 6 dB, 10 dB,
15.6dB, 21.6dB (inverting) are provided, whereas SE gain is
always configured as 4.1dB for headphone drive. A MUX control
terminal (HP/LINE) allows selection between the two sets of stereo
input signals. To simplify the audio system design, UTC PA3312
combines a stereo bridge-tied loads (BTL) mode for speaker drive
and a stereo single-end (SE) mode for headphone drive into a
single chip, where both modes are easily switched by the SE/BTL
input control pin signal.
FEATURES
* Low operating current with 10mA
* Compatible with pc 99 desktop line-out into 10KΩ load
* Internal gain control ,which eliminates external gain-setting
resistors
* 2.6w per channel output power into 3Ω at 5V , BTL mode
* Input MUX select terminal
* Pc-beep input
* Improves depop circuitry to eliminate turn-on and turn-off
transients in output
* Fully differential input
ORDERING INFORMATION
Order Number
Package
Packing
Normal
Lead Free Plating
PA3312-N24-R
PA3312-N24-T
PA3312L-N24-R
PA3312L-N24-T
HTSSOP-24
HTSSOP-24
Tape Reel
Tube
www.unisonic.com.tw
Copyright © 2007 Unisonic Technologies Co., Ltd
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PA3312
CMOS IC
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO
1, 12, 13, 24
PIN NAME
GND
I/O
DESCRIPTION
Ground connection for circuitry. Connected to the thermal pad.
Tap to voltage divider for internal mid-supply bias generator
Bit 0 of gain control
11
BYPASS
GAIN0
2
3
I
I
I
I
I
GANIN1
LLINEIN
LHPIN
Bit 1 of gain control
5
Left-channel line input, selected when SE/BTL is held low
Left-channel headphone input, selected when SE/BTL is held high
Power supply for output stage
6
7, 18
PVDD
Common right input for fully differential input. AC ground for single-ended
inputs.
8
RIN
LIN
I
I
I
Common left input for fully differential input. AC ground for single-ended
inputs.
10
14
For PC Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak)
square wave is input
PC-BEEP
HP/LINE
HP/LINE is the input MUX control input. When the HP/LINE terminal is
held high, the headphone inputs (LHPIN or RHPIN [6, 20]) are active.
When the HP/LINE terminal is held low, the line inputs (LLINEIN or
RLINEIN [5, 23]) are active.
17
I
15
19
SE/BTL
VDD
I
I
Hold SE/BTL low for BTL mode and hold high for SE mode.
Analog VDD input supply. This terminal needs to be isolated from PVDD to
achieve highest performance.
20
23
RHPIN
RLINEIN
I
I
Right-channel headphone input, selected when SE/BTL is held high
Right-channel line input, selected when SE/BTL is held low
Places entire IC in shutdown mode when held low, except PC-BEEP
remains active
SHUTDOWN
22
4
I
LOUT+
LOUT-
O
O
Left-channel positive output in BTL mode and positive output in SE mode
Left-channel negative output in BTL mode and high-impedance in SE
mode
9
Right-channel positive output in BTL mode and positive output in SE
mode
21
16
ROUT+
ROUT-
O
O
Right-channel negative output in BTL mode and high-impedance in SE
mode
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PA3312
CMOS IC
BLOCK DIAGRAM
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PA3312
CMOS IC
ABSOLUTE MAXIMUM RATING over operating free-air temperature range (unless otherwise
specified)
PARAMETER
SYMBOL
VDD
RATINGS
6
UNIT
V
Supply Voltage
Input Voltage
VIN
-0.3~VDD ~+0.3
Internally limited
-40 ~ +85
V
Power Dissipation
PD
Operating Junction Temperature
Storage Temperature
TOPR
TSTG
℃
℃
-65 ~ +85
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD
MIN
4.5
MAX
5.5
UNIT
V
Supply Voltage
0.8×VDD
SE/BTL, HP/LINE, GAIN0, GAIN1
SHUTDOWN
High-Level Input Voltage
VIH
V
2
0.6×VDD
0.4×VDD
0.8
SE/BTL, HP/LINE
GAIN0, GAIN1
Low-Level Input Voltage
VIL
TA
V
SHUTDOWN
Operating Free-Air Temperature
-40
85
℃
OPERATING CHARACTERISTICS VDD = 5 V, TA = 25℃, RL = 8Ω , Gain = 6 dB, BTL mode
PARAMETER
SYMBOL
POUT
TEST CONDITIONS
THD+N=10%
THD+N=1%
MIN
TYP
2.6
MAX
UNIT
W
RL = 3Ω
Output Power
2.05
Total Harmonic Distortion Plus
Noise
POUT = 1 W, f = 20 Hz ~ 15 kHz
TDH+N
0.65%
Maximum Output Power Bandwidth
Supply Ripple Rejection Ratio
Signal-to-Noise Ratio
BOM
RR
THD = 5%
f = 1 kHz, CB = 0.47 µF BTLmode
>15
72
KHz
dB
SNR
105
20
dB
CB=0.47µF,
BTLmode
SE mode
Noise Output Voltage
eN
µVRMS
f=20Hz ~ 20KHz
18
ELECTRICAL CHARACTERISTICS
TA = 25℃, VDD = 5 V, unless otherwise specified
PARAMETER
Output Offset Voltage (Measured
Differentially)
SYMBOL
TEST CONDITIONS
MIN
TYP
77
MAX
25
UNIT
mV
VIN = 0, AV = 6 dB
|VO(OFF)
|
Power Supply Rejection Ratio
High-Level Input Current
Low-Level Input Current
PSRR
|IIH|
VDD = 4.5 V ~ 5.5 V
VDD = 5.5 V, VIN = VDD
VDD = 5.5 V, VIN = 0 V
BTL mode
dB
µA
µA
1
1
|IIL|
6
3
10
5
Supply Current
IDD
mA
µA
SE mode
Supply Current, Shutdown Mode
IDD(SD)
150
300
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PA3312
CMOS IC
TYPICAL APPLICATION CIRCUIT
Right
CIRHP
0.47µF
Head−
phone
Input
20
23
RHPIN
Signal
Volume
Control
R
MUX
RLINEIN
CIRLINE
0.47µF
Right
Line
ROUT+
ROUT-
21
16
Input
Signal
Volume
Control
RIN
8
CRIN
0.47µF
PC-
COUTR
330µF
BEEP
Input
Signal
14
PC-BEEP
PC-
VDD
100KΩ
CPCB
0.47µF
1KΩ
Beep
GAIN0
GAIN1
HP/LINE
See Note A
2, 3
17
PVDD
VDD
18
Gain/
MUX
Control
VDD
CSR
Depop
Circuitry
0.1µF
SE/BEL
15
19
Power
Manag
ement
VDD
CSR
BYPASS 11
SHUT
DOWN
22
GND
Left
0.1µF
CILHP
0.47µF
Head−
phone
Input
CBYP
0.47µF
To System
Control
1, 12,
LHPIN
6
5
L
MUX
Volume
Control
Signal
LLINEIN
LIN
1KΩ
CILLINE
0.47µF
Left
Line
Input
Signal
LOUT+
LOUT-
13, 24
4
9
CLUTL
330µF
Volume
Control
10
CLIN
0.47µF
100KΩ
A. A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering
lower frequency noise signals, a larger electrolytic capacitor of 10 µF or greater should be
placed near the audio power amplifier.
Typical PA3312 Application Circuit Using Single-Ended Inputs and Input MUX
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PA3312
CMOS IC
TYPICAL APPLICATION CIRCUIT(Cont.)
CIRHP
0.47µF
20
23
RHPIN
CIRIN-
0.47µF
Right
Volume
Control
R
MUX
Negative
Differential
Input Signal
RLINEIN
ROUT+
ROUT-
21
16
Right
Positive
Differential
Input Signal
CRIN+
0.47µF
Volume
Control
8
RIN
COUTR
330µF
PC-BEEP
Input
Signal
14
PC-BEEP
PC-
VDD
100KΩ
CPCB
0.47µF
1KΩ
Beep
GAIN0
GAIN1
HP/LINE
See Note A
2, 3
PVDD 18
Gain/
MUX
Control
VDD
17
CSR
Depop
Circuitry
0.1µF
VDD
19
SE/BEL
15
Power
Manag
ement
VDD
CSR
BYPASS 11
SHUT
0.1µF
CILHP
DOWN
22
0.47µF
CBYP
0.47µF
To System
Control
1, 12,
LHPIN
6
5
GND
Left
L
MUX
Volume
Control
Negative
Differential
Input Signal
1KΩ
LLINEIN
LIN
LOUT+
LOUT-
13, 24
CILIN-
0.47µF
4
9
CLUTL
330µF
Left
Positive
Differential
Input Signal
Volume
Control
10
CLIN
0.47µF
100KΩ
A. A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Typical PA3312 Application Circuit Using Differential Inputs
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PA3312
CMOS IC
TYPICAL CHARACTERISTICS
Total Harmonic Distortion Plus Noise
vs. Frequency
10%
Total Harmonic Distortion Plus Noise
vs. Output Power
10%
RL=3Ω
GV=6dB
BTL
f=15KHz
1%
1%
POUT=1.0W
POUT=0.5W
f=1KHz
0.1%
0.1%
RL=3Ω
GV=6dB
BTL
POUT=1.75W
f=20Hz
0.01%
0.01%
20
100
1K
10K20K
0.01
0.1
1
10
Frequency, f (Hz)
Output Power, POUT (W)
Supply Ripple Rejection Ratio vs.
Frequency
Output Noise Voltage vs. Bandwidth
100
0
-20
-40
VDD=5V
RL=4Ω
RL=8Ω
CB=0.47µF
GV=6dB
BTL
90
80
70
60
50
-60
40
30
GV=21.6dB
GV=15.6dB
-80
20
-100
10
0
10
GV=6dB
-120
20
100
1K
10K
100
1K
10K 20K
Bandwidth, BW (Hz)
Frequency, f (Hz)
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PA3312
CMOS IC
TYPICAL CHARACTERISTICS(Cont.)
Supply Ripple Rejection Ratio vs.
Frequency
Crosstalk vs. Frequency
0
-20
-40
0
-20
-40
POUT=1W
RL=8Ω
GV=6dB
BTL
RL=32Ω
CB=0.47µF
GV=4.1dB
SE
-60
-80
-60
-80
LEFT TO RIGHT
-100
-120
-100
-120
RIGHT TO LEFT
100
20
100
1K
10K 20K
20
1K
10K 20K
Frequency, f (Hz)
Frequency, f (Hz)
Shutdown Attenuation vs. Frequency
VIN=1 VRMS
Crosstalk vs. Frequency
VOUT=1 VRMS
RL=10KΩ
GV=4.1dB
SE
0
-20
-40
0
-20
-40
RL=10KΩ, SE
-60
-80
-60
-80
RL=32Ω, SE
RL=8Ω, BTL
LEFT TO RIGHT
-100
-120
-100
-120
RIGHT TO LEFT
20
100
1K
10K 20K
20
100
1K
10K 20K
Frequency, f (Hz)
Frequency, f (Hz)
Closed-Loop Response
Gain
Signal-to-Noise Ratio vs. Frequency
10
180
140
POUT=1W
RL=8Ω
BTL
7.5
5
130
120
90
0
GV=6dB
GV=15.6dB
2.5
0
110
100
Phase
GV=21.6dB
-2.5
-5
90
80
-90
RL=8Ω
-7.5 GV=6dB
BTL
70
60
20
-10
10
-180
100
1K
10K 100K 1M
100
1K
10K 20K
Frequency, f (Hz)
Frequency, f (Hz)
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PA3312
CMOS IC
TYPICAL CHARACTERISTICS(Cont.)
Closed-Loop Response
Closed-Loop Response
30
180
90
30
180
90
25
20
25
20
Gain
Gain
15
10
15
10
0
0
Phase
Phase
5
0
5
0
-90
-90
RL=8Ω
-5 GV=15.6dB
BTL
RL=8Ω
-5 GV=21.6dB
BTL
-10
10
-10
10
-180
-180
100
1K
10K 100K 1M
100
1K
10K 100K 1M
Frequency, f (Hz)
Frequency, f (Hz)
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PA3312
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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