TC4013L-P14-R [UTC]
D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO14;型号: | TC4013L-P14-R |
厂家: | Unisonic Technologies |
描述: | D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO14 光电二极管 逻辑集成电路 触发器 |
文件: | 总6页 (文件大小:191K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
TC4013
Preliminary
CMOS IC
DAUL D-TYPE FLIP-FLOP
DESCRIPTION
The TC4013 is a dual D-type flip-flop which has two
independent circuits and each fillip-flop features independent
data, set, reset, and clock inputs and outputs. The input level
applied to DATA input are transferred to Q and Q output by
rising edge of the clock pulse. When SET input is “H”, and
RESET input is “L”, outputs become Q=”H” and Q =”L”. When
SET input is “L” and RESET input is “H”, outputs become
Q=”L” and Q =”H”. When both SET input and RESET input
are at “H”, outputs become Q=”H” and Q =”H”.
FEATURES
* Power supply voltage 3V to 18V
* Maximum Input Current of 1uA at 18V Over Full Package
Temperature
* Maximum quiescent supply current is 4μA
ORDERING INFORMATION
Ordering Number
Package
Packing
Lead Free
Halogen Free
TC4013G-P14-R
TC4013L-P14-R
TSSOP-14
Tape Reel
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TC4013
Preliminary
CMOS IC
PIN CONFIGURATION
1
2
3
4
5
6
7
Q1
Q1
VDD
Q2
14
13
12
CK1
Q2
RESET1
DATA1
SET1
11 CK2
RESET2
10
9
DATA2
SET2
8
VSS
FUNCTION TABLE
INPUTS
OUTPUTS
CK*
Q n+1
RESET
SET
H
DATA
Qn+1
L
H
H
-
-
-
-
-
-
H
L
L
H
H
L
H
H
L
L
L
L
L
L
L
H
-
L
H
L
H
No Change
No Change
Note: - : Don’t care
* : Level Change
LOGIC DIAGRAM
BLOCK DIAGRAM
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TC4013
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING (TA =25℃)
PARAMETER SYMBOL
RATINGS
VSS-0.5 to VSS+20
VSS-0.5 to VDD+0.5
VSS-0.5 to VDD+0.5
±10
UNIT
V
DC Supply Voltage
Input Voltage
VDD
VIN
V
Output Voltage
VOUT
IIN
V
DC Input Current
Power Dissipation
Operation Temperature
Storage Temperature
mA
mW
℃
PD
500
TOPR
TSTG
-40 ~ +85
-65 ~ +150
℃
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS (VSS=0,TA=25℃)
PARAMETER
SYMBOL
VDD
MIN
3
TYP
MAX
18
UNIT
V
DC Supply Voltage
Input Voltage
VIN
0
VDD
V
D.C. CHARACTERISTICS (VSS=0, TA=25℃)
PARAMETER
SYMBOL
TEST CONDITIONS
VOUT=0.5V, 4.5V;VDD=5V,∣IOUT∣<1μA
VOUT=1.0V, 9.0V; VDD=10V, ∣IOUT∣<1μA
VOUT=1.5V, 13.5V; VDD=15V, ∣IOUT∣<1μA
VOUT=0.5V, 4.5V; VDD=5V,∣IOUT∣<1μA
VOUT=1.0V, 9.0V; VDD=10V, ∣IOUT∣<1μA
VOUT=1.5V, 13.5V; VDD=15V, ∣IOUT∣<1μA
VIN=VSS, VDD; ∣IOUT∣<1μA; VDD=5V
VIN=VSS, VDD; ∣IOUT∣<1μA; VDD=10V
VIN=VSS, VDD; ∣IOUT∣<1μA; VDD=15V
VIN=VSS, VDD; ∣IOUT∣<1μA; VDD=5V
VIN=VSS, VDD; ∣IOUT∣<1μA; VDD=10V
VIN=VSS, VDD; ∣IOUT∣<1μA; VDD=15V
VIH=18V, VDD=18V
MIN
TYP MAX UNIT
3.5
7.0
2.75
5.5
High
Low
High
Low
VIH
11.0
8.25
Input Voltage
V
2.25
4.50
6.75
5.00
1.5
3.0
4.0
VIL
VOH
VOL
4.95
9.95 10.00
14.95 15.00
0.00
Output Voltage
Input Current
V
0.05
0.05
0.05
0.1
0.00
0.00
High
Low
IIH
IIL
10-5
uA
VIL=0V, VDD=18V
-10-5
-0.1
VOH=4.6, VIN=VSS, VDD; VDD=5V
VOH=2.5, VIN=VSS, VDD; VDD=5V
VOH=9.5, VIN=VSS, VDD; VDD=10V
VOH=13.5, VIN=VSS, VDD; VDD=15V
VOL=0.4, VIN=VSS, VDD; VDD=5V
VOL=0.5, VIN=VSS, VDD; VDD=10V
-0.51
-2.10
-1.30
-3.40
0.51
1.30
3.40
-1.0
-4.0
High
Low
IOH
-2.2
-9.0
Output Current
mA
uA
1.2
3.2
IOL
VOL=1.5, VIN=VSS, VDD; VDD=15V
12.0
0.002
0.004
0.008
VIN=VSS, VDD(Note); VDD=5V
VIN=VSS, VDD(Note); VDD=10V
VIN=VSS, VDD(Note); VDD=15V
1
2
4
Quiescent Supply Current
IDD
Note: All valid input combinations.
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TC4013
Preliminary
CMOS IC
A.C. CHARACTERISTICS (VSS=0, TA=25℃, CL=50pF)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=5V
MIN
TYP
70
MAX
200
100
80
UNIT
Low to High
High to Low
VDD=10V
VDD=15V
VDD=5V
35
tTLH
30
Output Transition Time
70
200
100
80
VDD=10V
VDD=15V
VDD=5V
35
tTHL
30
130
65
300
130
90
Propagation Delay Time
tpLH
tpHL
VDD=10V
VDD=15V
VDD=5V
ns
(CK – Q, Q )
50
110
50
300
130
90
VDD=10V
VDD=15V
VDD=5V
tpLH
tpHL
fCL
Propagation Delay Time
40
110
50
300
130
90
(SET, RESET – Q, Q )
VDD=10V
VDD=15V
VDD=5V
40
3.5
8.0
8.0
16.0
20.0
VDD=10V
VDD=15V
VDD=5V
Max. Clock Frequency
MHz
μs
12.0
No Limit
No Limit
VDD=10V
VDD=15V
VDD=5V
t CL
r
Max. Clock Input Rise Time
Max. Clock Input Fall Time
VDD=10V
VDD=15V
VDD=5V
t CL
f
μs
60
30
25
60
30
25
180
80
50
140
60
40
40
20
15
40
20
15
40
20
15
7.5
VDD=10V
VDD=15V
VDD=5V
Min. Pulse Width (SET, RESET)
Min. Clock Pulse Width
tW
tW
tsu
tH
ns
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
Min. Set-up Time (DATA - CK)
Min. Hold Time (DATA-CK)
20
10
6
VDD=10V
VDD=15V
VDD=5V
ns
Min. Removal Time
(SET, RESET-CK)
Input Capacitance
VDD=10V
VDD=15V
trem
CIN
5
pF
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TC4013
Preliminary
CMOS IC
PARAMETER MEASUREMENT INFORMATION
2. SET-RESET, Q
20ns
20ns
90%
50%
90%
50%
SET
10%
10%
20ns
tW
20ns
90%
50%
90%
50%
10%
10%
RESET
tW
50%
50%
Q
tPHL
tPLH
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TC4013
Preliminary
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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