U7313G-D28-T [UTC]
AUDIO PROCESSOR IC; 音频处理器IC
| 型号： | U7313G-D28-T |
| 厂家： | 
Unisonic Technologies |
| 描述： | AUDIO PROCESSOR IC |
| 文件： | 总14页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
U7313
CMOS IC
AUDIO PROCESSOR IC
DESCRIPTION
The U7313 is a 3-stereo inputs and 4-speaker outputs digital
audio processor which incorporates volume, tone(bass and treble) ,
balance(left/right)and fader(front/rear) into a single chip. Selectable
input gain and loudness function are provided to build a highly
effective electronic audio processor having the highest performance
and reliability with the external components. The AC signal setting is
obtained by resistor networks and switches which are set by
programming serial input signal via I2C bus. In addition, BiCOMS
processes are utilized for low distortion, low noise and low DC
stepping.
The U7313 is designed for quality audio applications in car
radio and Hi-Fi systems.
FEATURES
* Support I2C bus interface
* 3 stereo inputs and selectable input gain
* Volume control in 1.25dB/step
* Loudness function
* Bass and treble control
* 4 independent speakers control
* Independent mute function
* Low distortion
* Low noise and DC stepping
ORDERING INFORMATION
Ordering Number
Package
Packing
Lead Free
Halogen Free
U7313L-D28-T
U7313L-S28-R
U7313L-S28-T
U7313G-D28-T
U7313G-S28-R
U7313G-S28-T
DIP-28
SOP-28
SOP-28
Tube
Tape Reel
Tube
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Copyright © 2011 Unisonic Technologies Co., Ltd
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U7313
CMOS IC
PIN CONFIGURATION
CREF
VDD
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCL
SDA
3
GND
L
DIGGND
OUTLF
OUTRF
OUTLR
OUTRR
BOUTR
BINR
4
R
5
INR
OUTR
LOUDR
R3
6
7
8
9
R2
BOUTL
BINL
10
11
12
13
14
R1
LOUDL
L3
OUTL
INL
L2
L1
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U7313
CMOS IC
PIN DESCRIPTIONS
PIN NO. PIN NAME
I/O
PIN DESCRIPTION
Internal reference voltage, typical value is vdd/2, connect a capacitor to gnd to
depress ripple voltage.
1
CREF
2
3
VDD
Supply voltage.
GND
Analog gnd.
Connect a capacitor to gnd, the center frequency and quality of the response
behavior of treble module can be chosen by the capacitor. (Left speaker)
Connect a capacitor to gnd, the center frequency and quality of the response
behavior of treble module can be chosen by the capacitor. (Right speaker)
Input of volume module.(Right speaker)
4
5
L
I
I
R
6
7
INR
I
OUTR
O
Output of gain module.(Right speaker)
Connect
a
capacitor to gnd, change the capacitor can adjust the
8
LOUDR
I
amplitude-frequency characteristic of loudness.(Right speaker)
Channel 3 input.(Right speaker)
9
R3
R2
R1
I
I
I
10
11
Channel 2 input.(Right speaker)
Channel 1 input.(Right speaker)
Connect
a
capacitor to gnd, change the capacitor can adjust the
12
LOUDL
I
frequency-amplitude characteristic of loudness.(Left speaker)
Channel 3 input.(Left speaker)
13
14
15
16
17
L3
L2
I
I
Channel 2 input.(Left speaker)
L1
I
Channel 1 input.(Left speaker)
INL
OUTL
I
Input of volume module.(Left speaker)
O
Output of gain module.(Left speaker)
See the application circuit, change the capacitor and the resistor can adjust the
center frequency and quality of the response behavior of bass module.(Left
speaker)
18
19
20
21
BINL
BOUTL
BINR
I
I
I
I
See the application circuit, change the capacitor and the resistor can adjust the
center frequency and quality of the response behavior of bass module. (Left
speaker)
See the application circuit, change the capacitor and the resistor can adjust the
center frequency and quality of the response behavior of bass module. (Right
speaker)
See the application circuit, change the capacitor and the resistor can adjust the
center frequency and quality of the response behavior of bass module. (Right
speaker)
BOUTR
22
23
24
25
26
27
28
OUTRR
OUTLR
OUTRF
OUTLF
DIG GND
SDA
O
O
O
O
Output of the right rear speaker.
Output of left rear speaker.
Output of right front speaker.
Output of left front speaker.
Digital gnd of serial I2C bus.
I/O Data signal of serial I2C bus.
SCL
I
Clock signal of serial I2C bus.
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U7313
CMOS IC
BLOCK DIAGRAM
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U7313
CMOS IC
ABSOLUTE MAXIMUM RATINGS (Ta=25ºC, unless otherwise specified)
PARAMETER
SYMBOL
VDD
RATINGS
-0.5~10.2
100
UNIT
V
DC Supply Voltage
Max Input Clock Speed of Serial I2C Bus Signal
Operating Ambient Temperature
Storage Temperature
BCLK
KBit/s
℃
TOPR
-40~+85
-55~ +150
TSTG
℃
Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied
OVERALL CHARACTERSTICS
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=9V
MIN
6
TYP
9
MAX
10
UNIT
V
DC Supply Voltage
VDD
IS
Supply Current
8
11
mA
Ripple Rejection
|RR|
S/N
THD
VS=9V, RL=10KΩ,RG=600Ω
All gains=0dB; VOUT=1Vrms
V=1Vrms f=1KHZ
60
80
dB
Signal to Noise Ratio
Total Harmonic Distortion
Channel Separation
Input Gain Per Step
Volume Control Per Step
Bass Control Per Step
Treble Control Per Step
Speaker Control Per Step
106
0.01
103
3.75
1.25
2
dB
0.1
%
S(channel) f=1KHZ
Au(gain)
dB
dB/step
dB/step
dB/step
dB/step
dB/step
Au(volume)
Au(bass) f =100HZ
Au(treble) f =20KHZ
Au(speaker)
2
1.25
0
0
Au=0 to -20dB
-20 to -60dB
1
2
Total Tracking Error
Au(error)
dB
MODULE CHARACTERISTICS
(Ta=25ºC, VDD =9V, RL=10KΩ, (gain and all control 0dB), f=1KHZ unless otherwise specified)
PARAMETER
DC SUPPLY
SYMBOL
TEST CONDITION
MIN
TYP
MAX UNIT
DC Supply Voltage
Supply Current
VDD
IS
6
9
8
10
11
V
mA
GAIN & INPUT SELECTOR
Input Resistance
Clipping Level
RI G
VCL
Input1,2,3
35
2
50
2.5
100
70
KΩ
Vrms
dB
Input Separation(input 1,2,3)
Output Load resistance
Gain Range
SIN
80
2
RL
OUTL OUTR
KΩ
dB
GIN
11.25
Min. Gain
GINmin
GINmax
GSTEP
eIN
-1
0
11.25
3.75
2
1
dB
Max. Gain
dB
Adjacent Gain Steps
Input Noise
dB
G=11.25dB
uV
adjacent gain steps
G=18.75 to Av max
4
20
mV
mV
DC Shift Voltage Steps
VDC
4
VOLUME CONTROL
Input Resistance
RI V
Gv
Pin6,16
20
70
33
75
0
50
80
KΩ
dB
dB
dB
dB
dB
dB
Control Range
Min. Attenuation
AuMIN
AuMAX
AuSTEP
-1
1
Max. Attenuation
70
75
1.25
0
80
Adjacent Attenuation Steps
0.5
-1.25
-3
1.75
1.25
2
Au=0 to -20dB
Au=-20 to -60dB
Attenuation Set Error
EA
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U7313
CMOS IC
MODULE CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
ET
TEST CONDITION
MIN
TYP
MAX UNIT
Tracking Error
2
3
dB
mV
mV
Adjacent attenuation steps
from 0dB to Au max
0
DC Shift Voltage Steps
VDC
0.5
7.5
BASS CONTROL
Control Range
Gb
BSTEP
RB
Center freq=100HZ
±12
1
±14
2
±16
3
dB
dB
KΩ
Adjacent Attenuation Steps
Internal Feedback Resistance
TREBLE CONTROL
Control Range
34
44
58
Gt
Center freq=20KHZ
±13
1
±14
2
±15
3
dB
dB
Adjacent Attenuation Steps
SPEAKER ATTENUATORS
Control Range
TSTEP
GS
SSTEP
EA
35
37.5
1.25
40
1.75
1.5
dB
dB
dB
dB
mV
mV
Adjacent Attenuation Steps
Attenuation Set Error
Output Mute Attenuation
0.5
AuMUTE
80
100
0
adjacent attenuation steps
from 0 to mute
3
DC Shift Voltage Steps
VDC
1
10
OUTPUTS
Clipping Level
VOCL
RL
d=0.3%
2
2
2.5
Vrms
KΩ
nF
Ω
Output Load Resistance
Output Load Capacitance
Output Resistance
CL
10
120
4.8
ROUT
VOUT
30
75
Output DC Voltage
4.2
4.5
V
EFFECT OF AUDIO PROCESSING
BW=20-20kHZ, flat
output muted
all gains=0dB
2.5
5
μV
μV
Output Noise
eN(OUT)
15
BW=20-20kHZ , a curve
all gains=0dB
3
μV
Signal to Noise Ratio
Distortion
S/N
d
all gains=0dB; VOUT=1Vrms
Au=0,VIN=1Vrms
106
0.01
0.09
0.04
103
0
dB
%
0.1
VIN=1Vrms
Au=-20dB
%
VIN=0.3Vrms
%
Channel Separation( left/right)
Total Tracking Error
S(channel)
Au(error)
80
dB
dB
dB
Au=0 to -20dB
1
2
Au=-20dB to -60dB
0
I2C BUS INPUT
Low
VIL
VIH
1
V
V
Input Voltage
High
3
μA
Input Current
IIN
-5
+5
Output Voltage SDA Acknowledge
VOUT
IOUT=1.6mA
0.4
V
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U7313
CMOS IC
APPLICATION CIRCUIT
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U7313
I2C BUS INTERFACE
CMOS IC
The master communicated with U7313 by two lines SDA and SCL which should connect pull-up resistors to positive
supply voltage. See the figure below.
BYTE FORMAT
The byte transferred from SDA line should contain 8 bit binary data, and followed an acknowledge bit. The MSB is
transferred first, Maximum clock speed is 100Kbit/s.Detail see the figures below.
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U7313
CMOS IC
ACKNOWLEDGE
The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The slave which
acknowledge pull down the SDA line during the acknowledge clock pulse. The SDA line keep in a stable low state.
The slave which has been addressed has to generate an acknowledge after receiving each byte. If the SDA line still
at the high level during the ninth clock pulse time, the master can generate the stop information to abort the transfer.
If want to abort the acknowledge information, the master can stop detecting the acknowledge by waits one clock
without checking, then sends the new data. This approach of course is less protected from misoperation and
decrease the noise immunity.
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U7313
CMOS IC
FUNCTION CONTROL
Chip address
MSB
LSB
0
1
0
0
0
1
0
0
Quick reference
MSB
LSB
FUNCTION
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
B2
0
B1
B1
B1
B1
B1
G1
0
B0
B0
B0
B0
B0
G0
C3
C3
A2
A2
A2
A2
A2
S2
C2
C2
A1
A1
A1
A1
A1
S1
C1
C1
A0
A0
A0
A0
A0
S0
C0
C0
Volume Control
Speaker LF
1
Speaker RF
0
Speaker LR
1
Speaker RR
0
Gain & Input Selector
Bass Control
Treble Control
1
1
1
Gain & input selector
MSB
LSB
G1 G0 S2 S1 S0
FUNCTION
Audio Switch
Stereo 1
Stereo 2
Stereo 3
Stereo4(nonuse)
LOUDNESS ON
LOUDNESS OFF
+11.25dB
+7.5dB
+3.75dB
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0dB
For example:
Input: stereo 3
Gain:+3.75dB
Loudness on
The 8 bit string is: 0 1 0 1 0 0 1 0
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U7313
CMOS IC
FUNCTION CONTROL(Cont.)
Volume control
MSB
LSB
A1
FUNCTION(dB)
0
0
B2
B1
B0
A2
0
0
0
0
A0
0
1
0
1
0
0
1
1
0
0
-1.25
-2.5
-3.75
-5
1
0
1
1
1
0
1
1
1
0
1
-6.25
-7.5
-8.75
0
0
B2
0
0
0
0
1
1
1
1
B1
B0
A2
A1
A0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
-10
-20
-30
-40
-50
-60
-70
For example:
Bass control
Volume -32.5dB the 8 bit string is: 0 0 0 1 1 0 1 0
0
1
1
0
C3 C2
C1 C0
FUNCTION(dB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
-14
-12
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
For example:
Bass control -4dB the 8 bit string is: 0 1 1 0 0 1 0 1
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U7313
CMOS IC
FUNCTION CONTROL(Cont.)
Treble control
0
1
1
1
C3 C2
C1 C0
FUNCTION (dB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
-14
-12
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
For example:
Treble control -4dB the 8 bit string is: 0 1 1 1 0 1 0 1
Speaker attenuators
MSB
LSB
FUNCTION (dB)
1
1
1
1
0
0
1
1
0
1
0
1
B1 B0
B1 B0
B1 B0
B1 B0
A2 A1 A0
A2 A1 A0
A2 A1 A0
A2 A1 A0
SPEAKER LF
SPEAKER RF
SPEAKER LR
SPEAKER RR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
0
0
1
0
1
1
0
1
1
1
-10
-20
-30
1
1
1
Mute
For example: Output SPEAKER RF -15dB
The 8 bit string is: 1 0 1 0 1 1 0 0
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U7313
CMOS IC
TYPICAL CHARACTERISTICS
Figure 1: Volume+Loudness attenuation vs. Frequency vs. Volume control (C10,C11=100nF)
Figure 2: Volume+Loudness attenuation vs. Frequency vs. External Capacitor (Volume=-40dB)
Figure 3: Tone response(bass and treble control vs. amplitude-frequency response)
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U7313
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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