U74HC4046G-P16-R [UTC]
Phase Locked Loop, CMOS, PDSO16, HALOGEN FREE, PLASTIC, TSSOP-16;
| 型号： | U74HC4046G-P16-R |
| 厂家： | 
Unisonic Technologies |
| 描述： | Phase Locked Loop, CMOS, PDSO16, HALOGEN FREE, PLASTIC, TSSOP-16 光电二极管 |
| 文件： | 总18页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
U74HC4046
CMOS IC
PHASE LOCKED LOOP WITH VCO
DESCRIPTION
The U74HC4046 is a phase-locked-loop circuit including a linear
voltage-controlled oscillator (VCO), three different phase comparators
(PC1, PC2 and PC3), a common signal input amplifier and a common
comparator input.
SOP-16
The signal can be directly coupled to large voltage signals or with a
series capacitor coupled to small voltage signals. Small voltage signals
can be kept within the linear region of the input amplifiers with a self-bias
input circuit. The U74HC4046 and a passive low-pass filter form a
second-order loop PLL. With a linear op-amp, the VCO achieves
excellent linearity.
The VCO requires an external capacitor and resistor. R1 (between
R1 and GND) and capacitor C1 (between C1A and C1B) determine the
frequency range of the VCO. R2 (between R2 and GND) enables the
VCO to have a frequency offset if required.
TSSOP-16
For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a
wide choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is
provided in order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold
voltage lower than the VCO input voltage, but the DEMOUT voltage of U74HC4046 equals the VCO input voltage.
When DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT
should be left open. The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the
comparator input (COMPIN). If the VCO input is held at a constant DC level, the VCO output signal has a duty factor
of 50% (maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and
demodulator, while a HIGH level turns both off to minimize standby power consumption.
FEATURES
* Low Power Consumption
* Operating Power Supply Voltage Range: Digital Section 2.0 to 6.0 V
VCO Section 3.0 to 6.0 V
* Up to 17 MHz (typ.) Centre Frequency at VCC = 4.5 V
* Excellent VCO Frequency Linearity
* VCO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption
* Minimal Frequency Drift
* Three Phase Comparators: EXCLUSIVE-OR;
Edge-Triggered JK Flip-Flop;
Edge-Triggered RS Flip-Flop
* Zero Voltage Offset due to OP-Amp Buffering
* Standard Output Capability
* MSI ICC Category
ORDERING INFORMATION
Ordering Number
Package
SOP-16
Packing
Tape Reel
Tape Reel
U74HC4046G-S16-R
U74HC4046G-P16-R
TSSOP-16
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U74HC4046
CMOS IC
PIN CONFIGURATION
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
1
2
3
4
5
6
7
8
16
15 PC3OUT
14 SIGIN
13 PC2OUT
VCC
12
11
R2
R1
C1A
C1B
10 DEMOUT
VCOIN
GND
9
LOGIC SYMBOL
IEC SYMBOL
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U74HC4046
CMOS IC
PIN DESCRIPTION
PIN NO
SYMBOL
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
FUNCTION
Phase comparator pulse output
Phase comparator 1output
Comparator input
1
2
3
4
VCO output
5
Inhibit input
6
C1A
Capacitor C1 connection A
Capacitor C1 connection B
Ground
7
C1B
8
GND
9
VCOIN
DEMOUT
R1
VCO input
10
11
12
13
14
15
16
Demodulator output
Resistor R1 connection
Resistor R2 connection
Phase comparator 2 output
Signal input
R2
PC2OUT
SIGIN
PC3OUT
VCC
Phase comparator 3 output
Positive supply voltage
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U74HC4046
CMOS IC
FUNCTIONAL DIAGRAM
LOGIC DIAGRAM
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U74HC4046
CMOS IC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VCC
TEST CONDITIONS
MIN TYP MAX UNIT
DC Supply Voltage
-0.5
+7
20
20
25
V
DC Input Diode Current
DC Output Diode Current
DC Output Source or Sink Current
±IIK
for VIN <−0.5 V or VIN > VCC + 0.5 V
for VOUT <−0.5 V or VOUT > VCC + 0.5 V
for −0.5 V < VOUT < VCC + 0.5 V
mA
mA
mA
±IOK
±IO
±ICC
±IGND
;
DC VCC or GND Current
50
mA
Power Dissipation per Package
Plastic DIL
for temperature range: − 40 to +125 °C
above +70 °C: derate linearly with 12 mW/K
for temperature range: − 40 to +125 °C
above +70 °C: derate linearly with 8 mW/K
750
mW
PD
Power Dissipation per Package
Plastic Mini-Pack(SO)
500
mW
°C
Storage Temperature Range
TSTG
-65
+150
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VCC
TEST CONDITIONS
MIN TYP MAX UNIT
DC Supply Voltage
3.0
2.0
0
5.0
5.0
6.0
6.0
V
V
DC Supply Voltage if VCO Section is not used
DC Input Voltage Range
VCC
VIN
VCC
VCC
V
DC Output Voltage Range
VOUT
0
V
VCC = 2.0 V
VCC = 4.5 V
6.0 1000
ns
ns
ns
°C
°C
Input Rise and Fall Times (pin 5)
Ambient Operating Temperature
tR, tF
6.0
6.0
500
400
VCC = 6.0 V
see DC and AC
CHARACTERISTICS
-40
-40
+85
TOPR
+125
QUICK REFERENCE DATA (GND = 5V; T = 25 °C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
VCO Centre Frequency
fo
C1 = 40 pF; R1 = 3 kΩ;VCC = 5V
19
3.5
24
MHz
pF
Input Capacitance (pin 5)
CIN
CPD
(Note)
pF
Power Dissipation Capacitance per Package
Note : CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC2 × f + (C × V 2 × fO )
∑
i
L
CC
where: fi = input frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
fo =output frequency in MHz;
2
= sum of outputs.
(C × V × fO )
∑
L
CC
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U74HC4046
CMOS IC
DC CHARACTERISTICS (TA =25°C , unless otherwise specified)
Quiescent Supply Current (Voltages are referenced to GND (ground = 0 V))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
Pins 3, 5 and 14 at VCC
VCC=6.0V Pin 9 at GND; IIN at pins
3 and 14 to be excluded
;
Quiescent Supply Current
(VCO Disabled)
ICC
8.0
μA
Phase Comparator Section
PARAMETER
SYMBOL
VIH
TEST CONDITIONS
VCC=2.0V
MIN TYP MAX UNIT
DC Coupled
(HIGH Level Input Voltage SIGIN,
COMPIN)
1.5
3.15
4.2
1.2
2.4
3.2
0.8
2.1
2.8
2.0
4.5
6.0
V
V
VCC=4.5V
VCC=6.0V
DC Coupled
(LOW Level Input Voltage SIGIN,
COMPIN)
VCC=2.0V
0.5
1.35
1.8
VIL
VCC=4.5V
VCC=6.0V
VCC=2.0V
VI=VIH or VIL,
1.9
4.4
5.9
HIGH Level Output Voltage
VOH
V
V
V
V
VCC=4.5V
(PCPOUT, PCnOUT
)
- IOUT = 20μA
VCC=6.0V
HIGH Level Output Voltage
(PCPOUT, PCnOUT)
VCC=4.5V, - IO = 4.0 mA 3.98 4.32
VCC=6.0V ,- IO = 5.2 mA 5.48 5.81
VOH
VI=VIH or VIL,
VCC=2.0V
VCC=4.5V
0
0
0
0.1
0.1
0.1
LOW Level Output Voltage
VI=VIH or VIL,
- IOUT = 20μA
VOL
VOL
(PCPOUT, PCnOUT
)
VCC=6.0V
LOW Level Output Voltage
(PCPOUT, PCnOUT
VCC=4.5V , IO = 4.0 mA
VCC=6.0V , IO = 5.2 mA
VCC=2.0V
0.15 0.26
0.16 0.26
3.0
VI=VIH or VIL,
)
Input Leakage Current
(SIGIN, COMPIN )
VI = VCC or VCC=3.0V
7.0
±IIN
μA
GND
VCC=4.5V
VCC=6.0V
18.0
30.0
V
OUT = VCC or GND, VI=VIH or VIL,
3-State (OFF-state current PC2OUT
Input Resistance (SIGIN, COMPIN)
)
±IOZ
RIN
0.5
μA
VCC=6.0V
VCC=3.0V VIN at self-bias operating
800
250
150
kΩ
kΩ
kΩ
point; ΔVI = 0.5V;
VCC=4.5V
(Fig. 7)
VCC=6.0V
VCO Section (Voltages are Referenced to GND (Ground = 0 V))
PARAMETER
SYMBOL
VIH
TEST CONDITIONS
VCC=3.0V
MIN TYP MAX UNIT
2.1
3.15
4.2
1.7
2.4
3.2
1.3
HIGH Level Input Voltage INH
V
V
VCC=4.5V
VCC=6.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V
0.9
LOW Level Input Voltage INH
VIL
2.1 1.35
2.8
3.0
4.5
6.0
1.8
VCC=3.0V
VCC=4.5V
2.9
4.4
5.9
VI=VIH or VIL,
- IOUT = 20μA
HIGH Level Output Voltage VCOOUT
HIGH Level Output Voltage VCOOUT
LOW Level Output Voltage VCOOUT
LOW Level Output Voltage VCOOUT
VOH
VOH
VOL
VOL
V
V
V
VCC=6.0V
VCC=4.5V, -IOUT = 4.0 mA 3.98 4.32
VCC=6.0V, -IOUT = 5.2 mA 5.48 5.81
VI=VIH or VIL
VCC=3.0V
VCC=4.5V
0
0
0
0.1
0.1
0.1
VI=VIH or VIL,
IOUT = 20μA
VCC=6.0V
VCC=4.5V, IOUT = 4.0 mA
VCC=6.0V, IOUT = 5.2 mA
VCC=4.5V, IOUT = 4.0 mA
VCC=6.0V, IOUT = 5.2 mA
0.15 0.26
0.16 0.26
0.4
VI=VIH or VIL
VI=VIH or VIL
V
V
LOW Level Output Voltage C1A, C1B
Input Leakage Current(INH, VCOIN)
VOL
±IIN
0.4
VCC=6.0V, VI=VCC or GND
0.1
μA
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U74HC4046
CMOS IC
DC CHARACTERISTICS(Cont.)
VCO Section (Cont.)
PARAMETER
SYMBOL
R1
TEST CONDITIONS
VCC=3.0V
MIN TYP MAX UNIT
3.0
3.0
3.0
3.0
3.0
3.0
40
300
300
300
300
300
300
kΩ
kΩ
pF
V
VCC=4.5V
VCC=6.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V
VCC=3.0V
VCC=4.5V
Resistance Range
R2
C1
(Note)
Capacitor Range
40
VCC=6.0V
40
VCC=3.0V Over the range
1.1
1.1
1.1
1.9
3.4
4.9
specified for R1; for
linearity (Fig10)
Operating Voltage Range at VCOIN
VVCOIN
VCC=4.5V
VCC=6.0V
Note: The parallel value of R1 and R2 should be more than 2.7 kꢀ. Optimum performance is achieved when
R1 and/ or R2 are/is > 10 kꢀ.
Demodulator Section (Voltages are Referenced to GND (Ground = 0 V))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
VCC=3.0V
50
50
50
300
300
300
At RS > 300 kꢀ
the leakage current can
influence VDEMOUT
Resistor Range
RS
kꢀ
mV
ꢀ
VCC=4.5V
VCC=6.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V
±30
±20
±10
25
VI = VVCOIN =1/2 Vcc;
values taken over RS
range
Offset Voltage VCOIN to VDEMOUT
VOFF
Dynamic Output Resistance at
DEMOUT
RD
VDEMOUT = 1/2 Vcc
25
25
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U74HC4046
CMOS IC
AC CHARACTERISTICS (TA =25°C , unless otherwise specified)
Phase Comparator Section (GND = 0 V; tR = tF =6ns; CL = 50pF)
PARAMETER
SYMBOL
TEST CONDITIONS
VCC=2.0V
MIN TYP MAX UNIT
96
35
28
77
28
22
83
30
24
99
36
29
19
7
340
68
Propagation Delay SIGIN,
COMPIN to PCPOUT
tPHL/ tPLH
Fig.8
Fig.8
Fig.9
Fig.9
Fig.8
ns
ns
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=3.0V
VCC=4.5V
58
270
54
Propagation Delay SIGIN,
COMPIN to PC3OUT
tPHL/ tPLH
tPZH/ tPZL
tPHZ/ tPLZ
tPHZ/ tPLZ
46
280
56
3-State Output Enable Time
SIGIN, COMPIN to PC2OUT
ns
ns
ns
48
325
65
3-State Output Disable Time
SIGIN, COMPIN to PC2OUT
55
75
Output Transition Time
15
6
13
9
AC Coupled Input Sensitivity
(Peak-To-Peak Value)
at SIGIN or COMPIN
11
15
33
VIN(P-P)
fi = 1MHz
mV
VCC=6.0V
VCO Section (GND = 0 V; tR = tF = 6 ns; CL = 50 pF)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
VCC=3.0V
VCC=4.5V
VIN = VVCOIN = 1/2 VCC
R1 = 100 kꢀ; R2 = ∞;
;
Frequency Stability with
Temperature Change
Δf/T
%/K
C1= 100 pF
VCC=6.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V
VCC=3.0V
VCC=4.5V
7.0 10.0
VVCOIN = 1/2 VCC
R1 = 3 kꢀ;R2 = ∞;
;
VCO Centre Frequency
(duty Factor = 50%)
fo
MHz
%
11.0 17.0
C1 = 40 pF
13.0 21.0
1.0
0.4
0.3
50
R1 = 100 kꢀ; R2 = ∞;
ΔfVCO
VCO Frequency Linearity
Duty Factor at VCOOUT
C1 = 100 pF;(Fig.10)
VCC=6.0V
VCC=3.0V
VCC=4.5V
δVCO
%
50
VCC=6.0V
50
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U74HC4046
CMOS IC
PHASE COMPARATORS
If the signal swing is between the standard HC family input logic levels, the signal input (SIGIN) can be directly
coupled to the self-biasing amplifier at pin 14. Capacitive coupling is required for signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. To obtain the maximum locking range, the signal and comparator input
frequencies (fI) must have a 50% duty factor.
The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is:
VCC
π
VDEMOUT
=
(φSIGIN −φCOMPIN )
Where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter).
VCC
π
The phase comparator gain is:
KP =
( V / r )
As shown in Fig.1, the average output voltage from PC1, fed to the VCO input via the low-pass filter and seen
at the demodulator output at pin 10 (VDEMOUT) is the resultant of the phase differences of signals (SIGIN) and the
comparator input (COMPIN). The average of VDEMOUT is equal to VCC/2 when there is no signal or noise at SIGIN and
with this input the VCO oscillates at the centre frequency (fO). As shown in Fig.2 it is the typical waveforms for the
PC1 loop locked at fO.
π
Fig.1 Phase comparator 1: average output voltage versus input phase difference.
SIGIN
COMPIN
VCOOUT
PC1OUT
VCC
VCOIN
GND
Fig.2 Typical waveforms for PLL using phase comparator 1, loop locked at fO.
The frequency capture range (2fc) is he frequency range of input signals on which the PLL will lock if it was
initially out-of-lock. The frequency lock range (2fL) is the frequency range of input signals on which the loop will stay
locked if it was initially in lock. The capture range is smaller or equal to the lock range.
With PC1, the low-pass filter characteristics determine the capture range which can be made as large as the
lock range.
This configuration retains lock even with very noisy input signals. Typical behavior of this type of phase
comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency.
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CMOS IC
PHASE COMPARATORS (Cont.)
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detector. If the PLL is using the comparator, the loop is
controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 is
comprised of two D-type flip-flops, control-gating and a 3-state output stage. The circuit function is as an up-down
counter (Logic Diagram) for SIGIN causes an up-count and COMPIN causes a down-count.
The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is
VCC
4π
VDEMOUT
=
(φSIGIN −φCOMPIN )
where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter).
VCC
4π
The phase comparator gain is:
KP =
( V / r )
As shown in Fig.3, VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN. Typical
waveforms for the PC2 loop locked at fo are shown in Fig.4.
4π
Fig.3 Phase comparator 2: average output voltage versus input phase difference.
Fig.4 Typical waveforms for PLL using phase comparator 2, loop locked at fo.
If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type
output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of
SIGIN lags that of COMPIN, the n-type driver is held “ON”.
If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the
input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the
frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the
voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs
are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is
in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator
pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition.
For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO.
And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of
the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the
capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when
no signal present at SIGIN.
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U74HC4046
CMOS IC
PHASE COMPARATORS (Cont.)
Phase comparator 3 (PC3)
This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. If this comparator is used,
the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. The
transfer characteristic of PC3, assuming ripple (fr = fj) is suppressed, is:
VCC
2π
VDEMOUT
=
(φSIGIN −φCOMPIN )
where VDEMOUT = VPC3OUT (via low-pass filter).
VCC
2π
The phase comparator gain is:
KP
=
( V / r )
As shown in Fig.5, the average output voltage from PC3, fed to the low-pass filter and seen at the demodulator
output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN. As shown in Fig.6, it is the
typical waveforms for the PC3 loop locked at fo.
VCC
VDEMOUT(AV)
1/2VCC
VCC
VDEMOUT = VPC3OUT
=
(
-
)
COMPIN
SIGIN
2π
0
DEMOUT = (
-
)
0
180
SIGIN
COMPIN
360
DEMOUT
Fig.5 Phase comparator 3: average output voltage versus input phase difference.
Fig.6 Typical waveforms for PLL using phase comparator 3, loop locked at fo.
The phase-to-output response characteristic of PC3 (Fig.5) differs from that of PC2, as the phase angle
between SIGIN and COMPIN varies between 0o and 360o and 180o is the centre frequency. And the voltage swing of
PC3 is greater than that of PC2 for input phase differences, but as a consequence the ripple content of VCO input
signal is higher. Both of the PLL lock range and capture range of this type of phase comparator are dependent on
the low-pass filter. The VCO adjusts to its lowest frequency via PC3, when no signal present at SIGIN.
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FIGURE REFERENCES FOR DC CHARACTERISTICS
IIN
VIN
VIN
Self-Bias Operating Point
Fig.7 Typical input resistance curve at SIGIN, COMPIN.
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U74HC4046
CMOS IC
AC WAVEFORMS
SIGIN, COMPIN
VM
tPHL
tPLH
PCPOUT
PC1OUT
PC3OUT
VM
VM= 50%, VH= 90%, VL= 10%
tTHL
tTLH
Fig.8 Waveforms showing input (SIGIN, COMPIN) to output (PCPOUT, PC1OUT, PC3OUT) propagation delays and the
output transition times.
Fig.9 Waveforms showing the 3-state enable and disable times for PC2OUT
.
Fig.10 Definition of VCO frequency linearity: ∆V = 0.5 V over the VCC range:
For VCO linearity f’0 = (f1+f2)/2, linearity (f’0+f0)/f’0 ×100%
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U74HC4046
CMOS IC
APPLICATION INFORMATION
This is a reference for the values of external components to be used with the U74HC4046 in a PLL system.
The ranges of the values of the components:
Component Value
R1
R2
3 kꢀ ~ 300 kꢀ
3 kꢀ ~ 300 kꢀ
R1+R2
C1
Parallel value > 2.7 kꢀ
Greater than 40 pF
VCO Frequency Without Extra Offset (Phase comparator: PC1, PC2 or PC3)
Frequency Characteristic:
With R2 = ∞ and R1 between 3 kꢀ and 300 kꢀ, the characteristics of the VCO operation will be as shown in Fig.11
(Due to R1, C1 time constant a small offset remains when R2 = ∞).
Fig.11 Frequency characteristic of VCO operating without offset:
f0 = centre frequency; 2fL = frequency lock range.
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APPLICATION INFORMATION(Cont.)
VCO Frequency with Extra Offset (Phase Comparator: PC1, PC2 or PC3)
Frequency characteristic:
With R1 and R2 between 3 kꢀ and 300 kꢀ, the characteristics of the VCO operation will be as shown in Fig.12.
fVCO
fMAX
2fL
f0
due to R1, C1
fMIN
fOFF
due to R2, C1
VCC–0.9V
VCC
VCOIN
0.9V
½ VCC
Fig.12 Frequency characteristic of VCO operating with offset:
f0 = centre frequency; 2fL = frequency lock range.
PC1, PC2 or PC3
Selection of R1, R2 and C1
Given fo and fL, determine the value of R1×C1
Calculate fOFF from the equation fOFF = fO – 1.6fL
Obtain the values of C1 and R2
Calculate the value of R1 from the value of C1 and R1×C1.
Subject
Phase comparator
Design considerations
VCO adjusts to fo with φDEMOUT = 90° and VVCONIN = 1/2 VCD (Fig.1).
VCO adjusts to fo with φDEMOUT = -360° and VVCONIN = min. (Fig.3).
VCO adjusts to fo with φDEMOUT = -360° and VVCONIN = min. (Fig.5).
PC1
PC2
PC3
PLL Conditions with no
Signal at the SIGIN Input
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APPLICATION INFORMATION(Cont.)
PLL Frequency Capture Range (Phase comparator: PC1, PC2 or PC3)
Loop filter component selection
F
( jω)
τ
ω
τ
1
A small capture range (2fC) is obtained if
2fC ≈
2π fL /τ
π
Fig.13 Simple loop filter for PLL without offset; R3 ≥ 500 ꢀ.
F
( jω)
R4
m =
τ
τ
R3 + R4
ω
1/τ3 1/τ 2
τ
τ
τ
Fig.14 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 ꢀ.
Subject
Phase comparator Design considerations
PC1 or PC3
PC2
Yes
No
PLL Locks on Harmonics at Centre Frequency
PC1
High
Low
Noise Rejection at Signal Input
PC2 or PC3
PC1
fr = 2fi, large ripple content at φDEMOUT = 90°
fr = fi, small ripple content at φDEMOUT = 0°
fr = fi, large ripple content at φDEMOUT = 180°
AC Ripple Content when PLL is Locked
PC2
PC3
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PLL DESIGN EXAMPLE
Fig.15 Frequency Synthesizer.
The parameters of the frequency synthesizer in Fig.15:
Output frequency: 2 MHz to 3 MHz
Frequency steps: 100kHz
Settling time: 1ms
Overshoot: < 20%
The Open-Loop Gain is:
H(s)×G(s) = Kp ×Kf ×Ko × Kn
Where: Kp = phase comparator gain
Kf = low-pass filter transfer gain
Ko = Kv/s VCO gain
Kn = 1/n divider ratio
The programmable counter ratio Kn can be found as follows:
fout
2MHz
NMin
=
=
= 20
fstep 100kHz
fout
3MHz
NMax
=
=
= 30
fstep 100kHz
The VCO is set by the values of R1, R2 and C1, R2 = 10 kꢀ (adjustable). The values can be determined using the
information in the section “DESIGN CONSIDERATIONS”.
With fo = 2.5MHz and fL =500 kHz this gives the following values (VCC = 5.0 V):
R1 = 10 kꢀ; R2 = 10 kꢀ; C1 = 500 pF
2fL × 2×π
0.9 − (VCC − 0.9)
1MHz
3.2
KV
=
=
× 2π ≈ 2×106 r / s / V
The VCO gain is:
VCC
Kp =
= 0.4V / s
The gain of the phase comparator is:
The transfer gain of the filter is given by:
4π
1+τ2S
Kf =
1+ (τ1 +τ2 )S
Where:
and
τ2 = R4C2
τ1 = R3C2
The characteristics equation is: 1 + H(S) × G(S) = 0
1+ Kp ×Kv ×Kn ×τ
(τ1 +τ2 )
Kp ×Kv ×Kn
(τ1 +τ2 )
S2 +
2 S +
= 0
This results in:
Kp ×Kv ×Kn
(τ1 +τ2 )
ωn =
The natural frequency ωn is defined as follows:
1+ Kp ×Kv ×Kn ×τ2
(τ1 +τ2 )
1
ζ =
×
Damping Value ζ is Defined as follows:
2ωn
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CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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