UB264BL-AF-P08-R [UTC]
LION BATTERY PROTECTION IC FOR 2-SERIAL, 3-SERIAL OR 4-SERIAL-CELL PACK;
| 型号： | UB264BL-AF-P08-R |
| 厂家： | 
Unisonic Technologies |
| 描述： | LION BATTERY PROTECTION IC FOR 2-SERIAL, 3-SERIAL OR 4-SERIAL-CELL PACK |
| 文件： | 总11页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
UB264B
Preliminary
CMOS IC
LION BATTERY PROTECTION
IC FOR 2-SERIAL, 3-SERIAL,
OR 4-SERIAL-CELL PACK
(SECONDARY PROTECTION)
DESCRIPTION
The UTC UB264B Series is secondary protection IC for 2-, 3-, or
4-Cell lithium-ion rechargeable battery packs, and incorporates a
high-accuracy voltage detection circuit.
The UTC UB264B Series also includes a high accuracy delay
circuit for over voltage detection time without external capacitors.
FEATURES
*
High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n=1 to 4): 4.30V to 4.80V (in
50mV steps)
Overcharge hysteresis voltage n (n=1 to 4): -0.52V±0.21V,
−0.39V±0.16V, −0.26V±0.11V, −0.13V±0.06V, None
Delay times for overcharge detection can be set by an internal
circuit without external capacitors
*
*
*
*
*
*
*
*
Output latch function after overcharge detection
CMOS output active “H”
Wide operating voltage range 3.6V to 24V
Wide operating temperature range −40°C to +85°C
Low current consumption: 2.5μA typ. (+25°C) at 3.5V for
each cell
ORDERING INFORMATION
Ordering Number
Package
Packing
Lead Free
Halogen Free
UB264BL-P08-R
UB264BG-P08-R
TSSOP-8
Tape Reel
Note: xx: Output Voltage, refer SERIAL CODE LIST.
UB264BG-xx-P08-R
(1)Packing Type
(1) R: Tape Reel
(2)Package Type
(2) P08: TSSOP-8
(3)Output Voltage Code
(4)Green Package
(3) xx: Refer to SERIAL CODE LIST
(4) G: Halogen Free and Lead Free, L: Lead Free
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Copyright © 2017 Unisonic Technologies Co., Ltd
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UB264B
Preliminary
CMOS IC
SERIAL CODE LIST
OVERCHARGE OVERCHARGE OVERCHARGE OVERCHARGE
DETECTION
VOLTAGE
[VCU](V)
HYSTERSIS
VOLTAGE
[VHC](V)
DETECTION
DELAY TIME
[tCU](S)
RELEASE
DELAY TIME
[tCL](mS)
MODEL
CODE
OUTPUT FORM
CMOS output
active “H”
AA
AB
AC
AD
AE
AF
AG
AH
4.45±0.050
4.35±0.050
4.50±0.050
4.35±0.050
4.30±0.050
4.45±0.050
4.30±0.050
4.40±0.050
-0.39±0.16
-0.39±0.16
-0.39±0.16
-0.39±0.16
-0.39±0.16
-0.39±0.16
-0.39±0.16
-0.39±0.16
4.0±1.0
4.0±1.0
4.0±1.0
2.0±0.5
4.0±1.0
2.0±0.5
2.0±0.5
4.0±1.0
60.0±20.0
60.0±20.0
60.0±20.0
30.0±10.0
60.0±20.0
30.0±10.0
30.0±10.0
60.0±20.0
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
UB264B
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
MARKING
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UB264B
Preliminary
CMOS IC
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO.
PIN NAME
VDD
DESCRIPTION
1
2
Positive power input pin
SENSE
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative power input pin
3
4
5
6
VC1
VC2
VC3
VSS
Negative voltage connection pin of battery 4
Overcharge detection latch reset pin
7
8
CTL
CO
FET gate connection pin for charge
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UB264B
Preliminary
CMOS IC
BLOCK DIAGRAM
SENSE
VDD
Oscillator
Overcharge
Detector 1
VC1
Overcharge
Detector 2
VC2
VC3
VSS
Divider
CO
Overcharge
Detector 3
Control
Logic
CTL
Overcharge
Detector 4
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UB264B
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING (TA=25°C, unless otherwise specified)
PARAMETER
SYMBOL
VDS
RATINGS
VSS −0.3 ~ VSS+26
VSS −0.3 ~ VDD+0.3
VSS −0.3 ~ VDD+0.3
650
UNIT
V
Input Voltage Between VDD And VSS
Input Pin Voltage
VIN
V
CO Output Pin Voltage
VCO
V
Power Dissipation (Note 2)
Operation Ambient Temperature
Storage Temperature
PD
mW
°C
°C
Topr
−40 ~ +85
Tstg
−40 ~ +125
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. When mounted on printed circuit board
ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNIT
DETECTION VOLTAGE
Overcharge Detection Voltage
n (n = 1, 2, 3, 4)
VCUn
0.050
−
VCUn+
0.050
VCUn
VHCn
4.30 ~ 4.80 V, adjustable
HCn=−0.52 ±0.21V, −0.39 ±0.16V,
VCUn
VHCn
V
V
Overcharge Hysteresis
Voltage n (n = 1, 2, 3, 4)
DELAY TIME
V
−0.26 ±0.11V, −0.13 ±0.06V, None
Overcharge Detection Delay
Time
3.0
1.5
40
20
10
5
4.0
2.0
60
30
15
7.5
60
30
5.0
2.5
80
40
20
10
80
40
3.0
tCU
tCL
tTR
s
For AD, AF and AG products
For AD, AF and AG products
For AD, AF and AG products
For AD, AF and AG products
Overcharge Release Delay
Time
ms
ms
Overcharge Timer Reset
Delay Time
Transition Time To Test
Mode(Note1)
40
20
tTST
tCTL
ms
ms
CTL Pin Response Time
INPUT VOLTAGE
Operating Voltage Between
VDSOP
VCTLH
VCTLL
3.6
24
V
V
V
VDD And VSS
VDD×
CTL Input “H” Voltage
CTL Input “L” Voltage
0.95
VDD×
0.4
INPUT CURRENT
Current Consumption During
Operation
IOPE
V1=V2=V3=V4=3.5V
2.5
2.0
10
10
μA
μA
Current Consumption During
Overdischarge
IOPED V1=V2=V3=V4=2.3V
ISENSE V1=V2=V3=V4=3.5V
SENSE Pin Current
VC1 Pin Current
1.5
0
6.0
0.5
0.5
0.5
2.0
μA
μA
μA
μA
μA
μA
IVC1
IVC2
V1=V2=V3=V4=3.5V
-0.5
-0.5
-0.5
1.0
VC2 Pin Current
V1=V2=V3=V4= 3.5 V
0
VC3 Pin Current
IVC3
V1=V2=V3=V4=3.5 V
0
CTL Pin “H” Current
CTL Pin “L” Current
OUTPUT CURRENT
CO Pin Sink Current
CO Pin Source Current
ICTLH
ICTLL
V1=V2=V3=V4=3.5 V, VCTL=VDD
V1=V2=V3=V4=3.5 V, VCTL=0 V
1.5
-0.1
ICOL
ICOH
VCOP=VSS+0.5V
0.4
20
mA
VCOP=VDD−0.5V
μA
Note: 1. Test conditions: V1=V2= V3=V4=3.5 V, VDD ≥ VSENSE + 8.5V.
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UB264B
Preliminary
CMOS IC
OPERATING
1. Overcharge Detection
Under normal conditions, when the voltage of any one cell battery exceeds the overcharge detection voltage (VCU
)
during charging, and after the state is retained for the overcharge detection delay time (tCU), CO will become “H”.
This state is called overcharge. Attaching FET to the CO pin provides charge control and a second protection.
Only the voltage of all the batteries decreases below the total of the overcharge detection voltage (VCU) and the
overcharge hysteresis voltage (VHC) and the state is retained for the overcharge release delay time (tCL) or longer,
the overcharge status is released; however, CO stays at “H”. When the CTL pin is switched from “L” to “H”, CO
becomes “L”.
2. Overcharge Timer Reset
When an overcharge release noise that forces the voltage of the battery temporarily below the overcharge
detection voltage (VCU) is input during the overcharge detection delay time (tCU) from when VCU is exceeded to when
charging is stopped, tCU is continuously counted if the time the overcharge release noise persists is shorter than the
overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists
is tTR or longer, counting of tCU is reset once. After that, when VCU has been exceeded, counting tCU resumes.
3. CTL Pin
The CTL pin is used to control the output voltage of the CO pin. In the UTC UB264B Series, when the CTL pin is
switched from “L” to “H”, a reset signal is output to the overcharge detection latch and CO becomes “L”.
CTL PIN
“H”
CO PIN
Without latch
Open
Normal state (Note 1)
Normal state (Note 1)
Latch reset (Note 2)
-
“L”
“L”→ “H”
“H” →“L”
Notes: 1. The state is controlled by the overcharge detection circuit.
2. Latch reset becomes effective when the voltages of all the
batteries are lower than the total of the overcharge detection
voltage (VCU) and the overcharge hysteresis voltage (VHC) and the
overcharge release delay time (tCL) has elapsed.
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UB264B
Preliminary
CMOS IC
OPERATING(Cont.)
Notes: 1. The reverse voltage “H” to “L” or “L” to “H” of CTL pin is VDD pin voltage −2.8 V (Typ.), does not have
the hysteresis.
2. Since the CTL pin implements high resistance of 8MΩ to 12MΩ for pull down, be careful of external
noise application. If an external noise is applied, CO may become “H”. Perform thorough evaluation
using the actual application.
3. In the UTC UB264B Series, when the CTL pin is open or “L”, CO latches “H”. When the VDD pin
voltage is decreased to the UVLO voltage of 2 V (Typ.) or lower, the latch is reset.
4. Test Mode
In the UTC UB264B Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the SENSE pin voltage for at
least 80ms (V1=V2=V3=V4=3.5 V, Ta=25°C). The status is retained by the internal latch and the test mode is
retained even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin. When CO becomes
“H” when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the
UTC UB264B Series exits from the test mode.
SENSE pin voltage
VDD pin voltage
>8.5V
Pin voltage
VHCn
VCUn
Battery voltage
(n=1 to 4)
Test mode
CO Pin
tTST
tCU/64
tCL
Notes: 1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the UTC
UB264B Series returns to the normal mode.
2. Set the test mode when no batteries are overcharged.
3. The overcharge release delay time (tCL) is not shortened in the test mode.
4. The overcharge timer reset delay time (tTR) is not shortened in the test mode.
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UB264B
Preliminary
CMOS IC
TIMING CHARTS
1. Overcharge Detection Operation
VHCn
VCUn
Battery voltage
(n=1 to 4)
CTL Pin
CO Pin
tTR or
longer
t
TR or shorter
tCL
tCU
tCU or shorter
2. Overcharge Timer Reset Operation
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UB264B
Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT
1. 4-serial cell
SC Protector
EB+
VDD
RVDD
R1
CVDD
C1
SENSE
VC1
BAT1
BAT2
R2
UTC
C2
UB264B
Series
VC2
VC3
FET
R3
R4
C3
BAT3
BAT4
CO
DP
C4
VSS
CTL
External
input
RCTL
EB-
2. 3-serial cell
SC Protector
EB+
VDD
RVDD
R1
CVDD
C1
SENSE
VC1
BAT1
BAT2
R2
UTC
C2
UB264B
Series
VC2
VC3
FET
R3
C3
BAT3
CO
DP
VSS
CTL
External
input
RCTL
EB-
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UB264B
Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT(Cont.)
3. 2-serial cell
SC Protector
EB+
VDD
RVDD
R1
CVDD
C1
SENSE
VC1
BAT1
BAT2
R2
UTC
C2
UB264B
Series
VC2
VC3
FET
CO
DP
VSS
CTL
External
input
RCTL
EB-
Constants for External Components
NO.
1
PART
MIN
0.1
0.01
50
TYP
1
MAX
10
UNIT
KΩ
μF
Ω
R1 to R4
2
C1 to C4, CVDD
RVDD
0.1
100
100
1
3
500
500
4
RCTL
0
Ω
Notes: 1. the examples of connection shown above and the constants will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. Set the same constants to R1 to R4 and to C1 to C4 and CVDD
.
3. Set RVDD, C1 to C4 and CVDD so that the condition (RVDD) × (C1 to C4, CVDD) ≥ 5 × 10−6 is satisfied.
4. T Set R1 to R4, C1 to C4, and CVDD so that the condition (R1 to R4) × (C1 to C4, CVDD) ≥ 1 × 10−4 is
satisfied.
5. In some application circuits, even if an overcharged battery is not included, the order of connecting
batteries may be restricted to prevent transient output of CO detection pulses when the batteries are
connected. Perform thorough evaluation with the actual application circuit.
6. Since “H” may be output at CO transiently when the battery is being connected, connect the positive
terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
7. Before the battery connection, short-circuit the battery side pins RVDD and R1.
8. In the UTC UB264B Series, normally input “L” to the external input, and input “H” when releasing the
latch that maintains CO at “H” after overcharge detection.
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UB264B
Preliminary
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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