UPS604L-D08-T [UTC]
HIGH PERFORMANCE CURRENT MODE POWER SWITCH; 高性能电流模式电源开关
| 型号： | UPS604L-D08-T |
| 厂家： | 
Unisonic Technologies |
| 描述： | HIGH PERFORMANCE CURRENT MODE POWER SWITCH |
| 文件： | 总12页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
UPS604
LINEAR INTEGRATED CIRCUIT
HIGH PERFORMANCE
CURRENT MODE POWER
SWITCH
DESCRIPTION
The UTC UPS604 is designed to provide several special
enhancements to satisfy the needs, for example, Power-Saving
mode for low standby power (<0.3W), Frequency Hopping ,
Constant Output Power Limiting , Slope Compensation ,Over
Current Protection (OCP), Over Voltage Protection (OVP), Over
Load Protection (OLP), Under Voltage Lock Out (UVLO), Short
Circuit Protection (SCP) , Over Temperature Protection (OTP) etc.
IC will be shutdown or can auto-restart in situations.
DIP-8
FEATURE
* Low startup current (about 22μA)
* Fixed switching frequency(Norm. is 68KHz)
* Frequency hopping for Improved EMI Performance.
* Lower than 0.3W Standby Power Design
* Linearly decreasing frequency to 26KHz during light load
* Soft start
* Internal Slope Compensation
* Constant Power Limiting for universal AC input Range
* Gate Output Maximum Voltage Clamp(15V)
* Max duty cycle 74%
* Over temperature protection
* Overload protection
* Over voltage protection
* Leading edge blanking
* Cycle-by-Cycle current limiting
* Under Voltage Lock Out
* Short Circuit Protection
ORDERING INFORMATION
Ordering Number
Package
DIP-8
Packing
Tube
Lead Free
Halogen Free
UPS604G-D08-T
UPS604L-D08-T
www.unisonic.com.tw
Copyright © 2011 Unisonic Technologies Co., Ltd
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UPS604
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
DRAIN
1
8
DRAIN
CS
7
VIN
VCC
2
3
4
6
5
FB
SS
GND
PIN DESCRIPTION
PIN
1
NAME
DRAIN
VIN
FUNCTION
Power MOSFET drain
2
For startup and constant power limit, this pin is pulled to the line input via resistor
3
VCC
Supply voltage
Ground
4
GND
SS
5
Soft-start
6
FB
Feedback
7
CS
Controller current sense input
Power MOSFET drain
8
DRAIN
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UPS604
LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
VCC
3
Frequency
Hopping
1
8
DRAIN
DRAIN
OVP
Oscillator
UVLO
Reference voltage
Logic
Control
Soft Start
SS
5
Latch
Driver
Delay
Time
Q
Q
S
R
Burstmode
OTP
OLP
6
FB
7
CS
LEB
OCP
PWM COMP
Constant
Power Limit
Slope
Compensation
4
2
GND
VIN
Notes: OLP (Over Load Protection)
OVP (Over Voltage Protection)
OTP (Over Temperature Protection)
OCP (Over Current Protection)
UVLO (Under Voltage Latch-Out)
LEB (Led Edge Blanking)
SS (Soft Start)
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UPS604
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS (Ta＝25°C, unless otherwise specified)
PARAMETER
SYMBOL
VCC
RATINGS
30
UNIT
V
Supply Voltage
Input Voltage to Vin Pin
Input Voltage to FB Pin
Input Voltage to CS Pin
Junction Temperature
Operating Temperature
Storage Temperature
Vin
30
V
VFB
-0.3 ~ 6.2
-0.3 ~ 2.8
+150
V
VCS
V
TJ
°C
°C
°C
TOPR
TSTG
-40 ~ +125
-50 ~ +150
Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Note:
OPERATING RANGE
PARAMETER
SYMBOL
VCC
RATINGS
8.6 ~ 22
UNIT
V
Supply Voltage
ELECTRICAL CHARACTERISTICS (Ta＝25°C, VCC=15V, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY SECTION
Start Up Current
ISTR
IOFF
ION
VCC = VCC(ON)-0.1V
VSS = 0, IFB = 0
22
7
45
9
μA
mA
mA
Supply Current with switch
VSS = 4.8V, IFB = 0
7
9
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold Voltage
Min. Operating Voltage
Hysteresis
VTHD(ON)
VCC(MIN)
VCC(HY)
13.5
7.5
14.2
8.2
6
15
9
V
V
V
INTERNAL VOLTAGE REFERENCE
Reference Voltage
VREF
measured at pin VFB
6.3
0.5
6.5
6.7
4.4
V
CONTROL SECTION
VMIN
VMAX
V
V
VFB Operating Level
Burst-Mode Out FB Voltage
VFB(OUT)
VFB(END)
VFB(IN)
VCS =0
1.7
1.6
1.5
68
V
Reduce-Frequency end FB Voltage
Burst-Mode Enter FB Voltage
VCS =0
V
VCS =0
V
Normal
Switch Frequency
VFB = 4V
61
20
75
40
80
kHz
kHz
%
F(SW)
Power-Saving
Before enter burst mode
VFB=4.4V, VCS =0
VFB<0.5V
DMAX
DMIN
FJ(SW)
FDV
68
74
Duty Cycle
0
%
Frequency Hopping
±1.5
±3
±4.5
5
kHz
%
Frequency Variation VS VCC Deviation
Frequency Variation VS Temperature
Deviation
VCC=10 to 20V
T=-40 to 105°C
FDT
5
%
Feedback Resistor
RFB
TSS
VFB=0V
16
21
26
kΩ
Soft-Start Time
CSS=0.47μF
9.9
11.2
12.6
ms
PROTECTION SECTION
VOVP1
VOVP2
VSS<3.5V,VFB>5V
VSS=4.8V, VFB=3V
VCS=0, SS OPEN
CSS=0.47μF
19
28
V
V
OVP threshold
OLP threshold
VFB(OLP)
TD-OLP
4.7
55
4.9
62
5.1
70
V
Delay Time Of OLP
OTP threshold
ms
°C
V
T(THR)
120
3.9
5.1
135
4.1
5.4
150
4.3
5.7
OVP Disable threshold
OLP Enable threshold
VSS(DEACT)
VSS(ACT)
VFB>5V, VCC = 22V
VFB>5V
V
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UPS604
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT LIMITING SECTION
Peak Current Limitation
VCS
VFB=4.4V
0.86
0.77
1
V
V
Threshold Voltage For IVIN =60μA
POWER MOS-TRANSISTOR SECTION
Drain-Source Breakdown Voltage
Turn-on voltage between gate and source
Drain-Source Diode Continuous Source
Current
VSENSE-L
IVIN=60μA
VDSS
VTH
VGS=0V, ID=250μA
VDS=VGS, ID=250μA
600
2
V
V
4
IS
4.4
A
Static Drain-Source On-State Resistance
Rise Time
RDS(ON)
VGS=10V,ID=2.2A
VDD =300V, ID =4.0A
RG=25ꢀ (Note 1,2)
2.5
100
80
ꢀ
tR
tF
45
35
ns
ns
Fall Time
Notes: 1. Pulse Test: Pulse width≤300μs, Duty cycle≤2%
2. Essentially independent of operating temperature
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UPS604
LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
The internal reference voltages and bias circuit work at VCC> VTHD (ON), and shutdown at VCC<VCC (MIN)
.
(1) Soft-Start
When every IC power on, driver output duty cycle will be decided by voltage VSS on soft-start capacitor and VCS
on current sense resistor at beginning. After VSS reach 4.2V, the whole soft-start phase end, and driver duty cycle
depend on VFB and VCS. The relation among VSS, VFB and VOUT as followed FIG.3.
Furthermore, soft-start phase should end before VCC reach VCC (MIN) during VCC power on. Otherwise, if soft-start
phase remain not end before VCC reach VCC (MIN) during VCC power on, IC will enter auto-restart phase and not set up
VOUT. So the value of CSS should be between 0.1μFand 4.7μF.
Finally soft-start also set OVP1 active phase. OVP1 active phase between 0 and VSS(DEACT), OVP1 will not be
sensed after VSS reach VSS(DEACT).The Soft-start phase TSS：TSS = 23.8×CSS (ms) (Example: CSS=0.47μF, then
TSS=23.8×0.47=11.2ms).
VSS
4.2V
TSOFT-START
t
VFB
4.8V
t
VOUT
TSTRAT-UP
t
Driver
t
Fig.3 Soft-start phase
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UPS604
LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
(2) Switch Frequency Set
The maximum switch frequency is set to 68kHz. Switch frequency is modulated by output power POUT during IC
operating. At no load or light load condition, most of the power dissipation in a switching mode power supply is from
switching loss on the MOSFET transistor, the core loss of the transformer and the loss on the subber circuit. The
magnitude of power loss is in proportion to the number of switching events within a fixed period of time. So lower
switch frequency at lower load, which more and more improve IC’s efficiency at light load. At from no load to light
load condition, The IC will operate at from Burst mode to Reducing Frequency Mode. The relation curve between fSW
and POUT/POUT (MAX) as followed FIG.4.
FIG.4 The relation curve between fSW and relative output power POUT/ POUT (MAX)
(3) Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM
generation, this greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus
reduces the output ripple voltage.
(4) Frequency Hopping For EMI Improvement
The Frequency hopping is implemented in the IC; there are two oscillators built-in the IC. The first oscillator
is to set the normal switching frequency; the switching frequency is modulated with a period signal generated by the
2nd oscillator. The relation between the first oscillator and the 2nd oscillator as followed FIG.5. So the tone energy is
evenly spread out, the spread spectrum minimizes the conduction band EMI and therefore eases the system design
in meeting stringent EMI requirement.
Fosc
(kHz)
FSW_MAX
FSW_TYP
FSW_MIN
THopping
t(ms)
FIG.5 Frequency Hopping
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UPS604
LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
(5) Constant Output Power Limit
When the SENSE voltage, across the sense resistor RS, reaches the threshold voltage, around 0.8V, the output
GATE drive will be turned off after a small propagation delay tD. This propagation delay will introduce an additional
current proportional to tD×VIN/Lp. Since the propagation delay is nearly constant regardless of the input line voltage
VIN. Higher input line voltage will result in a larger additional current and hence the output power limit is also higher
than that under low input line voltage. To compensate this variation for wide AC input range, the threshold voltage is
adjusted by the VIN current. Since VIN pin is connected to the rectified input line voltage through a resistor RVIN, a
higher line voltage will generate higher VIN current into the VIN pin. The threshold voltage is decreased if the VIN
current is increased. Smaller threshold voltage, forces the output GATE drive to terminate earlier, thus reduce the
total PWM turn-on time and make the output power equal to that of low line input. This proprietary internal
compensation ensures a constant output power limit for wide AC input voltage from 90VAC to 264VAC.
(6) Protection section
The IC takes on more protection functions such as OLP, OVP and OTP etc. In case of those failure modes for
continual blanking time, the driver is shut down. At the same time, IC enters auto-restart, VCC power on and driver is
reset after VCC power on again.
OLP
After soft-start phase end, IC will shutdown driver if over load state occurs for continual TD-OLP. OLP function will
not inactive during soft-start phase. OLP case as followed FIG. 6. The test circuit as followed FIG.8. TD-OLP=5.53×TSS.
OVP
There are two kinds of OVP circuits, the first OVP function are enabled only when VSS<VSS (DEACT) & VFB>VFB
(OLP) during soft-start phase. During above condition, driver will be shutdown if over voltage state occurs (VCC>VOVP1
)
for continual a blanking time. The first OVP function will not inactive after soft-start phase. The second OVP will
shutdown the switching of the power MOSFET whenever VCC>VOVP2. The first OVP case as followed FIG.7. The test
circuit as followed FIG.9.
FIG.6 OLP case
FIG.7 OVP case
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UPS604
LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
FIG.8 OLP test circuit
FIG.9 OVP test circuit
OTP
OTP will shut down driver when junction temperature TJ>T (THR) for continual a blanking time.
(7) Driver Output Section
The driver-stage drives the gate of the MOSFET and is optimized to minimize EMI and to provide high circuit
efficiency. This is done by reducing the switch on slope when reaching the MOSFET threshold. This is achieved by a
slope control of the rising edge at the driver’s output. The output driver is clamped by an internal 15V Zener diode in
order to protect power MOSFET transistors against undesirable gate over voltage.
(8) Inside power switch MOS transistor
Specific power MOS transistor parameter is as “POWER MOS TRANSISTOR SECTION” in electrical
characteristics table.
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UPS604
LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION CIRCUIT
FIG.10 UPS604 Typical Application Circuit
Table1. Components reference description for UPS604 application circuit
DESIGNATOR PART TYPE DESIGNATOR PART TYPE DESIGNATOR PART TYPE
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
33μF
0.001μF
22μF
R1
R2
2.2Mꢀ
2.2Mꢀ
68Kꢀ
D1
D2
FR107
SB5100
RS1D
R3
D3
470μF
470μF
0.1μF
R4
100ꢀ
IC1
IC2
IC3
YC1
T1
UPS604
PC-817
TL431
R5
1Mꢀ
R6
15ꢀ
0.01μF
0.001μF
0.1μF
R7
560ꢀ
222
R8
1Kꢀ
EE25
R9
3.9Kꢀ
15Kꢀ
L1
UU10.5
2μH
220μF
R10
R11
R12
R13
R14
L2
10Kꢀ
L3
Ring Choke
LED
1.5Mꢀ~4Mꢀ
1.0ꢀ
LD1
F1
2A/250V
7D471K
SCK102R55A
334/275V
KBP205
1.8Kꢀ
ZNR1
TR1
XC1
BD1
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UPS604
LINEAR INTEGRATED CIRCUIT
TYPICAL CHARACTERISTICS
Feedback Voltage During Loadjump From
10% Up To 100% Load (VAC=90V)
Feedback Voltage During Loadjump From
10% Up To 100% Load (VAC=264V)
12V
10V
8V
6V
4V
2V
0
12V
10V
8V
6V
4V
2V
0
-2V
-2V
0
2000
Time (400μs/div)
4000
4000
0
0
0
2000
Time (400μs/div)
Startup With Full Load Condition at
VAC=264V, VSS and VOUT
Startup With Full Load Condition at
VAC=90V, VSS and VOUT
8V
6V
4V
8V
6V
4V
2V
0
2V
0
VSS
VSS
10V
5V
0
10V
5V
0
VOUT
VOUT
50
0
50
100
100
Time (10ms/div)
Time (10ms/div)
Startup Behavior At Nominal Load
Condition VAC=264V
Startup Behavior At Nominal Load
Condition VAC=90V
8V
6V
4V
8V
6V
4V
2V
0
2V
0
VSS
VSS
4V
2V
4V
2V
0
VFB
VFB
0
40
40
0
20
20
Time (4ms/div)
Time (4ms/div)
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UPS604
LINEAR INTEGRATED CIRCUIT
TYPICAL CHARACTERISTICS(Cont.)
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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