UTC4053 [UTC]
ANALOG MULTIPLEXERS/ DEMULTIPLEXERS; 模拟多路复用器/多路解复用器
| 型号： | UTC4053 |
| 厂家： | 
Unisonic Technologies |
| 描述： | ANALOG MULTIPLEXERS/ DEMULTIPLEXERS |
| 文件： | 总6页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTC 4053
CMOS IC
ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
DESCRIPTION
The UTC 4053 are Triple SPDT analog multiplexers for
application as digitally–controlled analog switches.
SOP-16
DIP-16
FEATURES
* Analog Voltage Range (VDD – VEE) = 3.0 ~ 18 V
Note: VEE must be≦VSS
* Linearized Transfer Characteristics
* Pin–to–Pin Replacement for CD4053
TSSOP-16
*Pb-free plating product number: 4053L
PIN CONFIGURATIONS
Y1
1
VDD
16
15
14
13
12
Y0
2
3
4
5
6
7
8
Y
X
Z1
Z
X1
UTC 4053
Z0
INH
VEE
VSS
X0
A
11
10
9
B
C
UTC UNISONIC TECHNOLOGIES CO., LTD.
1
www.unisonic.com.tw
QW-R502-036,A
UTC 4053
CMOS IC
UTC 4053 Triple 2–Channel Analog Multiplexer/Demultiplexer
6
11
10
9
INHIBIT
14
15
X
A
CONTROLS
B
C
COMMONS
OUT/IN
X0
X1
Y0
Y1
Z0
Z1
Y
Z
12
13
2
SWITCHES
IN/OUT
1
4
5
3
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be≦VSS
.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
DC Supply Voltage (Referenced to VEE, VSS≧VEE
SYMBOL
VDD
RATINGS
-0.5 ~ +18.0
UNIT
V
)
Input or Output Voltage (DC or Transient) (Referenced to VSS
for Control Inputs and VEE for Switch I/O)
Input Current (DC or Transient), per Control Pin
Switch Through Current
Power Dissipation. Per Package**
Storage Temperature
Vin, Vout
-0.5 ~ VDD +0.5
V
Iin
ISW
PD
Tstg
TLead
±10
±25
500
mA
mA
mW
℃
-65 ~ +150
260
℃
Lead Temperature (8 - Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
** Temperature Derating: “DIP and SOP” Packages: – 7.0 mW/℃ From 65℃ ~ 125℃
ELECTRICAL CHARACTERISTICS
(Ta=25℃, unless otherwise indicated.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
3.0
TYP#
MAX UNIT
SUPPLY REQUIREMENTS (Voltages Referenced to VEE
)
VDD – 3.0≧VSS≧VEE
Power Supply Voltage Range
Quiescent Current per Package
VDD
18
V
Control Inputs: Vin = VSS or VDD
Switch I/O: VEE ≦VI/O ≦VDD
,
and ∆Vswitch≦500mV*
IDD
µA
V
DD=5.0V
0.005
0.010
0.015
5.0
10
20
VDD=10V
VDD=15V
Ta=25℃ only (The channel
component, (Vin - Vout)/Ron, is
Total Supply Current (Dynamic Plus
Quiescent, Per Package)
not included.)
ID(AV)
µA
VDD=5.0V
(0.07 µA/kHz) f + IDD Typical
(0.20 µA/kHz) f + IDD
(0.36 µA/kHz) f + IDD
VDD=10V
VDD=15V
UTC UNISONIC TECHNOLOGIES CO., LTD.
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QW-R502-036,A
UTC 4053
CMOS IC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP#
MAX UNIT
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to VSS
)
Ron= per spec, Ioff = per spec
VDD=5.0V
2.25
4.50
6.75
1.5
V
Low – Level Input Voltage
VIL
VIH
VDD=10V
3.0
VDD=15V
4.0
Ron= per spec, Ioff = per spec
VDD=5.0V
3.5
7.0
11
2.75
5.50
8.25
High – Level Input Voltage
V
VDD=10V
VDD=15V
Input Leakage Current
Input Capacitance
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE
Recommended Peak–to–Peak Voltage
Into or Out of the Switch
Recommended Static or Dynamic
Voltage Across the Switch** (Figure 3)
Output Offset Voltage
Iin
Cin
Vin= 0 or VDD, VDD=15V
±0.00001 ±0.1
µA
pF
5.0
7.5
)
Channel On or Off
VI/O
0
0
VDD
600
VPP
Channel On
∆Vswitch
mV
µV
VOO
Vin = 0V, No Load
∆Vswitch≦500mV*
10
Vin = VIL or VIH (Control), and
Vin = 0 to VDD (Switch)
VDD=5.0V
ON Resistance
Ron
Ω
250
120
80
1050
500
280
70
VDD=10V
VDD=15V
V
DD=5.0V
25
ΔON Resistance Between Any Two
Channels in the Same Package
∆Ron
VDD=10V
10
50
Ω
VDD=15V
10
45
Vin = VIL or VIH (Control)
Channel to Channel or Any
One Channel, VDD=15V
Inhibit = VDD
Inhibit = VDD
Pins Not Adjacent
Pins Adjacent
Off–Channel Leakage Current
(Figure 8)
Ioff
±0.05
±100
nA
Capacitance, Switch I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
CI/O
CO/I
10
17
0.15
0.47
pF
pF
CI/O
pF
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential
performance.
* For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may
be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the
device will be unaffected unless the Maximum Ratings are exceeded. (See second page of this data sheet.)
UTC UNISONIC TECHNOLOGIES CO., LTD.
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QW-R502-036,A
UTC 4053
CMOS IC
ELECTRICAL CHARACTERISTICS*
(CL = 50pF, Ta=25℃, VEE≦VSS, unless otherwise indicated.)
PARAMETER
SYMBOL VDD – VEE Vdc
5.0
TEST CONDITIONS
MIN TYP# MAX UNIT
Propagation Delay Times
(Figure 4) Switch Input to
Switch Output (RL = 10 kΩ)
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns
(RL=10kΩ, VEE=VSS)Output “1” or “0”
to High Impedance, or High
25
65
tPLH, tPHL
10
15
5.0
10
15
5.0
10
15
10
8.0
20
ns
ns
ns
6.0
15
275
140
110
300
120
80
550
280
220
600
240
160
tPHZ, tPLZ
tPZH, tPZL
Inhibit to Output
Impedance to “1” or “0” Level
Control Input to Output
tPLH, tPHL
RL = 10 kΩ, VEE = VSS
Second Harmonic Distortion
Bandwidth (Figure 5)
RL = 10KΩ, f = 1 kHz, Vin = 5 VPP
RL = 1kΩ, Vin = 1/2 (VDD–VEE) p–p,
CL = 50pF, 20 Log (Vout/Vin) = -3dB)
RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p
fin = 55 MHz
RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p
fin = 3.0 MHz
0.07
%
BW
10
10
10
10
17
-50
-50
75
MHz
Off Channel Feedthrough
Attenuation (Figure 5)
Channel Separation
(Figure 6)
Crosstalk, Control Input to
Common O/I (Figure 7)
dB
dB
R1 = 1 kΩ, RL = 10 kΩ Control
tTLH = tTHL = 20 ns, Inhibit = VSS
mV
)
* The formulas given are for the typical characteristics only at 25℃.
# Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential
performance.
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
OUT/IN
IN/OUT
CONTROL
VEE
Figure 1. Switch Circuit Schematic
UTC UNISONIC TECHNOLOGIES CO., LTD.
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QW-R502-036,A
UTC 4053
CMOS IC
16
VDD
VEE
TRUTH TABLE
Control Inputs
INH
6
ON Switches
BINARY TO 1 - OF - 2
A 11
B 10
Select
B
LEVEL
DECODER WITH
INHIBIT
Inhibit
CONVERTER
C
0
0
0
0
1
1
1
1
x
A
0
1
0
1
0
1
0
1
x
UTC 4053
Z0 Y0 X0
Z0 Y0 X1
Z0 Y1 X0
Z0 Y1 X1
Z1 Y0 X0
Z1 Y0 X1
Z1 Y1 X0
Z1 Y1 X1
None
C
9
0
0
0
0
0
0
0
0
1
0
7
8
VSS
0
1
1
0
0
1
1
x
X0 12
X1 13
14 X
15 Y
Y0
2
Y1
Z0
1
5
4
Z
Z1
3
Figure 2. UTC 4053 Functional Diagram
x = Don’t Care
350
350
300
250
V
= 7.5 V
V
= 5.0 V
VDEED = - 7.5 V
VDEED = -5.0 V
300
250
T
a
=25℃
Ta =25℃
200
150
100
200
150
100
50
0
50
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
INPUT VOLTAGE, Vin (VOLTS)
INPUT VOLTAGE, Vin (VOLTS)
350
300
250
200
150
100
50
V
DD = 2.5 V
EE = - 2.5 V
=25℃
V
T
a
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
INPUT VOLTAGE, Vin (VOLTS)
UTC UNISONIC TECHNOLOGIES CO., LTD.
5
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QW-R502-036,A
UTC 4053
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
UTC UNISONIC TECHNOLOGIES CO., LTD.
6
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QW-R502-036,A
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