UTC571-D16-T [UTC]

Analog Circuit;


型号：	UTC571-D16-T
厂家：	Unisonic Technologies
描述：	Analog Circuit
文件：	总14页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UNISONIC TECHNOLOGIES CO., LTD

UTC571

LINEAR INTEGRATED CIRCUIT

COMPANDER

DESCRIPTION

The UTC571 is a versatile low cost dual gain control circuit in

which either channel may be used as a dynamic range compressor

or expandor. Each channel has a full-wave rectifier to detect the

average value of the signal, a linerarized

temperature-compensated variable gain cell,and an operational

amplifier.

DIP-16

The UTC571 is well suited for use in cellular radio and radio

communication systems, modems, telephone, and satellite

broadcast/receive audio systems.

FEATURES

* Complete compressor and expandor in one Chip

* Temperature compensated

Lead-free:

UTC571L

* Greater than 110dB dynamic range

* Operates down to 6VDC

Halogen-free: UTC571G

* System levels adjustable with external components

* Distortion may be trimmed out

* Dynamic noise reduction systems

* Voltage-controlled amplifier

ORDERING INFORMATION

Ordering Number

Package

DIP-16

Packing

Tube

Normal

Lead Free

Halogen Free

UTC571-D16-T

UTC571L-D16-T

UTC571G-D16-T

UTC571L-D16-T

(1)Packing Type

(2)Package Type

(3)Lead Plating

(1) T: Tube

(2) D16: DIP-16

(3) G: Halogen Free, L: Lead Free, Blank: Pb/Sn

www.unisonic.com.tw

1 of 14

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

PIN CONNECTIONS

RECT CAP 2

RECT CAP 1

RECT IN 1

RECT IN 2

AGCELL IN 2

VCC

AGCELL IN 1

GND

INV.IN 1

INV.IN 2

RES.R₃1

RES.R3 2

OUTPUT 1

OUTPUT 2

THD TRIM 2

THD TRIM 1

UNISONIC TECHNOLOGIES CO., LTD

2 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

BLOCK DIAGRAM

UNISONIC TECHNOLOGIES CO., LTD

3 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS(T_A=25℃)

PARAMETER

SYMBOL

V_CC

RATINGS

UNITS

Maximum Operating Voltage

Operating Temperature

Power Dissipation

T_A

0 ~ 70

400

°C

P_D

Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.

Absolute maximum ratings are stress ratings only and functional device operation is not implied.

AC ELECTRICAL CHARACTERISTICS(T_A=25 C, V_CC=+6V, unless otherwise stated)

PARAMETER

SYMBOL

V_CC

CONDITIONS

MIN

TYP MAX UNITS

Supply Voltage

Supply Current

I_CC

No signal

3.2

4.8

V/μs

Output Current capability

Output SlewRate

I_OUT

0.5

0.1

Untrimmed

Trimmed

Gsin Cell Distortion

2.0

％

Resister Tolerance

Internal Reference Voltage

Output DC Shift

2.0

150

1.7

1.85

Untrimmed

Expandor Output Noise

Unity Gain Level

No signal, 15Hz-20kHz

1kHz

-1.5

+1.5 dBm

Gain Change

0.1

+2,-25

+8,-0

Reference Drift

+20,-50

-1,+1.5

％

Resistor Drift

Tracking Error(measured relative

to value at unity gain) Equals

[VO-VO (unity gain)]dB-V2dBm

Rectifier input,

V2=+6dBm,V1=0dB

V2=-30dBm, V1=0dB

+0.2

Channel Separation

Note: 1. Input to V 1 and V 2 grounded.

2. Measured at 0dBm, 1kHz.

3. Expandor AC input change from no signal to 0dBm.

4. Relative to value at T_A= 2℃.

5. Electrical characteristics for the UTC571 only are specified over -40 to +8 C temperature range.

6. 0dBm = 775mV RMS.

UNISONIC TECHNOLOGIES CO., LTD

4 of 14

QW-R121-017.A

www.unisonic.com.tw

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION

Circuit Description

The UTC571 compandor building blocks, as shown in the block diagram, are a full-wave rectifier, a variable gain

cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a circuit which

can perform well with fewexternal components, yet can be adapted to many diverse applications.

The full-wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing node

which is biased at V_REF.The rectified current is averaged on an external filter capacitor tied to the C_RECTterminal, and

the average value of the input current controls the gain of the variable gain cell. The gain will thus be proportional to

the average value of the input signal for capacitively-coupled voltage inputs as shown in the following equation. Note

that for capacitively-coupled inputs there is no offset voltage capable of producing a gain error. The only error will

come from the bias current of the rectifier (supplied internally) which is less than 0.1mA.

IN −V^REFavg

^INavg

or G=

The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter

capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on the

gain control signal will modulate the signal passing through the variable gain cell. In an expander or compressor

application, this would lead to third harmonic distortion, so there is a trade-off to be made between fast attack and

decay times and distortion. For step changes in amplitude, the change in gain with time is shown by this equation.

G(t)=(Ginitial-Gfinal)e-t/t +Gfinal; t =10k · C_RECT

The variable gain cell is a current-in, current-out device with the ratio I_OUT/I_INcontrolled by the rectifier. IIN is the

current which flows from the DG input to an internal summing node biased at V_REF. The following equation applies for

capacitively-coupled inputs. The output current, I_OUT, is fed to the summing node of the op amp.

−VREF

^INR

I_IN=

A compensation scheme built into the DG cell compensates for temperature and cancels out odd harmonic

distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset

voltages. The THD trim terminal provides a means for nulling the internal offsets for lowdistortion operation.

The operational amplifier (which is internally compensated) has the non-inverting input tied to V_REF, and the

inverting input connected to the DG cell output as well as brought out externally. A resistor, R 3 , is brought out from

the summing node and allows compressor or expander gain to be determined only by internal components.

The output stage is capable of ±20mA output current. This allows a +13dBm (3.5V RMS ) output into a 300W

load which, with a series resistor and proper transformer, can result in +13dBm with a 600W output impedance.

A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the

rectifier and DG cell, and a bias current for the DG cell. The low tempco of this type of reference provides very stable

biasing over a wide temperature range.

The typical performance characteristics illustration shows the basic input-output transfer curve for basic

compressor or expander circuits.

UNISONIC TECHNOLOGIES CO., LTD

5 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

INTRODUCTION

Much interest has been expressed in high performance electronic gain control circuits. For non-critical

applications, an integrated circuit operational transconductance amplifier can be used, but when high-performance is

required, one has to resort to complex discrete circuitry with many expensive, well-matched components.

This paper describes an inexpensive integrated circuit, the UTC571 Compandor, which offers a pair of hig

performance gain control circuits featuring low distortion (<0.1%), high signal-to-noise ratio (90dB), and wide

dynamic range (110dB).

CIRCUIT BACKGROUND

The UTC571 Compandor was originally designed to satisfy the requirements of the telephone system. When

several telephone channels are multiplexed onto a common line, the resulting signal-to-noise ratio is poor and

companding is used to allow a wider dynamic range to be passed through the channel. Figure 1 graphically shows

what a compandor can do for the signal-to-noise ratio of a restricted dynamic range channel. The input level range of

+20 to -80dB is shown undergoing a 2-to-1 compression where a 2dB input level change is compressed into a 1dB

output level change by the compressor. The original 100dB of dynamic range is thus compressed to a 50dB range

for transmission through a restricted dynamic range channel. A complementary expansion on the receiving end

restores the original signal levels and reduces the channel noise by as much as 45dB.

The significant circuits in a compressor or expander are the rectifier and the gain control element. The phone

system requires a simple full-wave averaging rectifier with good accuracy, since the rectifier accuracy determines the

(input) output level tracking accuracy. The gain cell determines the distortion and noise characteristics, and the

phone system specifications here are very loose. These specs could have been met with a simple operational

transconductance multiplier, or OTA, but the gain of an OTA is proportional to temperature and this is very

undesirable. Therefore, a linearized Tran conductance multiplier was designed which is insensitive to temperature

and offers low noise and low distortion performance. These features make the circuit useful in audio and data

systems as well as in telecommunications systems.

UNISONIC TECHNOLOGIES CO., LTD

6 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

BASIC CIRCUIT HOOK-UP AND OPERATION

INV_IN

THD TRIM

8.9

6.11 5.12

20k

G_IN

ΔG

VREE

1.8V

OUTPUT

3.14

7.10

30k

_CCPIN 13

10k

RECT_IN

GND PIN 14

2.15

1.16

C_RECT

Figure 2.Chip Block Diagram

Figure 2 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-

wave averaging rectifier provides a gain control current, IG , for the variable gain (D G) cell. The output of the DG

cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish

circuit gain and set the output DC bias.

The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8V

reference denoted V_REF. The non-inverting input of the op amp is tied to V_REF,and the summing nodes of the rectifier

and D G cell (located at the right of R1 and R2) have the same potential. The THD trim pin is also the V_REFpotential.

C_IN1

ΔG

V_OUT

V_IN

V_REF

C_IN2

2R₃V_IN(avg)

R₁R₂I_B

I_B=140μA

Note:Gain=

C_RECT

Figure 3.Basic Expander

Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, V_INis applied to the inputs

of both the rectifier and the D G cell. When the input signal drops by 6dB, the gain control current will drop by a

factor of 2, and so the gain will drop 6dB. The output level at V_OUTwill thus drop 12dB, giving us the desired 2 to 1

expansion.

UNISONIC TECHNOLOGIES CO., LTD

7 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

Figure 4 shows the hook-up for a compressor. This is essentially an expandor placed in the feedback loop of the

op amp . the D G cell is setup to provide AC feedback only, so a separate DC feedback loop is provide by the two

RDC and CDC. The values of RDC will determine the DC bias at the output of the amp. The output will bias to:

^DC¹+ RDC2

V_OUTDC=1+

DCTOT

V_REF=(1+

)1.8V

20K

The output of the expander will bias up to:

V_OUT

V_REF

^DC=1+R

20K

V_REF

)1.8V=3.0V

⁼⁽¹⁺30K

The output will bias to 3.0V when the internal resistor are used. External resistor may be placed in series with

r3,(which will affect the gain ), or in parallel with R₄to raise the DC bias to any desired value.

CIRCUIT DETAILS—RECTIFIER

V+

I=V_IN/R1

V_IN

I_G

10k

C_R

Figure 5.Rectifier Concept

Figure 5 shows the concept behind the full-wave averaging rectifier. The input current to the summing node of

theopamp,V IN R 1 , is supplied by the output of the op amp. If we can mirror the op amp output current into a

unipolar current, we will have an ideal rectifier. The output current is averaged by R5 , CR, which set the averaging

time constant, and then mirrored with a gain of 2 to become IG , the gain control current.

UNISONIC TECHNOLOGIES CO., LTD

8 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

10K

V_IN

10K

I₁

I₂

C_R

Figure 6.Simplified Rectifier Schematic

Figure 6 shows the rectifier circuit in more detail. The op amp is a one-stage op amp, biased so that only one

output device is on at a time. The non-inverting input, (the base of Q1 ), which is shown grounded, is actually tied to

the internal 1.8V VREF . The inverting input is tied to the op amp output, (the emitters of Q5 and Q6 ), and the input

summing resistor R 1 . The single diode between the bases of Q5 and Q6 assures that only one device is on at a

time. To detect the output current of the op amp, we simply use the collector currents of the output devices Q5 and

Q6 . Q6 will conduct when the input swings positive and Q 5 conducts when the input swings negative. The collector

currents will be in error by the a of Q 5 or Q 6 on negative or positive signal swings, respectively. ICs such as this

have typical NPN bs of 200 and PNP bs of 40. The a’s of 0.995 and 0.975 will produce errors of 0.5% on negative

swings and 2.5% on positive swings. The 1.5% average of these errors yields a mere 0.13dB gain error.

At very low input signal levels the bias current of Q2 , (typically 50nA), will become significant as it must be

supplied by Q5 . Another low level error can be caused by DC coupling into the rectifier. If an offset voltage exists

between the V IN input pin and the base of Q2 , an error current of V_OS/R 1 will be generated. A mere 1mV of offset

will cause an input current of 100nA which will produce twice the error of the input bias current. For highest accuracy,

the rectifier should be coupled into capacitively. At high input levels the b of the PNP Q6 will begin to suffer, and

there will be an increasing error until the circuit saturates. Saturation can be avoided by limiting the current into the

rectifier input to 250mA. If necessary, an external resistor may be placed in series with R1 to limit the current to this

value. Figure 7 shows the rectifier accuracy vs input level at a frequency of 1kHz.

UNISONIC TECHNOLOGIES CO., LTD

9 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

At very high frequencies, the response of the rectifier will fall off. The roll-off will be more pronounced at lower

input levels due to the increasing amount of gain required to switch between Q 5 or Q 6 conducting. The rectifier

frequency response for input levels of 0dBm, -20dBm, and -40dBm is shown in Figure 8. The response at all three

levels is flat to well above the audio range.

VARIABLE GAIN CELL

Figure 9 is a diagram of the variable gain cell. This is a linearized two-quadrant transconductance multiplier.

Q1 ,Q2 and the op amp provide a predistorted drive signal for the gain control pair, Q3 and Q4 . The gain is

controlled by I G and a current mirror provides the output current.

The op amp maintains the base and collector of Q1 at ground potential (V_REF) by controlling the base of Q2 .

The input current I_IN(=V_IN/R 2 ) is thus forced to flow through Q1 along with the current I₁, so I_C1=I₁+I_IN. Since I2

has been set at twice the value of I₁, the current through Q2 is:

I₂-(I₁+I_IN)=I₁-I_IN=I_C2.

The op amp has thus forced a linear current swing between Q1 and Q2 by providing the proper drive to the base

of Q2 . This drive signal will be linear for small signals, but very non-linear for large signals, since it is compensating

for the non-linearity of the differential pair, Q1 and Q2 , under large signal conditions.

The key to the circuit is that same predistorted drive signal is applied to the gain control pair, Q3 and Q4. When

two differential pairs of transistors have the same signal applied, their collector current ratios will be identical

regardless of the magnitude of the currents. This gives us :

+ I^IN

− IIN

C2 ⁼IC3 ⁼I

UNISONIC TECHNOLOGIES CO., LTD

10 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

plus the relationships I_G= I_C3+ I_C4and I_OUT= I_C4- I_C3will yield the multiplier transfer function,

IN G

I_OUT=

I_IN=

2I1

This equation is liner and temperature-insenstive, but it assumes ideal transistor.

VOS=3mV

4mV

3mV

2mV

1mV

0.34

-6

INPUT LEVEL (dBm)

Figure 10.G Cell Distortion vs Offset Voltage

If the transistors are not perfectly matched, a parabolic, non-linearity is generated, which results in second

harmonic distortion. Figure 10 gives an indication of the magnitude of the distortion caused by a given input level and

offset voltage. The distortion is linearly proportional to the magnitude of the offset and the input level. Saturation of

the gain cell occurs at a +8dBm level. At a nominal operating level of 0dBm, a 1mV offset will yield 0.34% of second

harmonic distortion. Most circuits are somewhat better than this, which means our overall offsets are typically about

mV. The distortion is not affected by the magnitude of the gain control current, and it does not increase as the gain is

changed. This second harmonic distortion could be eliminated by making perfect transistors, but since that would be

difficult, we have had to resort to other methods. A trim pin has been provided to allow trimming of the internal

offsets to zero, which effectively eliminated second harmonic distortion. Figure 11 shows the simple trim network

required.

UNISONIC TECHNOLOGIES CO., LTD

11 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

Figure 12 shows the noise performance of the DG cell. The maximum output level before clipping occurs in the

gain cell is plotted along with the output noise in a 20kHz bandwidth. Note that the noise drops as the gain is

reduced for the first 20dB of gain reduction. At high gains, the signal to noise ratio is 90dB, and the total dynamic

range from maximum signal to minimum noise is 110dB.

Control signal feedthrough is generated in the gain cell by imperfect device matching and mismatches in the

current sources, I 1 and I 2 . When no input signal is present, changing I G will cause a small output signal. The

distortion trim is effective in nulling out any control signal feedthrough, but in general, the null for minimum

feedthrough will be different than the null in distortion. The control signal feedthrough can be trimmed independently

of distortion by tying a current source to the DG input pin. This effectively trims I . Figure 17 shows such a trim

network.

V_CC

R-Select for

3.6V

470k

100k

to PIN 3 or 14

Figure 13.control Signal Feedthrough

OPERATIONAL AMPLIFIER

The main op amp shown in the chip block diagram is equivalent to a 741 with a 1MHz bandwidth. Figure 18

shows the basic circuit. Split collectors are used in the input pair to reduce g M , so that a small compensation

capacitor of just 10pF may be used. The output stage, although capable of output currents in excess of 20mA, is

biased for a low quiescent current to conserve power. When driving heavy loads, this leads to a small amount of

crossover distortion.

UNISONIC TECHNOLOGIES CO., LTD

12 of 14

QW-R121-017.A

www.unisonic.com.tw

UTC571

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION(Cont.)

RESISTORS

Inspection of the gain equations in Figures 3 and 4 will show that the basic compressor and expander circuit

gains may be set entirely by resistor ratios and the internal voltage reference. Thus, any form of resistors that match

well would suffice for these simple hook-ups, and absolute accuracy and temperature coefficient would be of no

importance. However, as one starts to modify the gain equation with external resistors, the internal resistor accuracy

and tempco become very significant. Figure 15 shows the effects of temperature on the diffused resistors which are

normally used in integrated circuits, and the ion-implanted resistors which are used in this circuit. Over the critical 0

Cto+70 C temperature range, there is a 10-to-1 improvement in drift from a 5% change for the diffused resistors, to a

0.5% change for the implemented resistors. The implanted resistors have another advantage in that they can be

made the size of the diffused resistors due to the higher resistivity. This saves a significant amount of chip area.

1.15

140Ω/

Diffused

Resistor

1.10

1kΩ/

Low TC Implanted

1.05

Resistor

1.00

0.95

1％Error Band

Temperature

Figure 15.Resistance vs Temperature

-40

120

UNISONIC TECHNOLOGIES CO., LTD

13 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571

LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATION CIRCUIT

UTC assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or

other parameters) listed in products specifications of any and all UTC products described or contained

herein. UTC products are not designed for use in life support appliances, devices or systems where

malfunction of these products can be reasonably expected to result in personal injury. Reproduction in

whole or in part is prohibited without the prior written consent of the copyright owner. The information

presented in this document does not form part of any quotation or contract, is believed to be accurate

and reliable and may be changed without notice.

UNISONIC TECHNOLOGIES CO., LTD

14 of 14

www.unisonic.com.tw

QW-R121-017.A

UTC571-D16-T [UTC]

相关型号：

UTC571G-D16-T

UTC571L-D16-T

UTC571N

UTC571NG-S16-R

UTC571NG-S16-T

UTC571NG-S16W-R

UTC571NG-S16W-T

UTC571NL-S16-R

UTC571NL-S16-T

UTC571NL-S16W-R

UTC571NL-S16W-T

UTC571N_15