MGLS12864T-LED04-LV2 [VARITRONIX]
SPECIFICATION OF LCD MODULE TYPE; 规格液晶显示模组式
| 型号： | MGLS12864T-LED04-LV2 |
| 厂家： | 
VARITRONIX INTERNATIONAL LIMITED |
| 描述： | SPECIFICATION OF LCD MODULE TYPE |
| 文件： | 总11页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 2 OF 11
DOCUMENT REVISION HISTORY 1:
DOCUMENT
REVISION
FROM TO
A
DATE
DESCRIPTION
CHANGED CHECKED
BY
BY
2002.01.11 First Release
(Based on the test specification
PHILIP
TOM LEE
CHENG
VL-TS-MGLS12864T-20, REV. A,
2001.03.01)
A
B
2004.04.03 Items 1-3 were updated:
CHEN HUI
JUAN
HE ZUO
BING
(Based on Test Specification:
VL-TS-MGLS12864T-XX REV. Q
2003.12.23)
1.) (Page4, Table1)“Outline
dimensions” were updated.
2.) (Page5, Figure 1) Outline
Drawing was changed from
Rev. 0 to Rev. 2.
3.) (Page9, Point5.1) Table 5 was
updated.
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 3 OF 11
CONTENTS
Page No.
1.
2.
3.
GENERAL DESCRIPTION
4
4
7
8
MECHANICAL SPECIFICATIONS
INTERFACE SIGNALS
4.
4.1
4.2
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL MAXIMUM RATINGS (Ta=25°C)
ENVIRONMENTAL CONDITION
8
8
5.
ELECTRICAL SPECIFICATIONS
TYPICAL ELECTRICAL CHARACTERISTICS
TIMING SPECIFICATIONS
9
9
10
11
5.1
5.2
5.3
TIMING DIAGRAM OF VDD AGAINST V0
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 4 OF 11
VARITRONIX LIMITED
Specification
of
LCD Module Type
Item No.: MGLS12864T-20
1. General Description
·
·
·
·
·
·
·
·
128 x 64 dot matrix STN LV2 Positive Yellow Transflective dot matrix LCD graphic module.
Viewing direction: 6 o’ clock.
Driving scheme: 1/64 multiplexed drive, 1/9 bias.
‘ Toshiba’ T6963C flat pack or equivalent dot matrix LCD controller.
‘ Toshiba’ T6A39 flat pack or equivalent dot matrix liquid crystal graphic display column drivers.
‘ Toshiba’ T6A40 flat pack or equivalent dot matrix liquid crystal graphic display row driver.
8K byte display SRAM.
Yellow-green LED04 backlight.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter
Outline dimensions
Display format
Viewing area
Active area
Dot size
Specifications
78.0(W) x 70.0(H) x 15.5 MAX.(D)
128(Horizontal) x 64(Vertical)
62.0(W) x 44.0(H)
56.27(W) x 38.35(H)
0.39(W) x 0.55(H)
Unit
mm
dots
mm
mm
mm
Dot spacing
Dot pitch
0.05(W) x 0.05(H)
0.44(W) x 0.60(H)
mm
mm
Weight:
TBD
grams
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 5 OF 11
Figure 1: Outline Drawing 1
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 6 OF 11
Figure 2: Outline Drawing 2
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 7 OF 11
3. Interface signals
Table 2
Pin No. Symbol
Description
1
2
3
4
5
6
7
FG
VSS
VDD
V0
/WR
/RD
/CE
Frame ground (see note 1).
Ground (0V).
Power supply for logic (+5V).
Power supply for LCD drive
Data Write. Write data into T6963C when /WR=“Low”.
Data Read. Read data from T6963C when /RD=“Low”.
Chip enable for T6963C.
/CE must be “Low” when CPU communicates with T6963C.
8
9
C / D
/RST
/WR = “Low” …..C/D=”High”: Command Write C/D=”Low”: Data Write.
/RD = “Low” ….. C/D=”High”: Status Read
C/D=”Low”: Data Read.
“High”: Normal (T6963C has internal pull-up resistor).
“Low”: Initialize T6963C. Text and graphic have addresses and text and graphic
area settings are retained.
Data input/output (LSB).
Data input/output.
Data input/output.
Data input/output.
Data input/output.
Data input/output.
10
11
12
13
14
15
16
17
18
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
FS
Data input/output.
Data input/output (MSB).
Font select.
“High” for 6 x 8 font &
“Low” for 8 x 8 font.
-
-
A
K
Anode of backlight
Cathode of backlight
Note 1: This pin is electrically connected to the metal bezel (frame).
User can choose to connect this pin to VSS or leave it open.
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 8 OF 11
4.
Absolute Maximum Ratings
4.1
Electrical Maximum Ratings(Ta = 25 º C)
Table 3
Symbol
VDD - VSS
VLCD
Parameter
Min.
-0.3
-0.3
Max.
+7.0
+30.0
Unit
V
V
Supply voltage (Logic & LCD)
Supply voltage (LCD drive)
(Built-in)
=VDD – V0
Vin
Input voltage
-0.3
VDD+0.3
V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
All voltage values are referenced to VSS = 0V.
4.2
Environmental Condition
Table 4
Operating
Storage
Item
Temperature
(Topr)
Temperature
(Tstg)
Remark
Min.
0°C
Max.
+50°C
Min.
-10°C
Max.
+60°C
Ambient Temperature
Humidity
Dry
no condensation
95% max. RH for Ta £ 40°C
< 95% RH for Ta > 40°C
Vibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
3 directions
Frequency: 10 ~ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Shock (IEC 68-2-27)
Half-sine pulse shape
Pulse duration : 11 ms
3 directions
Peak acceleration: 981 m/s2 = 100g
Number of shocks : 3 shocks in 3
mutually perpendicular axes.
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 9 OF 11
5. Electrical Specifications
5.1
Typical Electrical Characteristics
At Ta = 25 °C, VDD = +5V±5%, VSS=0V.
Table 5
Conditions
Parameter
Symbol
VDD -VSS
Min.
4.75
Typ. Max. Unit
Supply voltage
(Logic & LCD)
5.00 5.25
V
Supply voltage (LCD)
VLCD
=VDD –V0
VIH
VIL
IDD
VDD = 5V, Note 1
9.7
10.2 10.7
V
Input signal voltage
“H” level
“L” level
VDD-2.2
-
-
VDD
0.8
V
V
mA
0
-
Supply current
(Logic & LCD)
Character mode,
VDD=5V, Note 1
Checker board mode,
VDD=5V, Note 1
Character mode,
VDD=5V, Note 1
Checker board mode,
VDD=5V, Note 1
Forward current
=240mA
6.2
9.3
-
-
6.4
2.3
2.3
4.1
9.6
3.5
3.5
4.3
mA
mA
mA
V
Supply current (LCD)
I0
-
Supply voltage of
Yellow-green LED04
backlight
VLED
3.9
Number of LED dies
=48.
Note 1:There is tolerance in optimum LCD driving voltage during production and it will be wit the
specified range.
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 10 OF 11
5.2
Timing Specifications
At Ta = 0°C To +50°C, VDD = 5V±5%,VSS=0V
Refer to Fig. 3, the bus timing diagram.
Table 6
Parameter
C/D Set-up time
C/D Hold Time
/CE,/RD,/WR Pulse
Width
Symbol
tCDS
tCDH
Min.
100
10
Max.
Unit
ns
ns
-
-
-
80
ns
tCE, tRD, tWR
Data Set-up Time
Data Hold Time
Access Time
80
40
-
-
-
ns
ns
ns
ns
tDS
tDH
tACC
tOH
150
50
Output Hold Time
10
C/D
/CE
/RD, /WR
Figure 3: Bus Timing Diagram
VL-FS-MGLS12864T-20 REV. B
(MGLS12864T-LED04-LV2)
APR/2004
PAGE 11 OF 11
5.3 Timing Diagram of VDD against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY
VOLTAGE
0V
50ms(typical)
OV
LCD SUPPLY
VOLTAGE
V0
Figure 4: Timing diagram of VDD against V0.
“Varitronix Limited reserves the right to change this specification.”
FAX: (852) 2343-9555.
URL: http://www.varitronix.com
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