BCM4414VG0F4440T06_技术文档

BCM^®in a VIA Package

Bus Converter

BCM4414xG0F4440yzz

S

®

C

NRTL US

C

US

Isolated Fixed-Ratio DC-DC Converter

Features & Beneﬁts

Product Ratings

• Up to 40A continuous low voltage side current

• Fixed transformation ratio (K) of 1/16

• Up to 776W/in³power density

• 97.5% peak efﬁciency

V_HI= 544V (400 – 700V)

I_LO= up to 40A

K = 1/16

V_LO= 34V (25 – 43.8V)

(no load)

Product Description

• Integrated ﬁltering

The BCM4414xG0F4440yzz in a VIA package is a high efﬁciency

Bus Converter, operating from a 400 to 700V_DChigh voltage bus

to deliver an isolated 25 to 43.8V_DCunregulated, low voltage.

• Parallel operation for multi-kW arrays

• OV, OC, UV, short circuit and thermal protection

• 4414 package

This unique ultra-low proﬁle module incorporates DC-DC

conversion, integrated ﬁltering and PMBus™ commands and

controls in a chassis or PCB mount form factor.

• High MTBF

• Thermally enhanced VIA package

• PMBus™ management interface

• Bidirectional operation (start up in forward direction only)

The BCM offers low noise, fast transient response and industry

leading efﬁciency and power density. A low voltage side

referenced PMBus compatible telemetry and control interface

provides access to the BCM’s conﬁguration, fault monitoring, and

other telemetry functions.

Typical Applications

Leveraging the thermal and density beneﬁts of Vicor’s VIA

packaging technology, the BCM module offers ﬂexible thermal

management options with very low top and bottom side

thermal impedances.

• High Voltage DC Power Distribution

• 3 Phase AC-DC Converters

• Information and Communication

Technology (ICT) Equipment

When combined with downstream Vicor DC-DC conversion

components and regulators, the BCM allows the Power Design

Engineer to employ a simple, low-proﬁle design, which will

differentiate the end system without compromising on cost or

performance metrics.

• High End Computing Systems

• Automated Test Equipment

• Industrial Systems

• High Density Energy Systems

• Transportation

• Green Buildings and Microgrids

Size:

4.35 x 1.40 x 0.37in

[110.55 x 35.54 x 9.40mm]

Part Ordering Information

High

Side

Voltage

Range

Ratio

Max

High

Side

Max

Low

Side

Max

Low

Side

Product

Function

Package

Length

Package

Width

Package

Type

Product Grade

(Case Temperature)

Option Field

Voltage

Voltage Current

BCM

44

14

x

G0

F

44 40

y

zz

BCM =

Bus Converter

Module

02 = Chassis/PMBus

06 = Short Pin/PMBus

10 = Long Pin/PMBus

Length in

Width in

B = Board VIA

C = –20 to 100°C ^[a]

T = –40 to 100°C ^[a]

Internal Reference

Inches x 10 Inches x 10 V = Chassis VIA

^[a]High temperature current derating may apply; See Figure 1, speciﬁed thermal operating area.

BCM^®in a VIA™ Package

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Typical Applications

3 Phase AIM

BCMin a VIA package

+

-

+HI

-HI

+LO

EXT_BIAS

SCL

L

O

A

D

L1

L2

L3

SDA

SGND

ADDR

-LO

ISOLATION BOUNDARY

3 phase AC to point of load (3 phase AIM + BCM4414xG0F4440yzz)

BCM in a VIA package

+HI

-HI

+LO

EXT_BIAS

SCL

5V

SDA

SGND

ADDR

R1

-LO

SCL

ISOLATION BOUNDARY

Host PMBus™

SDA

SGND

L

O

A

D

+

–

DC

BCM in a VIA package

+HI

-HI

+LO

EXT_BIAS

SCL

5V

SDA

SGND

ADDR

R2

-LO

ISOLATION BOUNDARY

Paralleling BCM in a VIA package – connection to common Host PMBus

BCM^®in a VIA™ Package

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Typical Applications (Cont.)

Host PMBus™

PMBus

+

–

V

EXT

SGND

PRM

BCM in a VIA Package

ENABLE

TRIM

VAUX

enable/disable

switch

EXT_BIAS

SCL

REF/

REF_EN

VTM

V

OUT

Adaptive Loop Temperature Feedback

VTM Start Up Pulse

AL

VT

VC

IFB

TM

VC

PC

+OUT

3

SHARE/

CONTROL NODE

SDA

PRM_SGND

}

R

AL_PRM

TRIM_PRM

PRM_SGND

SGND

R

SGND

LOAD

C

R

O_VTM_CER

ADDR

I_PRM_DAMP

O_PRM_DAMP

FUSE

+HI

+IN

–IN

+OUT

–OUT

+IN

–IN

+LO

–LO

L

I_PRM_FLT

O_PRM_FLT

C

V

C

R

I_PRM_CER

HI

O_PRM_CER

–HI

–OUT

SGND

HV

LV

ISOLATION BOUNDARY

HV

LV

ISOLATION BOUNDARY

SOURCE_RTN

LOAD_RTN

PRM_SGND

BCM4414xG0F4440yzz + PRM + VTM, Adaptive Loop Conﬁguration – connection to common Host PMBus

Host PMBus™

PMBus

+

–

V

EXT

SGND

V

REF

BCM in a VIA Package

SGND

REF 3312

IN OUT

PRM

SGND

Voltage Sense and Error Amplifier

(Differential)

EXT_BIAS

SCL

GND

VAUX

ENABLE

TRIM

enable/disable

switch

VTM

REF/

REF_EN

SGND

3

VT

VC

IFB

TM

VC

+OUT

AL

Voltage Reference with Soft Start

SDA

SHARE/

}

VTM Start up Pulse

CONTROL NODE

SGND

ADDR

SGND

PRM_SGND

V

+

V –

PC

VOUT

+IN

R

LOAD

SGND

C

–IN

I_PRM_DAMP

O_PRM_DAMP

O_VTM_CER

FUSE

+HI

+LO

–LO

+IN

–IN

+OUT

–OUT

+IN

–IN

L

_{External Current Sense}L

O_PRM_FLT

C

V

I_PRM_FLT

C

O_PRM_CER

HI

I_PRM_ELEC

–HI

–OUT

SGND

HV

LV

HV

LV

ISOLATION BOUNDARY

SOURCE_RTN

ISOLATION BOUNDARY

PRM_SGND

0 Ω

BCM4414xG0F4440yzz + PRM + VTM, Remote Sense Conﬁguration – connection to common Host PMBus

BCM^®in a VIA™ Package

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Pin Conﬁguration

1

TOP VIEW

3

+HI

–HI

+LO

5

6

7

8

9

EXT BIAS

SCL

PMBus™

SDA

SGND

ADDR

–LO

2

4

BCM in a 4414 VIA Package - Chassis (Lug) Mount

2

TOP VIEW

4

–HI

+HI

–LO

9

8

7

6

5

ADDR

SGND

SDA

PMBus™

SCL

EXT BIAS

+LO

1

3

BCM in a 4414 VIA Package - Board (PCB) Mount

Note: The dot on the VIA housing indicates the location of the signal pin 9.

Pin Descriptions

Pin Number

Signal Name

Type

Function

1

2

+HI

–HI

HIGH SIDE POWER

High voltage side positive power terminal

High voltage side negative power terminal

HIGH SIDE POWER

RETURN

LOW SIDE

POWER

3

4

+LO

–LO

Low voltage side positive power terminal

Low voltage side negative power terminal

LOW SIDE

POWER RETURN

5

6

7

EXT BIAS

SCL

INPUT

5V supply input

I²C™ Clock, PMBus™ Compatible

I²C Data, PMBus Compatible

SDA

INPUT/OUTPUT

LOW SIDE

SIGNAL RETURN

8

9

SGND

ADDR

Signal Ground

INPUT

Address assignment – Resistor based

Notes: All signal pins (5, 6, 7, 8, 9) are referenced to the low voltage side and isolated from the high voltage side.

Keep SGND signal separated from the low voltage side power return terminal (–LO) in electrical design.

BCM^®in a VIA™ Package

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Absolute Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.

Parameter

Comments

Min

Max

800

1

Unit

V

+HI to –HI

–1

HI_DC or LO_DC Slew Rate

+LO to –LO

V/µs

V

–1

60

–0.3

10

V

EXT BIAS to SGND

0.15

5.5

3.6

A

SCL to SGND

SDA to SGND

ADDR to SGND

–0.3

V

–0.3

V

High voltage side to case

3100

4300

1200

V_DC

Isolation Voltage /

Dielectric Withstand

High voltage side to low voltage side

Low voltage side to case

BCM^®in a VIA™ Package

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Electrical Speciﬁcations

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade); all other speciﬁcations are at T_CASE= 25ºC unless otherwise noted.

Attribute

Symbol

Conditions / Notes

Min

Typ

Max

Unit

General Powertrain Speciﬁcation – Forward Direction Operation (High Voltage Side to Low Voltage Side)

HI Side Voltage Range,

(Continuous)

V_{HI_DC}

400

130

700

350

V

HI Side Voltage Range,

(Transient)

V_{HI_TRANS}

V_{µC_ACTIVE}

HI Side Voltage Initialization

Threshold

HI side voltage where internal controller is initialized,

(powertrain inactive)

Disabled, V_{HI_DC}= 544V

T_CASE≤ 100ºC

6.3

9

HI Side Quiescent Current

No Load Power Dissipation

I_{HI_Q}

mA

10.2

15

V_{HI_DC}= 544V, T_CASE= 25ºC

V_{HI_DC}= 544V

3

30

P_{HI_NL}

W

V_{HI_DC}= 400 – 700V, T_CASE= 25ºC

V_{HI_DC}= 400 – 700V

18

32

V_{HI_DC}= 700V, C_{LO_EXT}= 470µF,

R_{LOAD_LO}= 20% of full load current

4

HI Side Inrush Current Peak

I_{HI_INR_PK}

A

T_CASE≤ 100ºC

8

DC HI Side Current

Transformation Ratio

I_{HI_IN_DC}

K

At I_{LO_OUT_DC}= 40A, T_CASE≤ 70ºC

2.6

A

High voltage to low voltage

K = V_{LO_DC}/ V_{HI_DC},at no load

1/16

V/V

LO Side Current (Continuous)

LO Side Current (Pulsed)

I_{LO_OUT_DC}

T_CASE≤ 70ºC

40

44

A

2ms pulse, 25% duty cycle,

I_{LO_OUT_AVG}≤ 50% rated I_{LO_OUT_DC}

I_{LO_OUT_PULSE}

V_{HI_DC}= 544V, I_{LO_OUT_DC}= 40A

95

94

96

95

92

7

96.9

Efﬁciency (Ambient)

η_AMB

V_{HI_DC}= 400 – 700V, I_{LO_OUT_DC}= 40A

V_{HI_DC}= 544V, I_{LO_OUT_DC}= 20A

%

97.5

96.1

Efﬁciency (Hot)

η_HOT

η_20%

V_{HI_DC}= 544V, I_{LO_OUT_DC}= 40A, T_CASE= 70°C

8A < I_{LO_OUT_DC}< 40A

%

Efﬁciency (Over Load Range)

R_{LO_COLD}

R_{LO_AMB}

R_{LO_HOT}

F_SW

V_{HI_DC}= 544V, I_{LO_OUT_DC}= 40A, T_CASE= –40°C

V_{HI_DC}= 544V, I_{LO_OUT_DC}= 40A

10.8

14.4

21.9

0.75

20

22

30

0.8

LO Side Output Resistance

8

mΩ

V_{HI_DC}= 544V, I_{LO_OUT_DC}= 40A, T_CASE= 70°C

LO side voltage ripple frequency = 2x F_SW

18

0.7

Switching Frequency

LO Side Voltage Ripple

MHz

mV

C_{LO_EXT}= 0µF, I_{LO_OUT_DC}= 40A,

V_{HI_DC}= 544V, 20MHz BW

300

V_{LO_OUT_PP}

T_CASE≤ 100ºC

800

BCM^®in a VIA™ Package

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BCM4414xG0F4440yzz

Electrical Speciﬁcations (Cont.)

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade); all other speciﬁcations are at T_CASE= 25ºC unless otherwise noted.

Attribute

Symbol

Conditions / Notes

Min

Typ

Max

Unit

General Powertrain Speciﬁcation – Forward Direction Operation (High Voltage Side to Low Voltage Side) Cont.

Effective HI Side Capacitance

(Internal)

C_{HI_INT}

C_{LO_INT}

Effective value at 544V_{HI_DC}

Effective value at 34V_{LO_DC}

0.2

36

µF

Effective LO Side Capacitance

(Internal)

Excessive capacitance may drive module into short

circuit protection

Rated LO Side Capacitance (External) C_{LO_OUT_EXT}

470

Rated LO Side Capacitance (External),

C_{LO_OUT_AEXT}

C_{LO_OUT_AEXT}Max = N • 0.5 • C_{LO_OUT_EXT MAX}, where

N = the number of units in parallel

Parallel Array Operation

Powertrain Hardware Protection Speciﬁcation – Forward Direction Operation (High Voltage Side to Low Voltage Side)

• These built-in powertrain protections are ﬁxed in hardware and cannot be conﬁgured through PMBus™.

• When duplicated in supervisory limits, hardware protections serve a secondary role and become active when supervisory limits are

disabled through PMBus.

Start up into a persistent fault condition. Non-latching

fault detection given V_{HI_DC}> V_{HI_UVLO+}

Auto Restart Time

t_{AUTO_RESTART}

V_{HI_OVLO+}

V_{HI_OVLO–}

900

730

700

1000

750

730

20

1100

780

ms

V

HI Side Overvoltage

Lockout Threshold

HI Side Overvoltage

Recovery Threshold

740

V

HI Side Overvoltage

Lockout Hysteresis

V_{HI_OVLO_HYST}

t_{HI_OVLO}

V

HI Side Overvoltage

Lockout Response Time

10

µs

ms

A

From powertrain active. Fast current limit protection

disabled during soft start

HI Side Soft Start Time

t_{HI_SOFT_START}

I_{LO_OUT_OCP}

t_{LO_OUT_OCP}

I_{LO_OUT_SCP}

t_{LO_OUT_SCP}

t_OTP+

1

LO Side Overcurrent Trip Threshold

42

55

50

70

LO Side Overcurrent

Response Time Constant

Effective internal RC ﬁlter

3.6

ms

A

LO Side Short Circuit

Protection Trip Threshold

LO Side Short Circuit

Protection Response Time

1

µs

°C

Overtemperature

Shutdown Threshold

Internal

125

BCM^®in a VIA™ Package

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Electrical Speciﬁcations (Cont.)

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade); all other speciﬁcations are at T_CASE= 25ºC unless otherwise noted.

Attribute

Symbol

Conditions / Notes

Min

Typ

Max

Unit

Powertrain Supervisory Limits Speciﬁcation – Forward Direction Operation (High Voltage Side to Low Voltage Side)

• These supervisory limits are set in the internal controller and can be reconﬁgured or disabled through PMBus™.

• When disabled, the powertrain protections presented in the previous table will intervene during fault events.

HI Side Overvoltage

Lockout Threshold

V_{HI_OVLO+}

V_{HI_OVLO–}

V_{HI_OVLO_HYST}

t_{HI_OVLO}

730

700

750

730

20

780

740

V

HI Side Overvoltage

Recovery Threshold

HI Side Overvoltage

Lockout Hysteresis

V

HI Side Overvoltage

Lockout Response Time

100

360

380

20

µs

V

HI Side Undervoltage

Lockout Threshold

V_{HI_UVLO–}

350

370

399

HI Side Undervoltage

Recovery Threshold

V_{HI_UVLO+}

V_{HI_UVLO_HYST}

t_{HI_UVLO}

V

HI Side Undervoltage

Lockout Hysteresis

V

HI Side Undervoltage

Lockout Response Time

100

50

µs

ms

A

From V_{HI_DC}= V_{HI_UVLO+}to powertrain active (i.e., one

time start up delay from application of V_{HI_DC}to V_{LO_DC}

HI Side Undervoltage Start Up Delay t_{HI_UVLO+_DELAY}

)

LO Side Overcurrent

I_{LO_OUT_OCP}

42

50

70

Trip Threshold

LO Side Overcurrent

t_{LO_OUT_OCP}

Effective internal RC ﬁlter

Internal

2

ms

°C

Response Time Constant

Overtemperature

t_OTP+

125

Shutdown Threshold

Overtemperature

t_OTP–

Internal

105

110

115

Recovery Threshold

C-Grade

T-Grade

–25

–45

Undertemperature

t_UTP

°C

s

Shutdown Threshold (Internal)

Start up into a persistent fault condition. Non-latching

fault detection given V_{HI_DC}> V_{HI_UVLO+}

Undertemperature Restart Time

t_{UTP_RESTART}

3

BCM^®in a VIA™ Package

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50

45

40

35

30

25

20

15

10

5

0

-60

-40

-20

0

20

40

60

80

100 120

Case Temperature (°C)

400V – 700V

Figure 1 — Speciﬁed thermal operating area

1. The BCM in a VIA package is cooled through the bottom case (bottom housing).

2. The thermal rating is based on typical measured device efﬁciency.

3. The case temperature in the graph is the measured temperature of the bottom housing, such that the internal operating temperature

does not exceed 125°C.

2500

2250

2000

1750

1500

1250

1000

750

50

45

40

35

30

25

20

15

10

5

500

250

0

400 430 460 490 520 550 580 610 640 670 700

HI Side Voltage (V)

I_{LO_OUT_DC}

I_{LO_OUT_PULSE}

P_{LO_OUT_DC}

P_{LO_OUT_PULSE}

Figure 2 — Speciﬁed electrical operating area using rated R_{LO_HOT}

110

100

90

80

70

60

50

40

30

20

10

0

20

40

60

80

100

LO Side Current (% I_{LO_DC}

)

Figure 3 — Speciﬁed HI side start up into load current and external capacitance

BCM^®in a VIA™ Package

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PMBus™ Reported Characteristics

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade); all other speciﬁcations are at T_CASE= 25ºC unless otherwise noted.

Monitored Telemetry

• The current telemetry is only available in forward operation. The input and output current reported value is not supported in reverse operation.

Accuracy

(Rated Range)

Functional

Reporting Range

Attribute

PMBus^TMRead Command

Update Rate

Reported Units

HI Side Voltage

HI Side Current

LO Side Voltage ^[b]

LO Side Current

LO Side Resistance

Temperature ^[c]

(88h) READ_VIN

(89h) READ_IIN

5% (LL – HL)

130 to 780V

–0.85 to 4.4A

8.125 to 48.75V

–13.6 to 70A

5 to 40mΩ

100µs

100ms

V_ACTUAL= V_REPORTEDx 10^–1

I_ACTUAL= I_REPORTEDx 10^–3

V_ACTUAL= V_REPORTEDx 10^–1

I_ACTUAL= I_REPORTEDx 10^–2

R_ACTUAL= R_REPORTEDx 10^–5

T_ACTUAL= T_REPORTED

20% (10 – 20% of FL)

5% (20 – 133% of FL)

(8Bh) READ_VOUT

5% (LL – HL)

20% (10 – 20% of FL)

5% (20 – 133% of FL)

(8Ch) READ_IOUT

5% (50 – 100% of FL) at NL

10% (50 – 100% of FL)(LL – HL)

(D4h) READ_ROUT

(8Dh) READ_TEMPERATURE_1

7°C (Full Range)

–55 to 130ºC

^[b]Default READ LO Side Voltage returned when unit is disabled = –300V.

^[c]Default READ Temperature returned when unit is disabled = –273°C.

Variable Parameters

• Factory setting of all Thresholds and Warning limits listed below are 100% of speciﬁed protection values.

• Variables can be written only when module is disabled with V_HI< V_{HI_UVLO–}and external bias (VDDB) applied.

• Module must remain in a disabled mode for 3ms after any changes to the variables below to allow sufﬁcient time to commit changes to EEPROM.

Functional

Reporting

Range

Accuracy

(Rated Range)

Default

Attribute

PMBus^TMCommand ^[3]

Conditions / Notes

Value

100%

0ms

HI Side Overvoltage

Protection Limit

V_{HI_OVLO–}is automatically 3%

lower than this set point

(55h) VIN_OV_FAULT_LIMIT

(57h) VIN_OV_WARN_LIMIT

(D7h) DISABLE_FAULTS

(5Bh) IIN_OC_FAULT_LIMIT

(5Dh) IIN_OC_WARN_LIMIT

(4Fh) OT_FAULT_LIMIT

5% (LL – HL)

130 – 750V

130 – 400V

0 – 4.4A

HI Side Overvoltage

Warning Limit

HI Side Undervoltage

Protection Limit

Can only be disabled to a preset

default value

HI Side Overcurrent

Protection Limit

20% (10 – 20% of FL)

5% (20 – 133% of FL)

HI Side Overcurrent

Warning Limit

20% (10 – 20% of FL)

5% (20 – 133% of FL)

0 – 4.4A

Overtemperature

Protection Limit

Internal temperature

7°C (Full Range)

50µs

0 – 125°C

0 – 100ms

Overtemperature

Warning Limit

(51h) OT_WARN_LIMIT

(60h) TON_DELAY

Additional time delay to the

undervoltage start up delay

Turn On Delay

BCM^®in a VIA™ Package

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Signal Characteristics

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade); all other speciﬁcations are at T_CASE= 25ºC unless otherwise noted. Please note: For chassis mount model, Vicor part

number 42550 will be needed for applications requiring the use of the signal pins. Signal cable 42550 is rated up to ﬁve insertions and extractions.

To avoid unnecessary stress on the connector, the cable should be appropriately strain relieved.

EXT. BIAS (VDDB) Pin

• VDDB powers the internal controller.

• VDDB needs to be applied to enable and disable the BCM through PMBus™ control (using OPERATION COMMAND), and to adjust warning and

protection thresholds.

• VDDB voltage not required for telemetry; however, if VDDB is not applied, telemetry information will be lost when V_INis removed.

Signal Type

State

Attribute

VDDB Voltage

Symbol

V_VDDB

Conditions / Notes

Min

Typ

Max

9

Unit

V

4.5

5

Regular

Operation

VDDB Current Consumption

Inrush Current Peak

Turn On Time

I_VDDB

50

mA

A

INPUT

I_{VDDB_INR}

t_{VDDB_ON}

V_VDDBslew rate = 1V/µs

3.5

1.5

Start Up

From V_{VDDB_MIN}to PMBus active

ms

SGND Pin

• All PMBus interface signals (SCL, SDA, ADDR) are referenced to SGND pin.

• SGND pin also serves as return pin (ground pin) for VDDB.

• Keep SGND signal separated from the low voltage side power return terminal (–LO) in electrical design.

Address (ADDR) Pin

• This pin programs the address using a resistor between ADDR pin and signal ground.

• The address is sampled during start up and is stored until power is reset. This pin programs only a Fixed and Persistent address.

• This pin has an internal 10kΩ pullup resistor to 3.3V.

• 16 addresses are available. The range of each address is 206.25mV (total range for all 16 addresses is 0 – 3.3V).

Signal Type

State

Attribute

Symbol

Conditions / Notes

See address section

Min

Typ

Max

Unit

ADDR Input Voltage

V_SADDR

I_SADDR

t_SADDR

0

3.3

1

V

Regular

Operation

MULTI‐LEVEL

INPUT

ADDR Leakage Current

ADDR Registration Time

Leakage current

From V_{VDDB_MIN}

µA

ms

Start Up

1

BCM^®in a VIA™ Package

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Rev 1.2

01/2018

BCM4414xG0F4440yzz

Serial Clock input (SCL) AND Serial Data (SDA) Pins

• High power SMBus speciﬁcation and SMBus physical layer compatible. Note that optional SMBALERT# is not supported.

• PMBus^TMcommand compatible.

Signal Type

State

Attribute

Symbol

Conditions / Notes

Min

Typ

Max

Unit

Electrical Parameters

V_IH

V_IL

2.1

3

V

Input Voltage Threshold

Output Voltage Threshold

0.8

V_OH

V

V_OL

0.4

10

V

Leakage Current

I_{LEAK_PIN}

I_LOAD

Unpowered device

µA

mA

Signal Sink Current

V_OL= 0.4V

4

Total capacitive load of

one device pin

Signal Capacitive Load

C_I

10

pF

Signal Noise Immunity

Timing Parameters

Operating Frequency

V_{NOISE_PP}

10 – 100MHz

300

mV

F_SMB

t_BUF

t_HD:STA

t_SU:STA

Idle state = 0Hz

10

400

kHz

µs

Free Time Between

Stop and Start Condition

1.3

DIGITAL

INPUT/OUTPUT

Regular

Operation

Hold Time After Start or

Repeated Start Condition

First clock is generated

after this hold time

0.6

µs

Repeat Start Condition

Set-Up Time

Stop Condition Set-Up Time

Data Hold Time

t_SU:STO

t_HD:DAT

t_SU:DAT

t_TIMEOUT

t_LOW

0.6

300

100

25

µs

ns

ms

µs

Data Set-Up Time

Clock Low Timeout

Clock Low Period

35

1.3

0.6

Clock High Period

t_HIGH

50

25

Cumulative Clock Low

Extend Time

t_LOW:SEXT

ms

ns

Clock or Data Fall Time

Clock or Data Rise Time

t_F

20

300

t_R

t_LOWt_R

t_F

SCL

V_IH

V_IL

t_HIGH

t_SU,DAT

t_HD,STA

t_HD,DAT

t_SU,STA

t_SU,STO

SDA

V_IH

V_IL

t_BUF

P

S

P

BCM^®in a VIA™ Package

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Timing Diagram (Forward Direction)

BCM^®in a VIA™ Package

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Application Characteristics

Temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the

forward direction (high voltage side to low voltage side). See associated ﬁgures for general trend data.

98.0

97.5

97.0

96.5

96.0

95.5

95.0

94.5

94.0

30

27

24

21

18

15

12

9

6

3

0

-40

-20

0

20

40

60

80

100

400 430 460 490 520 550 580 610 640 670 700

Case Temperature (ºC)

HI Side Input Voltage (V)

T_CASE

:

-40°C

25°C

70°C

V_{HI_DC}

:

400V

544V

700V

Figure 4 — No load power dissipation vs. V_{HI_DC}

Figure 5 — Full load efﬁciency vs. temperature

99

97

80

72

64

56

48

40

32

24

16

8

95

93

91

89

87

85

83

81

79

0

4

8

12

16

20

24

28

32

36

40

0

4

8

12

16

20

24

28

32

36

40

LO Side Output Current (A)

V_{HI_DC}

:

400V

544V

700V

V_{HI_DC}

:

400V

544V

700V

Figure 6 — Efﬁciency at T_CASE= –40°C

Figure 7 — Power dissipation at T_CASE= –40°C

99

97

80

72

64

56

48

40

32

24

16

8

95

93

91

89

87

85

83

81

79

0

4

8

12

16

20

24

28

32

36

40

0

4

8

12

16

20

24

28

32

36

40

LO Side Output Current (A)

V_{HI_DC}

:

400V

544V

700V

V_{HI_DC}

:

400V

544V

700V

Figure 8 — Efﬁciency at T_CASE= 25°C

Figure 9 — Power dissipation at T_CASE= 25°C

BCM^®in a VIA™ Package

Page 14 of 43

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99

97

80

72

64

56

48

40

32

24

16

8

95

93

91

89

87

85

83

81

79

0

4

8

12

16

20

24

28

32

36

40

0

4

8

12

16

20

24

28

32

36

40

LO Side Output Current (A)

V_{HI_DC}

:

400V

544V

700V

V_{HI_DC}

:

400V

544V

700V

Figure 10 — Efﬁciency at T_CASE= 70°C

Figure 11 — Power dissipation at T_CASE= 70°C

25

20

15

10

5

400

360

320

280

240

200

160

120

80

40

0

-40

-20

0

20

40

60

80

100

0

4

8

12

16

20

24

28

32

36

40

Case Temperature (ºC)

LO Side Output Current (A)

V_{HI_DC}

:

544V

I_{LO_DC}

:

40A

Figure 12 — R_LOvs. temperature; Nominal V_{HI_DC}

Figure 13 — V_{LO_OUT_PP}vs. I_{LO_DC}; No external C_{LO_OUT_EXT}Board

.

I_{LO_DC}= 40A at T_CASE= 70°C

mounted module, scope setting: 20MHz analog BW

BCM^®in a VIA™ Package

Page 15 of 43

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BCM4414xG0F4440yzz

Figure 14 — Full load LO side voltage ripple, no external C_{HI_IN_EXT}

;

Figure 15 — 0 – 40A transient response: no external C_{HI_IN_EXT},

no external C_{LO_OUT_EXT}Board mounted module,

no external C_{LO_OUT_EXT}

.

scope setting: 20MHz analog BW

Figure 16 — 40 – 0A transient response: no external C_{HI_IN_EXT}

,

Figure 17 — Start up from application of V_{HI_DC}= 544V, 20% I_{LO_DC},

no external C_{LO_OUT_EXT}

100% C_{LO_OUT_EXT}

Figure 18 — Start up from application of OPERATION COMMAND

with pre-applied V_{HI_DC}= 700V, 20% I_{LO_DC}

,

100% C_{LO_OUT_EXT}

BCM^®in a VIA™ Package

Page 16 of 43

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General Characteristics

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade); all other speciﬁcations are at T_CASE= 25ºC unless otherwise noted.

Attribute

Symbol

Conditions / Notes

Min

Typ

Max

Unit

Mechanical

Length

L

Lug (Chassis) Mount

110.30 [4.34] 110.55 [4.35] 110.80 [4.36]

112.51 [4.43] 112.76 [4.44] 113.01 [4.45]

mm [in]

cm³[in³]

g [oz]

Length

PCB (Board) Mount

Width

W

H

35.29 [1.39]

35.54 [1.40]

9.40 [0.37]

36.93 [2.25]

145 [5.115]

35.79 [1.41]

Height

9.019 [0.355]

9.781 [0.385]

Volume

Weight

Vol

W

Without heatsink

Pin Material

Underplate

C145 copper

Low stress ductile Nickel

Palladium

50

0.8

100

6

µin

Pin Finish (Gold)

Pin Finish (Tin)

Soft Gold

0.12

200

2

Whisker resistant matte Tin

400

Thermal

BCM4414xG0F4440yzz (T-Grade)

BCM4414xG0F4440yzz (C-Grade)

–40

–20

125

Operating Internal Temperature

Operating Case Temperature

T_INT

BCM4414xG0F4440yzz (T-Grade),

derating applied, see safe thermal

operating area

–40

–20

100

°C

T_CASE

BCM4414xG0F4440yzz (C-Grade),

derating applied, see safe thermal

operating area

Estimated thermal resistance to

maximum temperature internal

component from isothermal top

Thermal Resistance Top Side

θ_{INT_TOP}

1.47

0.28

°C/W

Estimated thermal resistance of thermal

coupling between the top and bottom

case surfaces

Thermal Resistance Coupling Between

Top Case and Bottom Case

θ_HOU

Estimated thermal resistance to

maximum temperature internal

component from isothermal bottom

Thermal Resistance Bottom Side

Thermal Capacity

θ_{INT_BOT}

1.59

54

°C/W

Ws/°C

Assembly

BCM4414xG0F4440yzz (T-Grade)

BCM4414xG0F4440yzz (C-Grade)

–40

125

°C

Storage Temperature

ESD Withstand

T_ST

Human Body Model,

“ESDA / JEDEC JDS-001-2012” Class I-C

(1kV to < 2kV)

ESD_HBM

1000

200

Charge Device Model,

“JESD 22-C101-E” Class II (200V to

< 500V)

ESD_CDM

BCM^®in a VIA™ Package

Page 17 of 43

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General Characteristics (Cont.)

Speciﬁcations apply over all line and load conditions, unless otherwise noted; boldface speciﬁcations apply over the temperature range of

–40°C ≤ T_CASE≤ 100°C (T-Grade). All other speciﬁcations are at T_CASE= 25ºC unless otherwise noted.

Attribute

Symbol

Conditions / Notes

Safety

Min

Typ

Max

Unit

Isolation Capacitance

C_{HI_LO}

R_{HI_LO}

Unpowered unit

620

10

780

940

pF

Isolation Resistance

At 500V_DC

MΩ

MIL-HDBK-217Plus Parts Count - 25°C

Ground Benign, Stationary, Indoors /

Computer

1.5

1.8

MHrs

MTBF

Telcordia Issue 2 - Method I Case III;

25°C Ground Benign, Controlled

cTÜVus EN 60950-1

cURus UL 60950-1

Agency Approvals / Standards

CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable

BCM^®in a VIA™ Package

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BCM in a VIA Package

I_HI

I_LO

R_LO

+

V•I

K

K • I_LO

K • V_HI

+

–

+

–

V_HI

V_LO

I_{HI_Q}

–

Figure 19 — BCM DC model (Forward Direction)

The BCM uses a high frequency resonant tank to move energy

from the high voltage side to the low voltage side and vice versa.

The resonant LC tank, operated at high frequency, is amplitude

modulated as a function of the HI side voltage and the LO side

current. A small amount of capacitance embedded in the high

voltage side and low voltage side stages of the module is sufﬁcient

for full functionality and is key to achieving high power density.

The effective DC voltage transformer action provides additional

interesting attributes. Assuming that R_LO= 0Ω and I_{HI_Q}= 0A,

Equation 3 now becomes Equation 1 and is essentially load

independent, resistor R is now placed in series with V_HI.

R

The BCM4414xG0F4440yzz can be simpliﬁed into the model

shown in Figure 19.

R

BCM

SAC

V

V_Lo_Out

+

–

K = 1/16

K = 1/32

Vin

V_HI

At no load:

V_LO= V_HI• K

(1)

K represents the “turns ratio” of the BCM.

Rearranging Eq (1):

Figure 20 — K = 1/16 BCM with series HI side resistor

The relationship between V_HIand V_LObecomes:

V = V – I • R • K

V_LO

K =

(2)

V_HI

(5)

(

)

LO

HI

In the presence of a load, V_LOis represented by:

Substituting the simpliﬁed version of Equation 4

(I_{HI_Q}is assumed = 0A) into Equation 5 yields:

V_LO= V_HI• K – I_LO• R_LO

(3)

V_LO= V_HI• K – I_LO• R • K²

(6)

and I_LOis represented by:

This is similar in form to Equation 3, where R_LOis used to represent

the characteristic impedance of the BCM. However, in this case a

real resistor, R, on the high voltage side of the BCM is effectively

scaled by K²with respect to the low voltage side.

I_HI– I_{HI_Q}

(4)

I_LO

=

K

R_LOrepresents the impedance of the BCM and is a function of the

R_{DS_ON}of the HI side and LO side MOSFETs, PC board resistance of

HI side and LO side boards and the winding resistance of the power

transformer. I_{HI_Q}represents the HI side quiescent current of the

BCM controller, gate drive circuitry and core losses.

Assuming that R = 1Ω, the effective R as seen from the low voltage

side is 3.9mΩ, with K = 1/16.

BCM^®in a VIA™ Package

Page 19 of 43

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A similar exercise can be performed with the addition of a

capacitor or shunt impedance at the high voltage side of the

BCM. A switch in series with V_HIis added to the circuit. This is

depicted in Figure 21.

Low impedance is a key requirement for powering a high-current,

low-voltage load efﬁciently. A switching regulation stage

should have minimal impedance while simultaneously providing

appropriate ﬁltering for any switched current. The use of a BCM

between the regulation stage and the point of load provides a

dual beneﬁt of scaling down series impedance leading back to

the source and scaling up shunt capacitance or energy storage

as a function of its K factor squared. However, these beneﬁts are

not achieved if the series impedance of the BCM is too high. The

impedance of the BCM must be low, i.e., well beyond the crossover

frequency of the system.

S

BCM

SAC

V

Vout

+

–

LO

K = 1/16

C

K = 1/32

VVin

HI

A solution for keeping the impedance of the BCM low involves

switching at a high frequency. This enables the use of small

magnetic components because magnetizing currents remain low.

Small magnetics mean small path lengths for turns. Use of low loss

core material at high frequencies also reduces core losses.

Figure 21 — BCM with HI side capacitor

The two main terms of power loss in the BCM module are:

A change in V_HIwith the switch closed would result in a change in

capacitor current according to the following equation:

ꢀnNo load power dissipation (P_{HI_NL}): deﬁned as the power

used to power up the module with an enabled powertrain

at no load.

dV_HI

ꢀnResistive loss (P_RLO): refers to the power loss across

the BCM module modeled as pure resistive impedance.

I_C(t) = C

(7)

dt

Assume that with the capacitor charged to V_HI, the switch is

opened and the capacitor is discharged through the idealized

BCM. In this case,

P_DISSIPATED= P_{HI_NL}+ P_R

(10)

LO

Therefore,

I_C= I_LO• K

(8)

P_{LO_OUT}= P_{HI_IN}– P_DISSIPATED= P_{HI_IN}– P_{HI_NL}– P_R

(11)

LO

substituting Equation 1 and 8 into Equation 7 reveals:

The above relations can be combined to calculate the overall

module efﬁciency:

C

dV_LO

dt

I_LO(t) =

•

(9)

K²

P_{LO_OUT}

P_{HI_IN}

P_{HI_IN}– P_{HI_NL}– P_R

P_{HI_IN}

LO

η =

=

(12)

The equation in terms of the LO side has yielded a K²scaling factor

for C, speciﬁed in the denominator of the equation.

A K factor less than unity results in an effectively larger capacitance

on the low voltage side when expressed in terms of the high

voltage side. With K = 1/16 as shown in Figure 21, C = 1µF would

2

V_HI• I_HI– P_{HI_NL}– I

• R_LO

( _LO)

=

V_HI• I_HI

appear as C = 256µF when viewed from the low voltage side.

2

P_{HI_NL}+ I

• R_LO

( _LO)

= 1 –

( )

V_HI• I_HI

BCM^®in a VIA™ Package

Page 20 of 43

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Thermal Considerations

The VIA package provides effective conduction cooling from either

of the two module surfaces. Heat may be removed from the top

surface, the bottom surface or both. The extent to which these

two surfaces are cooled is a key component for determining the

maximum power that can be processed by a VIA, as can be seen

from the speciﬁed thermal operating area in Figure 1. Since the

VIA has a maximum internal temperature rating, it is necessary to

estimate this temperature based on a system-level thermal solution.

For this purpose, it is helpful to simplify the thermal solution into

a roughly equivalent circuit where power dissipation is modeled as

a current source, isothermal surface temperatures are represented

as voltage sources and the thermal resistances are represented as

resistors. Figure 22 shows the “thermal circuit” for the VIA module.

θ_INT

+ T_{C_BOT}

s

P_DISS

s

Figure 23 — Single-sided cooling VIA thermal model

ꢀ Double side cooling: while this option might bring limited

advantage to the module internal components (given the

surface-to-surface coupling provided), it might be appealing

in cases where the external thermal system requires allocating

power to two different elements, such as heatsinks with

independent airﬂows or a combination of chassis/air cooling.

+

θ_{INT_TOP}

T_{C_TOP}

–

θ_HOU

s

–

Current Sharing

T_{C_BOT}

θ_{INT_BOT}

+

P_DISS

The performance of the BCM is based on efﬁcient transfer

of energy through a transformer without the need of closed

loop control. For this reason, the transfer characteristic can be

approximated by an ideal transformer with a positive temperature

coefﬁcient series resistance.

s

Figure 22 — Double-sided cooling VIA thermal model

This type of characteristic is close to the impedance characteristic

of a DC power distribution system both in dynamic (AC) behavior

and for steady state (DC) operation.

In this case, the internal power dissipation is P_DISS, θ_{INT_TOP}and

θ

_{INT_BOT}are the thermal resistance characteristics of the VIA module

and the top and bottom surface temperatures are represented as

T_{C_TOP}and T_{C_BOT}. It is interesting to note that the package itself

provides a high degree of thermal coupling between the top and

bottom case surfaces (represented in the model by the resistor

When multiple BCM modules of a given part number are

connected in an array, they will inherently share the load current

according to the equivalent impedance divider that the system

implements from the power source to the point of load. Ensuring

equal current sharing among modules requires that BCM array

impedances be matched.

θ_HOU). This feature enables two main options regarding

thermal designs:

ꢀnSingle side cooling: the model of Figure 22 can be simpliﬁed by

calculating the parallel resistor network and using one simple

thermal resistance number and the internal power dissipation

curves; an example for bottom side cooling only is shown in

Figure 23.

Some general recommendations to achieve matched array

impedances include:

ꢀnDedicate common copper planes/wires within the PCB/Chassis

to deliver and return the current to the modules.

ꢀnProvide as symmetric a PCB/Wiring layout as possible

In this case, θ_INTcan be derived as follows:

among modules

For further details see AN:016 Using BCM Bus Converters

in High Power Arrays.

(θ_{INT_TOP}+ θ_HOU) • θ_{INT_BOT}

θ_{INT_TOP}+ θ_HOU+ θ_{INT_BOT}

θ_INT

=

(13)

BCM^®in a VIA™ Package

Page 21 of 43

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Dielectric Withstand

Z_{HI_EQ1}

Z_{LO_EQ1}

The chassis of the BCM in a VIA package is required to be

connected to Protective Earth when installed in the end

application and must satisfy the requirements of IEC 60950-1 for

Class I products.

BCM^®1

R_{0_1}

V_LO

V_HI

Z_{LO_EQ2}

Z_{HI_EQ2}

BCM^®2

R_{0_2}

Summary

The case is required to be connected to protective earth in the

ﬁnal installation.

+

Load

DC

The construction of the VIA can be summarized by describing it as

a “Class II” component installed in a “Class I” subassembly.

ChiP Isolation

Z_{LO_EQn}

BCM^®n

R_{0_n}

Z_{HI_EQn}

High voltage side

Low voltage side

SELV

Figure 24 — BCM module array

Fuse Selection

In order to provide ﬂexibility in conﬁguring power systems, BCM in

a VIA package modules are not internally fused. Input line fusing

of BCM products is recommended at the system level to provide

thermal protection in case of catastrophic failure.

RI

The fuse shall be selected by closely matching system

requirements with the following characteristics:

Figure 25 — ChiP™ before ﬁnal assembly in the VIA

ꢀnCurrent rating

(usually greater than maximum current of BCM module)

HV VIA Isolation Drawing

ꢀnMaximum voltage rating

(usually greater than the maximum possible input voltage)

ꢀnAmbient temperature

+HI

-HI

+LO

-LO

ChiP

ꢀnNominal melting I²t

High voltage side

Low voltage side

SELV

ꢀnRecommend fuse: see safety agency approvals (HI side)

VIA HI Side Circuit

VIA LO Side Circuit

Reverse Operation

RI

BCM modules are capable of reverse power operation. Once the

unit is started, energy will be transferred from the low voltage

side back to the high voltage side whenever the low side voltage

exceeds V_HI• K. The module will continue operation in this fashion

as long as no faults occur.

FI

BI

PE

The BCM4414xG0F4440yzz has not been qualiﬁed for continuous

operation in a reverse power condition. However, fault protections

that help to protect the module in forward operation will also

protect the module in reverse operation.

Figure 26 — BCM in a VIA package after ﬁnal assembly

Transient operation in reverse is expected in cases where there is

signiﬁcant energy storage on the low voltage side and transient

voltages appear on the high voltage side.

BCM^®in a VIA™ Package

Page 22 of 43

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Filtering

The BCM in a VIA package has built-in single stage EMI ﬁltering

located on the high voltage side. The integrated EMI ﬁltering

consists of a common mode choke and differential mode

capacitors. However, it does not include Y2 capacitors for

common mode ﬁltering. Y2 common mode capacitors can be

added externally on the high voltage side between +HI and PE

(Case), and –HI and PE (Case) to meet certain EMI requirements.

A typical test set-up block diagram for conducted emissions is

shown in Figure 27.

EMI

Receiver

LISN

+HI

+LO

Single

DC

Power

Supply

Screen

Room /

Filters

VIA BCM

(DUT)

Load

–HI

–LO

The integrated ﬁltering reduces the voltage ripple on the high

voltage side. External LO side ﬁltering can be added as needed,

with ceramic capacitance used as a LO side bypass for this purpose.

VIA HI side and LO side voltage ranges shall not be exceeded. An

internal overvoltage function prevents operation outside of the

normal operating HI side range. However, the VIA is exposed to

the applied voltage even when disabled, and must withstand it.

External transient protection circuitry may be required to protect

the VIA from overvoltage transients imposed by a system that

would exceed maximum ratings.

Figure 27 — Typical test set up block diagram for

Conducted Emissions

The source response is generally the limiting factor in the

overall system response, given the wide bandwidth of the BCM.

Anomalies in the response of the source will appear at the LO side

of the module multiplied by its K factor.

Total load capacitance at the LO side of the BCM shall not exceed

the speciﬁed maximum to ensure correct operation in start up.

Due to the wide bandwidth and small LO side impedance of the

BCM, low frequency bypass capacitance and signiﬁcant energy

storage may be more densely and efﬁciently provided by adding

capacitance at the HI side of the BCM.

At frequencies less than 500kHz, the BCM appears as an

impedance of R_LObetween the source and load. Within this

frequency range, capacitance connected at the HI side appears as

an effective scaled capacitance on the LO side per the relationship

deﬁned in Equation 14.

C_HI

C_LO

=

(14)

K²

This enables a reduction in the size and number of capacitors used

in a typical system.

BCM^®in a VIA™ Package

Page 23 of 43

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System Diagram for PMBus™ Interface

5 V

EXT_BIAS

SCL

SDA

SCL

BCM in a VIA

Package

Host

PMBus™

SDA

SGND

ADDR

SGND

The controller of the BCM in a VIA package is referenced to the low voltage side signal ground (SGND).

The BCM in a VIA package provides the Host PMBus system with accurate telemetry monitoring and reporting, threshold and

warning limits adjustment, in addition to corresponding status ﬂags. The standalone BCM is periodically polled for status by the host

PMBus. Direct communication to the BCM is enabled by a page command. For example, the page (0x00) prior to a telemetry inquiry

points to the controller data and page (0x01) prior to a telemetry inquiry points to the BCM parameters.

The BCM enables the PMBus compatible host interface with an operating bus speed of up to 400kHz. The BCM follows the PMBus

command structure and speciﬁcation.

BCM^®in a VIA™ Package

Page 24 of 43

Rev 1.2

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Where:

PMBus™ Interface

Refer to “PMBus Power System Management Protocol Speciﬁcation

Revision 1.2, Part I and II” for complete PMBus speciﬁcations details

at http://pmbus.org.

X, is a “real world” value in units (A, V, °C, s)

Y, is a two’s complement integer received from the BCM controller

m, b and R are two’s complement integers deﬁned as follows:

Device Address

Command

TON_DELAY

Code

60h

88h

89h

8Bh

8Ch

8Dh

96h

A0h

A1h

A4h

A5h

A6h

A7h

D1h

D4h

m

R

3

1

3

1

2

0

5

b

0

The PMBus address (ADDR Pin) should be set to one of the

predetermined 16 possible addresses shown in the table below

using a resistor between the ADDR pin and SGND pin.

1

READ_VIN

1

READ_IIN

1

The BCM accepts only a ﬁxed and persistent address and does not

support SMBus address resolution protocol. At initial power-up, the

BCM controller will sample the address pin voltage and will keep

this address until device power is removed.

READ_VOUT ^[d]

READ_IOUT

1

READ_TEMPERATURE_1 ^[e]

READ_POUT

1

Slave

Address

Recommended

Resistor R_ADDR(Ω)

ID

HEX

1

MFR_VIN_MIN

MFR_VIN_MAX

MFR_VOUT_MIN

MFR_VOUT_MAX

MFR_IOUT_MAX

MFR_POUT_MAX

READ_K_FACTOR

READ_BCM_ROUT

1

2

1010 000b

1010 001b

1010 010b

1010 011b

1010 100b

1010 101b

1010 110b

1010 111b

1011 000b

1011 001b

1011 010b

1011 011b

1011 100b

1011 101b

1011 110b

1011 111b

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

487

1050

1

3

1870

1

4

2800

1

5

3920

1

65536

1

6

5230

7

6810

8

8870

^[d]Default READ LO side voltage returned when BCM unit is disabled = –300V.

^[e]Default READ Temperature returned when BCM unit is disabled = –273°C.

9

11300

14700

19100

25500

35700

53600

97600

316000

10

11

12

13

14

15

16

No special formatting is required when lowering the supervisory

limits and warnings.

Reported DATA Formats

The BCM controller employs a direct data format where all

reported measurements are in Volts, Amperes, Degrees Celsius,

or Seconds. The host uses the following PMBus speciﬁcation

to interpret received values metric preﬁxes. Note that the

COEFFICIENTS command is not supported:

1

m

X =

(

• (Y • 10^-R- b)

)

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Supported Command List

Command

Code

Function

Default Data Content

Data Bytes

PAGE

00h

01h

Access BCM stored information

Turn BCM on or off

00h

80h

N/A

20h

64h

00h

1

OPERATION

CLEAR_FAULTS

CAPABILITY

03h

Clear all faults

PMBus^TMkey capabilities set by factory

None

1

19h

OT_FAULT_LIMIT

OT_WARN_LIMIT

VIN_OV_FAULT_LIMIT

VIN_OV_WARN_LIMIT

IIN_OC_FAULT_LIMIT

IIN_OC_WARN_LIMIT

TON_DELAY

4Fh ^[f]

51h ^[f]

55h ^[f]

57h ^[f]

5Bh ^[f]

5Dh ^[f]

60h ^[f]

78h

Overtemperature protection

2

Overtemperature warning

2

High voltage side overvoltage protection

High voltage side overvoltage warning

High voltage side overcurrent protection

High voltage side overcurrent warning

Start up delay in addition to ﬁxed delay

Summary of faults

2

STATUS_BYTE

1

STATUS_WORD

STATUS_IOUT

79h

Summary of fault conditions

2

7Bh

Overcurrent fault status

1

STATUS_INPUT

7Ch

Overvoltage and undervoltage fault status

1

Overtemperature and undertemperature

fault status

STATUS_TEMPERATURE

7Dh

00h

1

STATUS_CML

7Eh

80h

88h

89h

8Bh

8Ch

8Dh

96h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

PMBus communication fault

Other BCM status indicator

00h

1

STATUS_MFR_SPECIFIC

READ_VIN

Reads HI side voltage

FFFFh

2

READ_IIN

Reads HI side current

FFFFh

2

READ_VOUT

Reads LO side voltage

FFFFh

2

READ_IOUT

Reads LO side current

FFFFh

2

READ_TEMPERATURE_1

READ_POUT

Reads internal temperature

FFFFh

2

Reads LO side power

FFFFh

2

PMBUS_REVISION

MFR_ID

PMBus compatible revision

22h

1

BCM controller ID

“VI”

2

MFR_MODEL

Internal controller or BCM model

Internal controller or BCM revision

Internal controller or BCM factory location

Internal controller or BCM manufacturing date

Internal controller or BCM serial number

Minimum rated high side voltage

Maximum rated high side voltage

Minimum rated low side voltage

Maximum rated low side voltage

Maximum rated low side current

Maximum rated low side power

Reads K factor

Part Number

FW and HW revision

“AP”

18

2

MFR_REVISION

MFR_LOCATION

MFR_DATE

“YYWW”

Serial Number

Varies per BCM

646464646464h

4

MFR_SERIAL

16

2

MFR_VIN_MIN

MFR_VIN_MAX

MFR_VOUT_MIN

MFR_VOUT_MAX

MFR_IOUT_MAX

MFR_POUT_MAX

READ_K_FACTOR

READ_BCM_ROUT

SET_ALL_THRESHOLDS

A0h

A1h

A4h

A5h

A6h

A7h

D1h

D4h

D5h ^[f]

2

Reads low voltage side output resistance

Set supervisory warning and protection thresholds

2

6

Disable overvoltage, overcurrent or

undervoltage supervisory faults

DISABLE_FAULT

D7h ^[f]

00h

2

^[f]The BCM must be in a disabled state with V_HI< V_{HI_UVLO–}and VDDB applied during a write message.

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Command Structure Overview

Write Byte protocol:

The Host always initiates PMBus™ communication with a START bit. All messages are terminated by the Host with a STOP bit. In a write

message, the master sends the slave device address followed by a write bit. Once the slave acknowledges, the master proceeds with the

command code and then similarly the data byte.

1

7

1

8

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Data Byte

A

x = 0

P

x = 0 x = 0

S

Start Condition

Repeated start Condition

Sr

Rd Read

Wr Write

X

A

P

Indicated that ﬁeld is required to have the value of x

Acknowledge (bit may be 0 for an ACK or 1 for a NACK)

Stop Condition

From Master to Slave

From Slave to Master

…

Continued next line

Figure 1 — PAGE COMMAND (00h), WRITE BYTE PROTOCOL

Read Byte protocol:

A Read message begins by ﬁrst sending a Write Command, followed by a REPEATED START Bit and a slave Address. After receiving the

READ bit, the BCM controller begins transmission of the Data responding to the Command. Once the Host receives the requested Data, it

terminates the message with a NACK preceding a stop condition signifying the end of a read transfer.

1

7

1

8

1

7

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Sr Slave Address Rd

A

Data Byte

A

x = 1

P

x = 0 x = 0

x = 1 x = 0

Figure 2 — ON_OFF_CONFIG COMMAND (02h), READ BYTE PROTOCOL

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Write Word protocol:

When transmitting a word, the lowest order byte leads the highest order byte. Furthermore, when transmitting a Byte, the least signiﬁcant

bit (LSB) is sent last. Refer to System Management Bus (SMBus) speciﬁcation version 2.0 for more details.

Note: Extended command and Packet Error Checking Protocols are not supported.

1

7

1

8

1

8

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Data Byte Low

A

x = 0

Data Byte High

A

x = 0

P

x = 0 x = 0

Figure 3 — TON_DELAY COMMAND (D6h)_WRITE WORD PROTOCOL

Read Word protocol:

1

7

1

8

1

7

1

8

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Sr Slave Address Rd

A

Data Byte Low

A

x = 0

Data Byte High

A

x = 1

P

x = 0 x = 0

x = 1 x = 0

Figure 4 — MFR_VIN_MIN COMMAND (88h)_READ WORD PROTOCOL

Write Block protocol:

1

7

1

8

1

8

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Byte Count = N

A

x = 0

Data Byte 1

A

x = 0

...

x = 0 x = 0

...

8

1

8

1

Data Byte 2

A

x = 0

...

Data Byte N

A

x = 0

P

Figure 5 — SET_ALL_THRESHOLDS COMMAND (D5h)_WRITE BLOCK PROTOCOL

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Read Block protocol:

1

7

1

8

1

7

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Sr Slave Address Rd

A

Data Byte = N

A

x = 0

...

x = 0 x = 0

x = 1 x = 0

...

8

1

8

1

8

1

Data Byte 1

A

x = 0

Data Byte 2

A

x = 0

...

Data Byte N

A

x = 1

P

Figure 6 — SET_ALL_THRESHOLDS COMMAND (D5h)_READ BLOCK PROTOCOL

Write Group Command protocol:

Note that only one command per device is allowed in a group command.

1

7

1

8

1

8

1

8

1

S

Slave Address Wr

A

Command Code

A

x = 0

Data Byte Low

A

x = 0

Data Byte High

One or more Data Bytes

A

x = 0

...

First Device

x = 0 x = 0

First Command

1

7

1

8

1

8

1

8

1

Sr Slave Address Wr

A

Command Code

A

Data Byte Low

A

x = 0

Data Byte High

A

...

P

Second Device

x = 0 x = 0

Second Command

x = 0

One or more Data Bytes

x = 0

1

7

1

8

1

8

1

8

1

Sr Slave Address Wr

A

Command Code

A

x = 0

Data Byte Low

A

x = 0

Data Byte High

One or more Data Bytes

A

x = 0

Nth Device

x = 0 x = 0

Nth Command

Figure 7 — DISABLE_FAULT COMMAND (D7h)_WRITE

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Supported Commands Transaction Type

Page Command (00h)

A direct communication to the BCM controller and a simulated

communication to non-PMBus™ devices is enabled by a page

command. Supported command access privileges with a

pre-selected PAGE are deﬁned in the following table. Deviation

from this table generates a communication error in

STATUS_CML register.

The page command data byte of 00h prior to a command call will

address the BCM controller speciﬁc data and a page data byte

of 01h would broadcast to the BCM. The value of the Data Byte

corresponds to the pin name trailing number with the exception

of 00h and FFh.

Data Byte

Description

PAGE Data Byte

Access Type

00h

01h

BCM controller

BCM

Command

Code

00h

01h

PAGE

00h

01h

03h

19h

4Fh

R/W

R

R/W

W

OPERATION Command (01h)

OPERATION

CLEAR_FAULTS

CAPABILITY

W

R

The OPERATION command can be used to turn on and off

the connected BCM.

OT_FAULT_LIMIT

OT_WARN_LIMIT

VIN_OV_FAULT_LIMIT

VIN_OV_WARN_LIMIT

IIN_OC_FAULT_LIMIT

IIN_OC_WARN_LIMIT

TON_DELAY

R/W

R

If synchronous start up is required in the system, it is recommended

to use the command from host PMBus in order to achieve

simultaneous array start up.

51h

55h

57h

5Bh

5Dh

60h

78h

79h

7Bh

7Ch

7Dh

7Eh

80h

88h

89h

8Bh

8Ch

8Dh

96h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

A0h

A1h

A4h

A5h

A6h

A7h

D1h

D4h

D5h

D7h

Unit is On when asserted (default)

Reserved

STATUS_BYTE

R/W

R

STATUS_WORD

STATUS_IOUT

R

R/W

STATUS_INPUT

STATUS_TEMPERATURE

STATUS_CML

R

7

6

5

4

3

2

1

0

b

1

0

R

R/W

R

STATUS_MFR_SPECIFIC

READ_VIN

R/W

R

This command accepts only two data values: 00h and 80h. If any

other value is sent the command will be rejected and a CML Data

error will result.

READ_IIN

R

READ_VOUT

R

READ_IOUT

R

READ_TEMPERATURE_1

READ_POUT

R

PMBUS_REVISION

MFR_ID

MFR_MODEL

R

MFR_REVISION

MFR_LOCATION

MFR_DATE

R

MFR_SERIAL

R

MFR_VIN_MIN

R

MFR_VIN_MAX

MFR_VOUT_MIN

MFR_VOUT_MAX

MFR_IOUT_MAX

MFR_POUT_MAX

READ_K_FACTOR

READ_BCM_ROUT

SET_ALL_THRESHOLDS

DISABLE_FAULT

R

R/W

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CLEAR_FAULTS Command (03h)

OT_FAULT_LIMIT Command (4Fh),

OT_WARN_ LIMIT Command (51h),

This command clears all status bits that have been previously set.

Persistent or active faults are re-asserted again once cleared. All

faults are latched once asserted in the BCM controller. Registered

faults will not be cleared when shutting down the BCM

powertrain by recycling the BCM high side voltage or sending

the OPERATION command.

VIN_OV_FAULT_ LIMIT Command (55h),

VIN_OV_WARN_ LIMIT Command (57h),

IIN_OC_FAULT_ LIMIT Command (5Bh),

IIN_OC_WARN_ LIMIT Command (5Dh)

The values of these registers are set in non-volatile memory and

can only be written when the BCM is disabled.

CAPABILITY Command (19h)

The values of the above mentioned faults and warnings are set by

default to 100% of the respective BCM model supervisory limits.

However, these limits can be set to a lower value. For example: In

order for a limit percentage to be set to 80%, one would send a

write command with a (50h) Data Word.

Packet Error Checking is not supported

Maximum supported bus speed is 400kHz

The Device does not have SMBALERT# pin and does

not support the SMBus Alert Response protocol

Any values outside the range of (00h – 64h) sent by a host will be

rejected, will not override the currently stored value and will set the

Unsupported Data bit in STATUS_CML.

Reserved

The SET_ALL_THRESHOLDS COMMAND (D5h) combines in one

block overtemperature fault and warning limits, V_HIovervoltage

fault and warning limits as well as I_LOovercurrent fault and warning

limits. A delay prior to a read command of up to 200ms following a

write of new value is required.

7

6

5

4

3

2

1

0

b

0

1

0

The VIN_UV_WARN_LIMIT (58h) and VIN_UV_FAULT_LIMIT

(59h) are set by the factory and cannot be changed by the host.

However, a host can disable the undervoltage setting using the

DISABLE_FAULT COMMAND (D7h).

The BCM controller returns a default value of 20h. This value

indicates that the PMBus™ frequency supported is up to 400kHz

and that both Packet Error Checking (PEC) and SMBALERT# are

not supported.

All FAULT_RESPONSE commands are unsupported. The BCM

powertrain supervisory limits and powertrain protection will behave

as described in the Electrical Speciﬁcations. In general, once a fault

is detected, the BCM powertrain will shut down and attempt to

auto-restart after a predetermined delay.

TON_DELAY Command (60h)

The value of this register word is set in non-volatile memory and

can only be written when the BCM is disabled.

The maximum possible delay is 100ms. Default value is set

to (00h). The reported value can be interpreted using the

following equation.

TON_DELAY_ACTUAL= t_REPORTED• 10^-3(s)

Staggering start up in an array is possible with the TON_DELAY

Command. This delay will be in addition to any start up delay

inherent in the BCM module. For example: start up delay from

application of V_HIis typically 20ms. When TON_DELAY is greater

than zero, the set delay will be added to it.

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STATUS_BYTE (78h) and STATUS_WORD (79h)

STATUS_WORD

High Byte

Low Byte

STATUS_BYTE

Not Supported: UNKNOWN FAULT OR WARNING

Not Supported: OTHER

UNIT IS BUSY

UNIT IS OFF

Not Supported: FAN FAULT OR WARNING

Not Supported: VOUT_OV_FAULT

POWER_GOOD Negated*

IOUT_OC_FAULT

VIN_UV_FAULT

STATUS_MFR_SPECIFIC

INPUT FAULT OR WARNING

TEMPERATURE FAULT OR WARNING

IOUT/POUT FAULT OR WARNING

PMBus^TMCOMMUNCATION EVENT

NONE OF THE ABOVE

Not Supported: VOUT FAULT OR WARNING

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

b

* equal to POWER_GOOD#

All fault or warning ﬂags, if set, will remain asserted until

cleared by the host or once the BCM and VDDB power is

removed. This includes undervoltage fault, overvoltage fault,

overvoltage warning, overcurrent warning, overtemperature

fault, overtemperature warning, undertemperature fault, reverse

operation, communication faults and analog controller

shutdown fault.

If the BCM controller is powered through VDDB, it will retain the

last telemetry data and this information will be available to the user

via a PMBus Status request. This is in agreement with the PMBus

standard, which requires that status bits remain set until speciﬁcally

cleared. Note that in the case where the BCM V_HIis lost, the status

will always indicate an undervoltage fault, in addition to any other

fault that occurred.

Asserted status bits in all status registers, with the exception of

STATUS_WORD and STATUS_BYTE, can be individually cleared.

This is done by sending a data byte with one in the bit position

NONE OF THE ABOVE bit will be asserted if either the

STATUS_MFR_SPECIFIC (80h) or the High Byte of the

STATUS WORD is set.

corresponding to the intended warning or fault to be cleared. Refer

to the PMBus™ Power System Management Protocol Speciﬁcation

– Part II – Revision 1.2 for details.

STATUS_IOUT (7Bh)

The POWER_GOOD# bit reﬂects the state of the device and does

not reﬂect the state of the POWER_GOOD# signal limits. The

POWER_GOOD_ON COMMAND (5Eh) and POWER_GOOD_OFF

COMMAND (5Fh) are not supported. The POWER_GOOD# bit is

set, when the BCM is not in the active state, to indicate that the

powertrain is inactive and not switching. The POWER_GOOD#

bit is cleared, when the BCM is in the active state, 5ms after the

powertrain is activated allowing for soft start to elapse.

POWER_GOOD# and OFF bits cannot be cleared as they always

reﬂect the current state of the device.

IOUT_OC_FAULT

Not Supported: IOUT_OC_LV_FAULT

IOUT_OC_WARNING

Not Supported: IOUT_UC_FAULT

Not Supported: Current Share Fault

Not Supported: In Power Limiting Mode

Not Supported: POUT_OP_FAULT

Not Supported: POUT_OP_WARNING

The Busy bit can be cleared using CLEAR_ALL Command (03h) or

by writing either data value (40h, 80h) to PAGE (00h) using the

STATUS_BYTE (78h).

7

6

5

4

3

2

1

0

b

1

0

1

0

Fault reporting, such as SMBALERT# signal output, and host

notiﬁcation by temporarily acquiring bus master status is

not supported.

Unsupported bits are indicated above. A one indicates a fault.

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STATUS_INPUT (7Ch)

STATUS_MFR_SPECIFIC (80h)

Reserved

PAGE Data Byte = (01h)

VIN_OV_FAULT

VIN_OV_WARNING

Not Supported: VIN_UV_WARNING

VIN_UV_FAULT

Not Supported: Unit Off For Insufficient

Input Voltage

Reserved

BCM UART CML

Not Supported: IIN_OC_FAULT

Not Supported: IIN_OC_WARNING

Not Supported: PIN_OP_WARNING

Hardware Protections Shutdown Fault

BCM Reverse Operation

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

b

0

1

0

1

0

Unsupported bits are indicated above. A one indicates a fault.

The reverse operation bit, if asserted, indicates that the BCM is

processing current in reverse. Reverse current reported value is

not supported.

STATUS_TEMPERATURE (7Dh)

The BCM has hardware protections and supervisory limits. The

hardware protections provide an additional layer of protection

and have the fastest response time. The Hardware Protections

Shutdown Fault, when asserted, indicates that at least one of the

powertrain protection faults is triggered. This fault will also be

asserted if a disabled fault event occurs after asserting any bit using

the DISABLE_FAULTS COMMAND.

OT_FAULT

OT_WARNING

Not Supported: UT_WARNING

UT_FAULT

Reserved

The BCM UART is designed to operate with the controller UART.

If the BCM UART CML is asserted, it may indicate a hardware or

connection issue between both devices.

Reserved

PAGE Data Byte = (00h)

Reserved

7

6

5

4

3

2

1

0

b

1

0

1

0

BCM at PAGE (01h) is present

Reserved

Unsupported bits are indicated above. A one indicates a fault.

BCM UART CML

STATUS_CML (7Eh)

Hardware Protections Shutdown Fault

BCM Reverse Operation

Invalid Or Unsupported Command Received

Invalid Or Unsupported Data Received

Not Supported: Packet Error Check Failed

7

6

5

4

3

2

1

0

Not Supported: Memory Fault Detected

Not Supported: Processor Fault Detected

Reserved

b

0

When the PAGE COMMAND (00h) data byte is equal to (00h), the

BCM Reverse operation, Analog Controller Shutdown Fault, and

BCM UART CML bit will return the result of the active BCM. The

BCM UART CML will also be asserted if the active BCM

stops responding. The BCM must communicate at least once

to the internal controller in order to trigger this FAULT. The

BCM UART CML can be cleared using the PAGE (00h) CLEAR_

FAULTS (03h) Command.

Other Communication Faults

Not Supported: Other Memory Or Logic

Fault

7

6

5

4

3

2

1

0

b

1

0

1

0

Unsupported bits are indicated above. A one indicates a fault.

The STATUS_CML data byte will be asserted when an unsupported

PMBus™ command or data or other communication fault occurs.

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READ_VIN Command (88h)

READ_POUT Command (96h)

If PAGE data byte is equal to (01h), command will return the BCM’s

LO side power in the following format:

If PAGE data byte is equal to (01h), command will return the BCM’s

HI side voltage in the following format:

P_{LO_ACTUAL}= P_{LO_REPORTED}(W)

V_{HI_ACTUAL}= V_{HI_REPORTED}• 10^-1(V)

If PAGE data byte is equal to (00h), command will also return the

BCM’s LO side power.

READ_IIN Command (89h)

If PAGE data byte is equal to (01h), command will return the BCM’s

HI side current in the following format:

MFR_VIN_MIN Command (A0h),

MFR_VIN_MAX Command (A1h),

MFR_VOUT_MIN Command (A4h),

MFR_VOUT_MAX Command (A5h),

MFR_IOUT_MAX Command (A6h),

MFR_POUT_MAX Command (A7h)

I_{HI_ACTUAL}= I_{HI_REPORTED}• 10^-3(A)

If PAGE data byte is equal (00h), command will also return the

BCM’s HI side current.

READ_VOUT Command (8Bh)

These values are set by the factory and indicate the device HI

side/LO side voltage and LO side current range and LO side

power capacity.

If PAGE data byte is equal to (01h), command will return the BCM’s

LO side voltage in the following format:

If the PAGE data byte is equal to (00h – 01h),commands report the

rated BCM HI side voltage minimum and maximum in Volts, LO side

voltage minimum and maximum in Volts, LO side current maximum

in Amperes and LO side power maximum in Watts.

V_{LO_ACTUAL}= V_{LO_REPORTED}• 10^-1(V)

READ_IOUT Command (8Ch)

If PAGE data byte is equal to (01h), command will return the BCM’s

LO side current in the following format:

I_{LO_ACTUAL}= I_{LO_REPORTED}• 10^-2(A)

If PAGE data byte is equal (00h), command will also return the

BCM’s LO side current.

READ_TEMPERATURE_1 Command (8Dh)

If PAGE data byte is equal to (01h), command will return the BCM’s

temperature in the following format:

T_ACTUAL= T_REPORTED(°C)

If PAGE data byte is equal (00h), command will also return the

BCM’s temperature

BCM^®in a VIA™ Package

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READ_K_FACTOR Command (D1h)

DISABLE_FAULT Command (D7h)

If PAGE data byte is equal to (01h), command will return the BCM’s

K factor in the following format:

DISABLE_FAULT

MSB

LSB

K_FACTOR_ACTUAL= K_FACTOR_REPORTED• 2^-16(V/V)

Reserved

IOUT_OC_FAULT

Reserved

The K factor is deﬁned in the BCM to represent the ratio of the

transformer winding and hence is equal to V_LO/ V_HI.

VIN_OV_FAULT

Reserved

VIN_UV_FAULT

Reserved

READ_BCM_ROUT Command (D4h)

If PAGE data byte is equal to (01h), command will return the BCM’s

LO side resistance in the following format:

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

b

BCM_R_{LO_ACTUAL}= BCM_R_{LO_REPORTED}• 10^-5(Ω)

Unsupported bits are indicated above. A one indicates that the

supervisory fault associated with the asserted bit is disabled.

SET_ALL_THRESHOLDS Command (D5h)

The values of this register block are set in non-volatile memory and

can only be written when the BCM is disabled.

SET_ALL_THRESHOLDS_BLOCK (6 Bytes)

This command allows the host to disable the supervisory faults

and respective statuses. It does not disable the powertrain analog

protections or warnings with respect to the set limits in the

SET_ALL_THRESHOLDS Command.

IOUT_OC_WARN_ LIMIT

IOUT_OC_FAULT_ LIMIT

VIN_OV_WARN_ LIMIT

The HI side undervoltage can only be disabled to a pre-set low

limit as speciﬁed in the Monitored Telemetry Functional

Reporting Range.

VIN_OV_FAULT_ LIMIT

OT_WARN_LIMIT

OT_FAULT_LIMIT

5

4

3

2

1

0

h

64 64 64 64 64 64

The values of this register block are set in non-volatile memory and

can only be written when the BCM is disabled.

This command provides a convenient way to conﬁgure all of the

limits, or any combination of limits described previously using

one command.

V_HIovervoltage, overcurrent and overtemperature values are all set

to 100% of the speciﬁed supervisory limits by default and can only

be set to a lower percentage.

To leave a particular threshold unchanged, set the corresponding

threshold data byte to a value greater than (64h).

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3. The unsupported PMBus command code

The BCM Controller Implementation vs.

PMBus™ Speciﬁcation Rev 1.2

response as described in the Fault Management and Reporting:

nꢀnDeviations from the PMBus speciﬁcation:

a. PMBus section 10.2.5.3, exceptions

The BCM controller is an I²C™ compliant, SMBus™ compatible

device and PMBus command compliant device. This section denotes

some deviation, perceived as differences from the PMBus Part I and

Part II speciﬁcation Rev 1.2.

• The busy bit of the STATUS_BYTE as implemented can

be cleared (80h). In order to maintain compatibility with

the speciﬁcation, (40h) can also be used.

1. The PMBus interface meets all Part I and II PMBus speciﬁcation

requirements with the following differences to the

transport requirement.

ꢀnManufacturer Implementation of the PMBus Spec:

a. PMBus section 10.5, setting the response to a detected

fault condition

Unmet DC parameter Implementation vs SMBus™ spec

• All powertrain responses are pre-set and cannot

be changed.

PMBus

Interface

SMBus

Rev 2.0

Symbol

Parameter

Units

Min Max Min Max

b. PMBus section 10.6, reporting faults and warnings

[a]

to the Host

V_IL

Input Low Voltage

Input High Voltage

Input Leakage per Pin

–

0.99

–

0.8

V

[a]

• SMBALERT# signal and Direct PMBus Device to Host

Communication are not supported. However, the PMBus

interface will set the corresponding fault status bits and

will wait for the host to poll.

V_IH

2.31

10

2.1 V_{VDD_IN}

[b]

I_{LEAK_PIN}

22

–

5

µA

[a]

V

= 3.3V

VDD_IN

[b]

= 5V

BUS

c. PMBus section 10.7, clearing a shutdown due to a fault

2.The BCM accepts 38 PMBus command codes.

Implemented commands execute functions as described in the

PMBus speciﬁcation.

• There is no RESET pin or EN pin in the BCM. Cycling

power to the BCM will not clear a BCM Shutdown. The

BCM will clear itself once the fault condition is removed.

ꢀnDeviations from the PMBus speciﬁcation:

a. Section 15, fault related commands

d. PMBus Section 10.8.1, corrupted data transmission faults:

• Packet error checking is not supported.

• The limits and Warnings unit is implemented as a

percentage (%) a range from decimal (0 – 100) of the

factory set limits.

Data Transmission Faults Implementation

This section describes data transmission faults as implemented in the BCM controller.

Response to Host

STATUS_BYTE

STATUS_CML

Section

Description

Notes

Unsupported

NAK

FFh

CML

Other Fault

Data

10.8.1

10.8.2

10.8.3

Corrupted data

No response; PEC not supported

Sending too few bits

Reading too few bits

X

Host sends or reads too

few bytes

10.8.4

X

Host sends too many

bytes

10.8.5

10.8.6

X

Reading too many bytes

X

Device will ACK own address

BUSY bit in STATUS_BYTE even if

STATUS_WORD is set

10.8.7

Device busy

BCM^®in a VIA™ Package

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Data Content Faults Implementation

This section describes data content fault as implemented in the BCM controller.

Response

STATUS_BYTE

to Host

STATUS_CML

Section

Description

Notes

Other

Fault

Unsupported

Command

Unsupported

Data

NAK

X

CML

X

Improperly set read bit

in the address byte

10.9.1

10.9.2

10.9.3

X

Unsupported

command code

X

Invalid or

unsupported data

X

10.9.4

10.9.5

Data out of range

Reserved bits

No response; not a fault

BCM^®in a VIA™ Package

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BCM in VIA Package Chassis (Lug) Mount Package Mechanical Drawing

'

(5

ꢀ

ꢋꢀ

3

4

1

2

BCM^®in a VIA™ Package

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Rev 1.2

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BCM in VIA Package PCB (Board) Mount Package Mechanical Drawing

5

6

7

8

9

4

3

2

13

OTPVIEW

BTOMSIDE

C(PMNTOIDSE)

0

1

2

1

BCM^®in a VIA™ Package

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BCM in VIA Package PCB (Board) Mount Package Recommended Hole Pattern

'

SDETI'LA

4

3

A

9

8

7

6

5

EDATIL

3

12

MCDHOLPTARNE

1

10

2

1

BCM^®in a VIA™ Package

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BCM4414xG0F4440yzz

4414 UHV VIA BCM TIM PAD Mechanical Drawing

In chassis-mount applications, an insulation layer of Gap Pad TIM is necessary to meet the creepage requirements from the high voltage

side terminals to the case. Vicor part number 45766 is the TIM Pad for 4414 UHV VIA BCM to meet the creepage and is placed between the

UHV VIA BCM and chassis.

BCM^®in a VIA™ Package

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Rev 1.2

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Revision History

Revision

Date

Description

Page Number(s)

1.0

07/05/17

Initial release

n/a

Updated agency approvals

Updated TIM pad mechamical drawing

1, 18

41

1.1

1.2

10/06/17

01/16/18

Updated monitored telemetry technical information

Updated mechanical drawings

10

38 – 40

BCM^®in a VIA™ Package

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Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and

accessory components, fully conﬁgurable AC-DC and DC-DC power supplies, and complete custom

power systems.

Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor

makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves

the right to make changes to any products, speciﬁcations, and product descriptions at any time without notice. Information published by

Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies.

Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

Speciﬁcations are subject to change without notice.

Visit http://www.vicorpower.com/dc-dc/isolated-ﬁxed-ratio/hv-bus-converter-module for the latest product information.

Vicor’s Standard Terms and Conditions and Product Warranty

All sales are subject to Vicor’s Standard Terms and Conditions of Sale, and Product Warranty which are available on Vicor’s webpage

(http://www.vicorpower.com/termsconditionswarranty) or upon request.

Life Support Policy

VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE

EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used

herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to

result in a signiﬁcant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms

and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemniﬁes

Vicor against all liability and damages.

Intellectual Property Notice

Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the

products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property

rights is granted by this document. Interested parties should contact Vicor’s Intellectual Property Department.

The products described on this data sheet are protected by the following U.S. Patents Numbers:

Patents Pending.

Contact Us: http://www.vicorpower.com/contact-us

Vicor Corporation

25 Frontage Road

Andover, MA, USA 01810

Tel: 800-735-6200

Fax: 978-475-6715

www.vicorpower.com

email

Customer Service: custserv@vicorpower.com

Technical Support: apps@vicorpower.com

The PMBus™ name, SMIF, Inc. and logo are trademarks of SMIF, Inc.

I²C™ is a trademark of NXP Semiconductor

All other trademarks, product names, logos and brands are property of their respective owners.

BCM^®in a VIA™ Package

Page 43 of 43

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型号：	BCM4414VG0F4440T06
厂家：	VICOR CORPORATION
描述：	Isolated Fixed-Ratio DC-DC Converter
文件：	总43页 (文件大小：1438K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BCM4414VG0F4440T06 [VICOR]

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