PFM4414BB6M48D0T08 [VICOR]
Two temperature grades including operation to -40°C;
| 型号： | PFM4414BB6M48D0T08 |
| 厂家： | 
VICOR CORPORATION |
| 描述： | Two temperature grades including operation to -40°C |
| 文件： | 总23页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PFM™ in a VIA Package
AC-DC Converter
PFM4414xB6M48D0yzz
S
®
C
NRTL US
C
US
Isolated AC-DC Converter with PFC
Features & Benefits
Product Ratings
VIN = 85 – 264 V
VOUT = 48 V
POUT = up to 400 W
IOUT = 8.33 A
• Universal input (85 to 264 VAC
)
• 48 VOUT, regulated, isolated SELV
• 92% typical efficiency
• Built-in EMI filtering
• Chassis mount or board mount packaging options
• Always-on, self-protecting converter control architecture
• SELV Output
Product Description
The PFM in a VIA Package is a highly advanced 400 W AC-DC
converter operating from a rectified universal AC input which
delivers an isolated and regulated Safety Extra Low Voltage
(SELV) 48 V secondary output.
• Two temperature grades including operation to -40°C
• VIA Package
Robust Mechanical Design
Versatile thermal management capability
• Safe and reliable secondary-side energy storage
• High MTBF
This unique, ultra-low profile module incorporates AC-DC
conversion, integrated filtering and transient surge protection
in a chassis mount or PCB mount form factor.
The PFM enables a versatile two-sided thermal strategy which
greatly simplifies thermal design challenges.
• 140 W/cubic inch power density
• 4414 package
When combined with downstream Vicor DC-DC conversion
components and regulators, the PFM allows the Power Design
Engineer to employ a simple, low-profile design which will
differentiate his end-system without compromising on cost or
performance metrics.
• External rectification and transient protection required
Typical Applications
• Small cell base stations
• Telecom switching equipment
• LED lighting
• Industrial power systems
Size:
4.35 x 1.40 x .37 in
110.6 x 35.5 x 9.3 mm
Part Ordering Information
Output
Voltage
(Range)
Max
Output
Power
Product
Function
Package
Length
Package
Width
Package
Type
Input
Voltage
Range
Ratio
Product Grade
Option Field
PFM
44
14
x
B6
M
48
D0
y
z
z
PFM =
Power Factor
Module
00 = Chassis/Always On
04 = Short Pin/Always On
08 = Long Pin/Always On
Length in Width in
Inches x 10 Inches x 10 V = Chassis VIA
B = Board VIA
C = -20 to 100°C
T = -40 to 100°C
Internal Reference
PFM™ in a VIA Package
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Typical PCB Mount Applications
M1
M2
J1
F1
48 V
+
_
48 V 5 A
L
+OUT
+IN
-IN
+OUT
-OUT
2 x Cool-Power®
ZVS Buck
+
_
3.3 V 10 A
+
+
+
85 -
264 Vac
VIA
VIA
MOV
PFM™
AIM™
C1 C2 C3
Cool-Power®
ZVS Buck
+
_
1.8 V 8 A
-OUT
N
The PCB terminal option allows mounting on an industry standard printed circuit board, with two different pin lengths. Vicor
offers a variety of downstream DC-DC converters driven by the 48 V output of the PFM in a VIA package. The 48 V output is
usable directly by loads that are tolerant of the PFC line ripple, such as fans, motors, relays, and some types of lighting. Use
downstream DC-DC Point of Load converters where more precise regulation is required.
Parts List for Typical PCB Mount Applications
J1
Qualtek 703 W IEC 320-C14 Power Inlet
F1
Littelfuse 0216008.MXP 8 A 250 VAC 5 x 20 mm holder
M1
M2
Vicor AIM™ AIM1714BB6MC7D5yzz
Vicor PFM™ PFM4414BB6M48D0yzz
Nichicon UVR1J472MRD 4700 µF 63 V 3.4 A 22 x 50 mm bent 90° x 2 pcs
or
CDE 380LX472M063K022 4700 µF 63 V 4.9 A 30 x 30 mm snap x 2 pcs
C1
or
Sic Safco Cubisic LP A712121 10,000 µF 63 V 6.4 A 45 x 75 x 12 mm rectangular
Littelfuse TMOV20RP300E VARISTOR 10 kA 300 V 250 J 20 mm
MOV
PFM™ in a VIA Package
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Typical Chassis Mount Applications
M1
M2
J1
F1
48 V
L
+OUT
+IN
-IN
+OUT
Fan
85 -
264 Vac
VIA
AIM™
VIA
MOV
PFM™
C1 C2 C3
-OUT
N
-OUT
Relays
8
8
16
Dispensors
Controller
Coin Box
The PFM in a VIA package is available in Chassis Mount option, saving the cost of a PCB and allowing access to both sides of the
power supply for cooling. The parts list below minimizes the number of interconnects required between necessary components,
and selects components with terminals traditionally used for point to point chassis wiring.
Parts List for Typical Chassis Mount Applications
J1
Qualtek 719 W or 723 W IEC 320-C14 Power Inlet
F1
Littelfuse 0216008.MXP 8 A 250 VAC 5 x 20 mm in a J1, or separate fuse holder
M1
M2
Vicor AIM™ AIM1714VB6MC7D5y00
Vicor PFM™ PFM4414VB6M48D0y00
UCC E32D630HPN103MA67M 10,000 µF, 63 V 7.4 A, 35 x 67 mm screw terminal
C1
or
Kemet ALS30A103DE063, 10,000 µF 63 V 10.8 A 36 x 84 mm screw terminal
MOV
Littelfuse TMOV20RP300E VARISTOR 10 kA 300 V 250 J 20 mm
PFM™ in a VIA Package
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Pin Configuration
TOP VIEW
+IN B1
–IN A1
+OUT
D2
C2 –OUT
4414 VIA PFM - Chassis Mount - Terminals Up
1
TOP VIEW
2
–IN A1
+IN B1
C2 –OUT
D2 +OUT
4414 VIA PFM - PCB Mount - Pins Down
Please note that these Pin drawings are not to scale.
Pin Descriptions
Pin Number
Signal Name
Type
Function
INPUT POWER
A1
B1
C2
D2
–IN
+IN
Negative input power terminal
Positive input power terminal
Negative output power terminal
Positive output power terminal
RETURN
INPUT POWER
OUTPUT POWER
RETURN
–OUT
+OUT
OUTPUT POWER
PFM™ in a VIA Package
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Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
Min
Max
Unit
Input voltage +IN to –IN
1 ms max
0
600
Vpk
Input voltage (+IN to -IN)
Continuous, Rectified
0
275
VRMS
Output voltage (+Out to -Out)
Output current
-0.5
0.0
58
12.4
VDC
A
in/lbs (N-m)
°C
Screw Torque
4 mounting, 2 input, 2 output
T-Grade
4 (0.45)
125
Operating junction temperature
Storage temperature
Dielectric Withstand*
Input-Case
-40
-55
T-Grade
125
°C
See note below
Basic Insulation
2121
4242
707
Vdc
Vdc
Vdc
Input-Output
Reinforced Insulation
Functional Insulation
Output-Case
* Please see Dielectric Withstand section. See page 18.
10.00
8.00
6.00
4.00
2.00
0.00
500
400
300
200
100
0
-60
-40
-20
0
20
40
60
80
100
Case Temperature (°C)
Current
Power
Safe Operating Area
PFM™ in a VIA Package
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Electrical Specifications
Specifications apply over all line and load conditions, 50 Hz and 60 Hz line frequencies, TJ = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified product grade. COUT is 10,000 µF +/- 20% unless otherwise specified.
Attribute
Symbol
Conditions / Notes
Min
85
Typ
Max
Unit
Power Input Specification
Input voltage range,
continuous operation
VIN
VIN
264
600
148
VRMS
V
VRMS
VRMS
Input voltage range,
transient, non-operational (peak)
1 ms
Input voltage cell reconfiguration
low-to-high threshold
VIN-CR+
VIN-CR-
145
135
Input voltage cell reconfiguration
high-to-low threshold
132
Input current (peak)
Source line frequency range
Power factor
IINRP
fline
PF
See Figure 8, Startup Waveforms
Input power >200 W
12
63
A
Hz
-
47
0.96
Differential mode inductance, common mode
inductance may be higher. See section "Source
Inductance Considerations" on page 15.
Input inductance, maximum
Input capacitance, maximum
LIN
1
mH
µF
CIN
After bridge rectifier, between +IN and - IN
1.5
No Load Specification
Input power – no load, maximum
PNL
7
W
Power Output Specification
VIN = 230 Vrms, 100% Load
Output voltage set point
Output voltage, no load
VOUT
46
48
92
50
V
V
VOUT-NL
Over all operating steady state line conditions
42
54
Non-faulting abnormal line and load transient
conditions
Output voltage range (transient)
Output power
VOUT
POUT
30
57.6
400
V
See SOA on Page 5
W
%
VIN = 230 V, full load, exclusive of input rectifier losses
90.5
85 V < VIN < 264 V, full load, exclusive of
input rectifier losses
90
%
%
mV
V
h
Efficiency
85 V < VIN < 264 V, 75% load,
exclusive of input rectifier losses
90
Output voltage ripple,
switching frequency
Over all operating steady-state line and load
conditions, 20 MHz BW, measured at C3, Figure 5
VOUT-PP-HF
VOUT-PP-LF
200
3.0
2000
Output voltage ripple
line frequency
Over all operating steady-state line and load
conditions, 20 MHz BW
7.0
Output capacitance (external)
Output turn-on delay
COUT-EXT
TON
Allows for 20% capacitor tolerance
6800
15000
1000
1000
11
µF
ms
ms
ms
%
ms
%
%
A
From VIN applied
Full load
500
500
5.5
Start-up setpoint aquisition time
Cell reconfiguration response time
Voltage deviation (transient)
Recovery time
TSS
TCR
Full load
%VOUT-TRANS
TTRANS
-37.5
20
300
600
3
Line regulation
%VOUT-LINE
%VOUT-LOAD
IOUT
Full load
Load regulation
10% to 100% load
3
Output current (continuous)
Output current (transient)
SOA
8.33
12.5
IOUT-PK
20 ms duration, average power ≤POUT, max
A
PFM™ in a VIA Package
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, 50 Hz and 60 Hz line frequencies, TJ = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified product grade. COUT is 10,000 µF +/- 20% unless otherwise specified.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Powertrain Protections
Input undervoltage turn-on
Input undervoltage turn-off
Input overvoltage turn-on
Input overvoltage turn-off
Output overvoltage threshold
VIN-UVLO+
VIN-UVLO-
VIN-UVLO-
VIN-UVLO+
VOUT-UVLO+
See Timing Diagram
74
71
83
VRMS
VRMS
VRMS
VRMS
V
65
See Timing Diagram
265
270
273
61
287
64
Instantaneous, latched shutdown
58
Upper start / restart temperature
threshold (case)
TCASE-OTP-
TJ-OTP+
100
°C
°C
°C
Overtemperature shutdown
threshold (junction)
125
Overtemperature shutdown
threshold (case)
TCASE-OTP+
110
Overcurrent blanking time
Input overvoltage response time
Input undervoltage response time
Output overvoltage response time
Short circuit response time
Fault retry delay time
TOC
TPOVP
TUVLO
TSOVP
TSC
Based on line frequency
400
460
40
550
ms
ms
ms
ms
µs
s
Based on line frequency
Powertrain on
200
30
Powertrain on, operational state
See Timing Diagram
270
10
TOFF
Output power limit
PPROT
50% overload for 20 ms typ allowed
400
W
PFM™ in a VIA Package
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Timing diagram
PFM™ in a VIA Package
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Timing diagram (Cont.)
PFM™ in a VIA Package
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Application Characteristics
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
93.6
93.4
93.2
93.0
92.8
92.6
92.4
92.2
92.0
85
105
125
145
165
185
205
225
245
265
85
105 125 145 165 185 205 225 245 265
Input Line Voltage
Input Line Voltage
25°C
Figure 1 — Full load efficiency vs. line voltage
Figure 2 — Typical no load power dissipation vs. VIN ,
module enabled
1.00
0.98
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
800
700
600
500
400
300
200
100
0
0
100
200
300
400
3
1
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
EN61000-3-2, Class D
Output Power (W)
230 V, 50 Hz
1/3x EN61000-3-2, Class A
VIN
:
120 V/60 Hz
100 V/50 Hz
230 V/50 Hz
Figure 4 — Typical power factor vs. VIN and IOUT using typical
Figure 3 — Typical input current harmonics, full load vs. VIN using
applications circuit on pages 2 & 3
typical applications circuit on pages 2 & 3
Figure 5 — Typical switching frequency output voltage ripple
waveform, TCASE = 30ºC, VIN = 230 V, IOUT = 8.3 A,
no external ceramic capacitance, 20 MHZ BW
Figure 6 — Typical line frequency output voltage ripple waveform,
TCASE = 30ºC, VIN = 230 V, IOUT = 8.3 A,
COUT = 10,000 µF. 20 MHZ BW
PFM™ in a VIA Package
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Application Characteristics (Cont.)
Figure 7 — Typical output voltage transient response,
TCASE = 30ºC, VIN = 230 V, IOUT = 8.3 A, 2.1 A
COUT = 10,000 µF
Figure 8 — Typical startup waveform, application of VIN ,
IOUT = 8.3 A, COUT = 10,000 µF
Figure 10 — Line drop out, 230 V 50 Hz, 0° phase,
Figure 9 — 230 V, 120 V range change transient response,
IOUT = 8.3 A, COUT = 10,000 µF
IOUT = 8.3 A, COUT = 10,000 µF
Figure 11 — Line drop out, 90° phase, VIN = 230 V,
Figure 12 — Typical line current waveform, VIN = 120 V,
IOUT = 8.3 A, COUT = 10,000 µF
60 HZ IOUT = 8.3 A, COUT = 10,000 µF
PFM™ in a VIA Package
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Application Characteristics (Cont.)
230V, 90% load, QPk and Avg:
115V, 90% load, QPk and Avg:
Det
ResBW
Meas
MATrd
9 kHz
20 msUnit
55022RED
dBæV
Det
ResBW
Meas
MATrd
9 kHz
20 msUnit
55022RED
dBæV
Att 20 dB
Att 20 dB
INPUT
INPUT
2
T
2
T
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
1
MHz
10 MHz
1
MHz
10 MHz
SGL
SGL
2AV
3QP
2AV
3QP
21.Dec 2015 09:18
150 kHz
Date: 21.DEC.2015 09:18:37
21.Dec 2015 11:12
150 kHz
Date: 21.DEC.2015 11:12:10
30 MHz
30 MHz
Figure 14 — Typical EMI Spectrum, Peak Scan, 90% load, 230 VIN,
COUT = 10,000 µF using Typical Chassis Mount
Application Circuit
Figure 13 — Typical EMI Spectrum, Peak Scan, 90% load,
115 VIN, COUT = 10,000 µF using Typical Chassis
Mount Application Circuit
94
92
90
88
86
84
82
80
78
94
92
90
88
86
84
82
80
78
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Load Current (A)
Load Current (A)
85 V
85 V
115 V
230 V Eff
VIN:
85 V
85 V
115 V
230 V Eff
VIN:
115 V
230 V P Diss
115 V
230 V P Diss
Figure 15 — VIN to VOUT efficiency and power dissipation
Figure 16 — VIN to VOUT efficiency and power dissipation
vs. VIN and IOUT , TCASE = -40ºC
vs. VIN and IOUT , TCASE = 20ºC
94
92
90
88
86
84
82
80
78
50
45
40
35
30
25
20
15
10
0
1
2
3
4
5
6
7
8
9
Load Current (A)
85 V
85 V
115 V
230 V Eff
VIN:
115 V
230 V P Diss
Figure 17 — VIN to VOUT efficiency and power dissipation
vs. VIN and IOUT , TCASE = 80ºC
PFM™ in a VIA Package
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General Characteristics
Specifications apply over all line and load conditions, 50 Hz and 60 Hz line frequencies, TC = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified Product Grade.
Attribute
Symbol
Conditions / Notes
Mechanical
Min
Typ
Max
Unit
Length
L
W
H
110.6 / [4.35]
35.5 / [1.40]
9.3 / [0.37]
36.9 / [2.25]
148 / [5.2]
mm / [in]
mm / [in]
mm / [in]
cm3/ [in3]
g / [oz]
Width
Height
Volume
Weight
Vol
W
Without heatsink
Pin material
Underplate
C145 copper, half hard
Low stress ductile nickel
Palladium
50
0.8
100
6
µin
µin
µin
Pin finish
Soft Gold
0.12
2
Thermal
C - Grade, see derating curve in SOA
T - Grade, see derating curve in SOA
-20
-40
100
100
°C
°C
Operating case temperature
TC
Thermal resistance, junction to case, top
RJC_TOP
RJC_BOT
1.34
1.72
°C/W
Thermal resistance, junction to case,
bottom
°C/W
Coupling thermal resistance,
top to bottom of case, internal
RHOU
0.57
54
°C/W
J/K
Shell Thermal capacity
Thermal design
See Thermal Design on Page 17
Assembly
Human Body Model,
JEDEC JESD 22-A114C.01
ESDHBM
ESDMM
ESDCDM
1,000
N/A
Machine Model,
JEDEC JESD 22-A115B
ESD rating
V
Charged Device Model,
JEDEC JESD 22-C101D
200
Safety
cTUVus, EN60950-1 and IEC 60950-1
cURus, UL 60950-1 and CAN/CSA 60950-1
Agency approvals/standards
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
Touch Current measured in accordance
with IEC 60990 using measuring network
Figure
0.5
mA
3 (PFM in a VIA package only)
PFM™ in a VIA Package
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General Characteristics (Cont.)
Specifications apply over all line and load conditions, 50 Hz and 60 Hz line frequencies, TC = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified Product Grade.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
EMI/EMC Compliance (Pending)
FCC Part 15, EN55022, CISPR22: 2006 +
A1: 2007, Conducted Emissions
Class B Limits - with –OUT
connected to GND
EN61000-3-2: 2009,
Harmonic Current Emissions
Class A
EN61000-3-3: 2005,
Voltage Changes & Flicker
PST <1.0; PLT <0.65; dc <3.3%
dmax <6%
EN61000-4-4: 2004,
Electrical Fast Transients
Level 2, Performance Criteria A
EN61000-4-5: 2006,
Surge Immunity
Level 3, Immunity Criteria A,
external TMOV required
EN61000-4-6: 2009,
Conducted RF Immunity
Level 2, 130 dBµV (3.0 VRMS
)
EN61000-4-8: 1993 + A1 2001,
Power Frequency H-Field 10A/m,
continuous field
Level 3, Performance Criteria A
EN61000-4-11: 2004,
Voltage Dips & Interrupts
Class 2, Performance Criteria A Dips,
Performance Criteria B Interrupts
Reliability
Case
Reliability Assurance Relex Modeling , Studio 2007,v2]
Temp (°C)
Duty Cycle
Condition
MTBF (MHrs)
FIT
1
Telcordia Issue 2, Method I Case 1
25
100%
GB,GC
0.702
1424
MIL-HDBK-217FN2 Parts Count - 25°C Ground Benign,
Stationary, Indoors / Computer
2
3
25
25
100%
100%
GB,GC
GB,GC
0.322
2.43
3102
412
Telcordia Issue 2, Method I Case 3
PFM™ in a VIA Package
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Input Fuse Selection
Product Details and Design Guidelines
PFM in a VIA package products are not internally fused in order to
provide flexibility in configuring power systems. Input line fusing is
recommended at system level, in order to provide thermal protection in
case of catastrophic failure. The fuse shall be selected by closely
matching system requirements with the following characteristics:
Building Blocks and System Designs
Recommended fuse: 216 Series Littelfuse 8A or lower current rating
(usually greater than the PFM maximum current at lowest
input voltage)
L
+OUT
+IN
-IN
+OUT
-OUT
VIA
VIA
AIM™
PFM™
Maximum voltage rating
(usually greater than the maximum possible input voltage)
-OUT
N
Holdup Capacitor
Ambient temperature
Breaking capacity per application requirements
Nominal melting I2t
Figure 18 – 400 W Universal AC-to-DC Supply
Source Inductance Considerations
The VIA PFM is a high efficiency AC-to-DC converter, operating from a
universal AC input to generate an isolated SELV 48 VDC output bus
with power factor correction. It is the key component of an AC-to-DC
power supply system such as the one shown in Figure 18 above.
The PFM Powertrain uses a unique Adaptive Cell Topology that
dynamically matches the powertrain architecture to the AC line
voltage. In addition the PFM uses a unique control algorithm to reduce
the AC line harmonics yet still achieve rapid response to dynamic load
conditions presented to it at the DC output terminals. Given these
unique power processing features, the PFM can expose deficiencies in
the AC line source impedance that may result in unstable operation if
ignored.
The input to the VIA PFM is a rectified sinusoidal AC source with a
power factor maintained by the module with harmonics conforming to
IEC 61000-3-2. Internal filtering enables compliance with the standards
relevant to the application (Surge, EMI, etc.). See EMI/EMC Compliance
standards on Page 14.
It is recommended that for a single PFM, the line source inductance
should be no greater than 1 mH for a universal AC input of 100 - 240 V.
If the PFM will be operated at 240 V nominal only , the source
impedance may be increased to 2 mH. For either of the preceding
operating conditions it is best to be conservative and stay below the
maximum source inductance values. When multiple PF ’s are used on a
single AC line, the inductance should be no greater than 1 mH/N, where
N is the number of PFM’s on the AC branch circuit, or 2 mH/N for 240
Vac operation. It is important to consider all potential sources of series
inductance including and not limited to, AC power distribution
transformers, structure wiring inductance, AC line reactors, and
additional line filters. Non-linear behavior of power distribution
devices ahead of the PFM may further reduce the maximum
The module uses secondary-side energy storage (at the SELV
48 V bus) to maintain output hold up through line dropouts and
brownouts. Downstream regulators also provide tighter voltage
regulation, if required.
Traditional PFC Topology
Full Wave EMI/TVS
Rectifier
Filter
inductance and require testing to ensure optimal performance.
Isolated
DC/DC
Converter
48 V Bus
If the PFM is to be utilized in large arrays, thePFMs should be spread
across multiple phases or sources thereby minimizing the source
inductance requirements, or be operated at a line voltage close to 240
Vac. Vicor Applications should be contacted to assist in the review of
the application when multiple devices are to be used
in arrays.
Figure 19 – Traditional PFC AC-to-DC supply
To cope with input voltages across worldwide AC mains
(85 – 264 Vac), traditional AC-DC power supplies (Figure 19)
use two power conversion stages: 1) a PFC boost stage to step up from a
rectified input as low as 85 Vac to ~380 Vdc; and 2) a DC-DC down
converter from 380 Vdc to a 48 V bus.
Fault Handling
Input Undervoltage (UV) Fault Protection
The input voltage is monitored by the micro-controller to detect an
input under voltage condition. When the input voltage is less than the
VIN-UVLO-, a fault is detected, the fault latch and reset logic disables the
modulator, the modulator stops powertrain switching, and the output
voltage of the unit falls. Aꢀer a time tUVLO, the unit shuts down. Faults
lasting less than tUVLO may not be detected. Such a fault does not go
through an auto-restart cycle. Once the input voltage rises above VIN-
The efficiency of the boost stage and of traditional power supplies is
significantly compromised operating from worldwide AC lines as low
as 85 Vac.
Adaptive Cell™ Topology
, the unit recovers from the input UV fault, the powertrain
resumes normal switching aꢀer a time tON and the output voltage of
UVLO+
With its single stage Adaptive Cell™ topology, the VIA PFM enables
consistently high efficiency conversion from worldwide AC mains to a
48 V bus and efficient secondary-side power distribution.
the unit reaches the set-point voltage within a time tSS
.
PFM™ in a VIA Package
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Overcurrent (OC) Fault Protection
Output Filtering
The VIA PFM requires an output bulk capacitor in the range of 6,800 μF
The unit’s output current, determined by VEAO, VIN_B and the primary-
side sensed output voltage is monitored by the microcontroller to
detect an output OC condition. If the output current exceeds its current
limit, a fault is detected, the reset logic disables the modulator, the
modulator stops powertrain switching, and the output voltage of the
module falls aꢀer a time tOC. As long as the fault persists, the module
goes through an auto-restart cycle with off time equal to tOFF + tON and
on time equal to tOC. Faults shorter than a time tOC may not be
detected. Once the fault is cleared, the module follows its normal start
2
2
C = 2 POUT*(0.005+t )/(V – V
)
*
d
2
1
where:
C
VIA PFM’s output bulk
capacitance in farads
t
Hold-up time in seconds
d
up sequence aꢀer a time tOFF
.
POUT
VIA PFM’s output power in watts
Short Circuit (SC) Fault Protection
V
Output voltage of VIA PFM’s
2
1
The microcontroller determines a short circuit on the output of the unit
by measuring its primary sensed output voltage and EAO. Most
commonly, a drop in the primary-sensed output voltage triggers a short
circuit event. The module responds to a short circuit event within a
time tSC. The module then goes through an auto restart cycle, with an
off time equal to tOFF + tON and an on time equal to tSC, for as long as
the short circuit fault condition persists. Once the fault is cleared, the
unit follows its normal start up sequence aꢀer a time tOFF. Faults
shorter than a time tSC may not be detected.
converter in volts
V
Downstream regulator undervoltage turn off (volts)
–OR–
POUT /IOUT-PK, whichever is greater.
to 15,000 μF for proper operation of the PFC front-end. A minimum
10,000 μF is recommended for full rated output. Capacitance can be
reduced proportionally for lower maximum loads.
Temperature Fault Protection
The microcontroller monitors the temperature within the
The output voltage has the following two components of voltage ripple:
1) Line frequency voltage ripple: 2*fLINE Hz component
PFM . If this temperature exceeds TJ-OTP+, an overtemperature fault is
detected, the reset logic block disables the modulator, the modulator
stops the powertrain switching and the output voltage of the PFM falls.
Once the case temperature falls below TCASE-OTP-, aꢀer a time greater
than or equal to tOFF, the converter recovers and undergoes a normal
restart. For the C-grade version of the converter, this temperature is
75°C. Faults shorter than a time tOTP may not be detected. If the
temperature falls below TCASE-UTP-, an undertemperature fault is
detected, the reset logic disables the modulator, the modulator stops
powertrain switching and the output voltage of the unit falls. Once the
case temperature rises above TCASE-UTP, aꢀer a time greater than or
equal to tOFF, the unit recovers and undergoes a normal restart.
2) Switching frequency voltage ripple: 1 MHz module switching
frequency component (see Figure 5).
Line Frequency Filtering
Output line frequency ripple depends upon output bulk capacitance.
Output bulk capacitor values should be calculated based on line
frequency voltage ripple. High-grade electrolytic capacitors with
adequate ripple current ratings, low ESR and a minimum voltage rating
of 63 V are recommended.
lPK
Output Overvoltage Protection (OVP)
The microcontroller monitors the primary sensed output voltage to
detect output OVP. If the primary sensed output voltage exceeds VOUT-
OVLO+
lPK/2
, a fault is latched, the logic disables the modulator, the modulator
loutDC
stops powertrain switching, and the output voltage of the module falls
aꢀer a time tSOVP. Faults shorter than a time tSOVP may not be detected.
This type of fault is a latched fault and requires that 1) the EN pin be
toggled or 2) the input power be recycled to recover from the fault.
l
fLINE
Hold-up Capacitance
Figure 20 – Output current waveform
The VIA PFM uses secondary-side energy storage (at the SELV 48 V bus)
and optional PRM® regulators to maintain output hold up through line
dropouts and brownouts. The module’s output bulk capacitance can be
sized to achieve the required hold up functionality.
Hold-up time depends upon the output power drawn from the VIA
PFM based AC-to-DC front end and the input voltage range of
downstream DC-to-DC converters.
The following formula can be used to calculate hold-up capacitance for
a system comprised of PFM and a downstream regulator:
PFM™ in a VIA Package
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Based on the output current waveform, as seen in Figure 20, the
following formula can be used to determine peak-to-peak line
frequency output voltage ripple:
to simplify the thermal solution into a roughly equivalent circuit where
power dissipation is modeled as a current source, isothermal surface
temperatures are represented as voltage sources and the thermal
resistances are represented as resistors. Figure 21 shows the “thermal
circuit” for the VIA module.
VPPl
~
=
0.2
POUT /(VOUT * fLINE * C)
*
where:
+
VPP
l
Output voltage ripple Peak-to-peak line frequency
Average output power
RJC_TOP
TC_TOP
POUT
VOUT
fLINE
C
–
Output voltage set point, nominally 48 V
Frequency of line voltage
RHOU
s
–
TC_BOT
Output bulk capacitance
RJC_BOT
+
PDISS
I
I
Maximum average output current
Peak-to-peak line frequency output current ripple
DC
PK
s
Figure 21 – Double sided cooling VIA thermal model
In certain applications, the choice of bulk capacitance may be
determined by hold-up requirements and low frequency output
voltage filtering requirements. Such applications may use the greater
capacitance value determined from these requirements. The ripple
current rating for the bulk capacitors can be determined from the
following equation:
In this case, the internal power dissipation is PDISS, RJC_TOP and RJC_BOT
are thermal resistance characteristics of the VIA module and the top
and bottom surface temperatures are represented as TC_TOP, and TC_BOT
It interesting to notice that the package itself provides a high degree of
thermal coupling between the top and bottom case surfaces
(represented in the model by the resistor RHOU). This feature enables
two main options regarding thermal designs:
.
~
I
=
0.8 POUT /VOUT
ripple
*
Single side cooling: the model of Figure 21 can be simplified by
calculating the parallel resistor network and using one simple
thermal resistance number and the internal power dissipation
curves; an example for bottom side cooling only is shown in
Figure 22.
Switching Frequency Filtering
This is included within the VIA PFM. No external filtering is necessary
for most applications. For the most noise sensitive applications, a
common mode choke followed by two caps to PE GND will reduce
switching noise further.
EMI Filtering and Transient Voltage Suppression
EMI Filtering
The PFM with PFC is designed such that it will comply with EN55022
Class B for Conducted Emissions with the Vicor AIM,
AIM1714xB6MC7D5yzz. The emissions spectrum is shown in Figures
13 & 14. If the positive output is connected to earth ground, a 4700 pF
500 V capacitor on the -OUT terminal to ground is also recommended.
RJC
+ TC_BOT
s
PDISS
EMI performance is subject to a wide variety of external influences
such as PCB construction, circuit layout etc. As such, external
components in addition to those listed herein may be required in
specific instances to gain full compliance to the standards specified.
s
Transient Voltage Suppression
The PFM contains line transient suppression circuitry to meet
specifications for surge (i.e. EN61000-4-5) and fast transient conditions
(i.e. EN61000-4-4 fast transient/“burst”).
Figure 22 – Single-sided cooling VIA thermal model
In this case, RJC can be derived as following:
Thermal Considerations
(RJC_TOP + RHOU) • RJC_BOT
The VIA™ package provides effective conduction cooling from either of
the two module surfaces. Heat may be removed from the top surface,
the bottom surface or both. The extent to which these two surfaces are
cooled is a key component for determining the maximum power that
can be processed by a VIA™, as can be seen from specified thermal
operating area on Page 5. Since the VIA has a maximum internal
temperature rating, it is necessary to estimate this internal temperature
based on a system-level thermal solution. To this purpose, it is helpful
R
JC
=
RJC_TOP + RHOU + RJC_BOT
PFM™ in a VIA Package
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Special care should be taken when enabling the constant-power load
near the auto-ranger threshold, especially with an inductive source
upstream of the VIA PFM. A load current spike may cause a large input
voltage transient, resulting in a range change which could temporarily
reduce the available power (see Adaptive Cell™ Topology below).
Double side cooling: while this option might bring limited
advantage to the module internal components (given the surface-
to-surface coupling provided), it might be appealing in cases where
the external thermal system requires allocating power to two
different elements, like for example heatsinks with independent
airflows or a combination of chassis/air cooling.
Adaptive Cell™ Topology
Powering a Constant Power Load
The Adaptive Cell topology utilizes magnetically coupled “top” and
“bottom” primary cells that are adaptively configured in series or
parallel by a configuration controller comprised of an array of switches.
A microcontroller monitors operating conditions and defines the
configuration of the top and bottom cells through a range
control signal.
When the output voltage of the VIA PFM module is applied to the input
of the downstream regulator, the regulator turns on and acts as a
constant-power load. When the module’s output voltage reaches the
input undervoltage turn on of the regulator, the regulator will attempt
to start. However, the current demand of the downstream regulator at
the undervoltage turn-on point and the hold-up capacitor charging
current may force the VIA PFM into current limit. In this case, the unit
may shut down and restart repeatedly. In order to prevent this multiple
restart scenario, it is necessary to delay enabling a constant-power load
when powered up by the upstream VIA PFM until aꢀer the output set
point of the VIA PFM is reached.
A comparator inside the microcontroller monitors the line voltage and
compares it to an internal voltage reference.
If the input voltage of the PFM crosses above the positive going cell
reconfiguration threshold voltage, the top cell and bottom cell
configure in series and the unit operates in “high” range.
If the peak of input voltage of the unit falls below the negative-going
range threshold voltage for two line cycles, the cell configuration
controller configures the top cell and bottom cell in parallel, the unit
operates in “low” range.
This can be achieved by
1. keeping the downstream constant-power load
off during power up sequence
Power processing is held off while transitioning between ranges and
the output voltage of the unit may temporarily droop. External output
hold up capacitance should be sized to support power delivery to the
load during cell reconfiguration. The minimum specified external
output capacitance is sufficient to provide adequate ride-through
during cell reconfiguration for typical applications. Waveforms
showing active cell reconfiguration can be seen in Figure 9.
and
2. turning the downstream constant-power load
on aꢀer the output voltage of the module
reaches 48 V steady state
Aꢀer the initial startup, the output of the PFM can be allowed to fall to
30 V during a line dropout at full load. In this case, the circuit should
not disable the downstream regulator if the input voltage falls aꢀer it is
turned on; therefore, some form of hysteresis or latching is needed on
the enable signal for the constant power load. The output capacitance
of the VIA PFM should also be sized appropriately for a constant power
load to prevent collapse of the output voltage of the module during line
dropout (see Hold up Capacitance on Page 16). A constant-power load
can be turned off aꢀer completion of the required hold up time during
the power-down sequence or can be allowed to turn off when it reaches
its own undervoltage shutdown point.
Dielectric Withstand
The chassis of the PFM is required to be connected to Protective Earth
when installed in the end application and must satisfy the
requirements of IEC 60950-1 for Class I products. Both sides of the
housing are required to be connected to Protective Earth to satisfy
safety and EMI requirements. Protective earthing can be accomplished
through dedicated wiring harness (example: ring terminal clamped by
mounting screw) or surface contact (example: pressure contact on bare
conductive chassis or PCB copper layer with no solder mask).
The PFM contains an internal safety approved isolating component (VI
ChiP) that provides the Reinforced Insulation from Input to Output.
The isolating component is individually tested for Reinforced
Insulation from Input to Output at 3000 Vac or 4242 Vdc prior to the
final assembly of the VIA™.
The timing diagram in Figure 23 shows the output voltage of the VIA
PFM and the downstream regulator’s enable pin voltage and output
voltage of the PRM regulator for the power up and power down
sequence. It is recommended to keep the time delay approximately 10
to 20 ms.
When the VIA assembly is complete the Reinforced Insulation can only
be tested at Basic Insulation values as specified in the electric strength
Test Procedure noted in clause 5.2.2 of IEC 60950-1.
VIA PFM
48V – 3%
VOUT
Test Procedure Note from IEC 60950-1
PRM UV
Turn on
“For equipment incorporating both REINFORCED INSULATION and
lower grades of insulation, care is taken that the voltage applied to the
REINFORCED INSULATION does not overstress BASIC INSULATION or
SUPPLEMENTARY INSULATION.”
tDELAY
Downstream
Regulator
Enable
Downstream
Regulator
VOUT
tHOLD-UP
Figure 23 – PRM Enable Hold off Waveforms
PFM™ in a VIA Package
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Summary
The final VIA assembly contains basic insulation from input to case,
reinforced insulation from input to output, and functional insulation
from output to case.
The output of the VIA complies with the requirements of SELV circuits
so only functional insulation is required from the output (SELV) to case
(PE) because the case is required to be connected to protective earth in
the final installation. The construction of the VIA can be summarized
by describing it as a “Class II” component installed in a “Class I”
subassembly. The reinforced insulation from input to output can only
be tested at a basic insulation value of 2121 Vdc on the completely
assembled VIA product.
VI ChiP Isolation
Input
Output
SELV
RI
Figure 24 – VI Chip before final assembly in the VIA
VIA PFM Isolation
VI ChiP
Input
Output
SELV
VIA Input Circuit
VIA Output Circuit
RI
BI
PE
FI
Figure 25 – PFM VIA after final assembly
PFM™ in a VIA Package
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VIA PFM Chassis Mount Package Mechanical Drawing
Product outline drawing; Product outline drawings are available in .pdf and .dxf formats.
3D mechanical models are available in .pdf and .step formats.
PFM™ in a VIA Package
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VIA PFM PCB Mount Package Mechanical Drawing and Recommended Land Pattern
9
8
7
6
5
EDITAL
CSALE8:1
4
3
3
12
SDETIAL
1
10
MCDHOLPTARNE
2
1
5
6
7
8
9
3
4
2
13
OTPVIEW
0
1
TBMOVEW
1
2
PFM™ in a VIA Package
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Revision History
Revision
Date
Description
Page Number(s)
1.0
12/24/15
Initial release
n/a
PFM™ in a VIA Package
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Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are
used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS
ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH
RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR
PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable
for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes
no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and
operating safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products
and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is
granted by this document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers: Patents Pending.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
PFM™ in a VIA Package
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