PI3323-00 [VICOR]
14 â 42VIN ZVS Buck Regulator;
| 型号： | PI3323-00 |
| 厂家： | 
VICOR CORPORATION |
| 描述： | 14 â 42VIN ZVS Buck Regulator |
| 文件： | 总36页 (文件大小：1147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZVS Regulators
PI332x-00
14 – 42VIN ZVS Buck Regulator
Product Description
Features & Benefits
The PI332x-00 is a family of high-input-voltage, wide-input-range
DC-DC ZVS Buck regulators integrating controller, power
switches and support components all within a high-density
System-in-Package (SiP).
• High‑Efficiency HV ZVS Buck Topology
• Wide input voltage range of 14 – 42V
• Power‑up into pre‑biased load
The integration of a high-performance Zero-Voltage Switching
(ZVS) topology, within the PI332x-00 series, increases point-of-load
performance providing best-in-class power efficiency. The
PI332x-00 requires only an external inductor, two voltage selection
resistors and minimal capacitors to form a complete DC-DC
switch-mode buck regulator.
• Parallel capable with single‑wire current sharing
• Input Over/Undervoltage Lockout (OVLO/UVLO)
• Output Overvoltage Protection (OVP)
• Overtemperature Protection (OTP)
• Fast and slow current limits
Output Voltage
• Differential amplifier for output remote sensing
• User‑adjustable soft start & tracking
Device
IOUT Max
Set
3.3V
5.0V
Range
2.2 – 4.0V
4.0 – 6.5V
22A
20A
PI3323-00
PI3325-00
•
–40 to 120°C operating range (TINT),
‑LGIZ, ‑BGIZ models
•
–55 to 120°C operating range (TINT),
‑LGMZ, ‑BGMZ, ‑BGMP models
Applications
• HV to PoL Buck Regulator Applications
• Computing, Communications, Industrial,
Automotive Equipment
Package Information
• 10 x 14 x 2.56mm LGA SiP
• 10.5 x 14.5 x 3.05mm BGA SiP
Note: Product images may not highlight current product markings.
ZVS Regulators
Page 1 of 36
Rev 1.6
02/2021
PI332x-00
Contents
Order Information
3
3
Application Description
Output Voltage Set Point
Soft Start Adjust and Tracking
Inductor Pairing
27
27
27
28
28
28
29
30
31
32
33
34
Thermal, Storage and Handling Information
Absolute Maximum Ratings
Functional Block Diagram
3
4
Pin Description
5
Parallel Operation
Package Pinout
6
Filter Considerations
VDR Bias Regulator
PI332x-00 Common Electrical Characteristics
PI3323-00 (3.3VOUT) Electrical Characteristics
PI3325-00 (5.0VOUT) Electrical Characteristics
Functional Description
7
8
Layout Guidelines
15
22
22
22
22
22
22
22
23
23
23
23
23
23
26
Recommended PCB Footprint and Stencil
Package Drawings
ENABLE (EN)
Revision History
Remote Sensing
Warranty
Soft Start
Output Voltage Selection
Output Current Limit Protection
Input Undervoltage Lockout
Input Overvoltage Lockout
Output Overvoltage Protection
Overtemperature Protection
Pulse Skip Mode (PSM)
Variable Frequency Operation
Thermal Characteristics
SiP Power Dissipation as Percentage of Total System Losses
ZVS Regulators
Page 2 of 36
Rev 1.6
02/2021
PI332x-00
Order Information
Nominal
Output Voltage
Rated
Output Current
Product
Temperature Range
Package
Transport Media
PI3323-00-BGIZ
PI3323-00-BGMZ
PI3323-00-BGMP
PI3323-00-LGMZ
PI3325-00-BGIZ
PI3325-00-BGMZ
PI3325-00-BGMP
PI3325-00-LGIZ
PI3325-00-LGMZ
–40 to 120°C
10.5 x 14.5mm BGA
3.3V
5.0V
22A
20A
–55 to 120°C
10.5 x 14.5mm lead-solder BGA
10 x 14mm LGA
–40 to 120°C
–55 to 120°C
TRAY
10.5 x 14.5mm BGA
10.5 x 14.5mm lead-solder BGA
10 x 14mm LGA
–40 to 120°C
–55 to 120°C
Thermal, Storage and Handling Information
Name
Rating
Storage Temperature
–65 to 150°C
–40 to 120°C
–55 to 120°C
245°C
-LGIZ, BGIZ
Internal Operating Temperature
-LGMZ, -BGMZ, -BGMP
Soldering Temperature for 20 seconds
MSL Rating
3
ESD Rating, JESD22-A114F, JESD22-C101F
2kV HBM; 1kV CDM, respectively
Absolute Maximum Ratings
Name
VIN
Rating
–0.7 to 55V
–0.7VDC to 55V
–0.5 to 25V
100mA
VS1
VOUT
SGND
TRK
–0.3 to 5.5V, 30mA
VDR, SYNCI, SYNCO, PWRGD, EN, COMP,
EAO, EAIN, VDIFF, VSN, VSP, TESTx
–0.3 to 5.5V, 5mA
Notes: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the
Electrical Specifications table is not guaranteed. All voltages are referenced to PGND unless otherwise noted.
ZVS Regulators
Page 3 of 36
Rev 1.6
02/2021
PI332x-00
Functional Block Diagram
VS1
VIN
VOUT
Q2
Q1
VSP
VSN
+
-
VDIFF
Power
Control
VDR
VCC
EAIN
CEAIN-INT
EAO
ZVS Control
-
+
VREF
SYNCO
SYNCI
PWRGD
EN
CHF
RZI
Digital Parametric Trim
COMP
TESTx
TRK
PGND
0Ω
Simplified block diagram
ZVS Regulators
Page 4 of 36
Rev 1.6
02/2021
PI332x-00
Pin Description
Name
VS1
Location
Block 1
I/O
Description
Power
Power
Switching Node: and ZVS sense for power switches.
Input Voltage: and sense for UVLO, OVLO and feed forward ramp.
VIN
Block 3
Gate Driver VCC: Internally generated 5.1V. May be used as a bias supply for low power external
loads. See Application Description for important considerations.
VDR
5K
I/O
Synchronization Input: Synchronize to the falling edge of external clock frequency. SYNCI is a
high impedance digital input node and should always be connected to SGND when not in use. The
PI332x-00 family is not optimized for external synchronization functionality. Refer to Application
Description of Parallel Operation for details.
SYNCI
4K
3K
I
Synchronization Output: Outputs a high signal at the start of each clock cycle for the longer of
½ of the minimum period or the on time of the high-side power MOSFET.
SYNCO
O
TEST1
TEST2
TEST3
TEST4
TEST5
2K
1K
1J
I/O
I/O
I/O
I/O
I/O
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
1H
1E
Power Good: High impedance when regulator is operating and VOUT is in regulation.
Otherwise pulls to SGND.
PWRGD
1G
O
Enable Input: Regulator enable control. When asserted active or left floating: regulator is enabled.
Otherwise regulator is disabled.
EN
1F
Block 5
1C
I/O
Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO communication returns. SGND
and PGND are star connected within the regulator package.
SGND
TRK
Soft Start and Track Input: An external capacitor may be connected between TRK pin and SGND
to increase the rise time of the internal reference during soft start.
I
Compensation Capacitor: Connect capacitor for control loop dominant pole. See Error Amplifier
section for details. A default CCOMP of 4.7nF is used in the example.
COMP
1B
O
EAO
EAIN
VDIFF
VSN
1A
2A
O
Error Amp Output: External connection for additional compensation and current sharing.
Error Amp Inverting Input: Connection for the main Vout feedback divider tap
Independent Amplifier Output: Active only when module is enabled.
Independent Amplifier Inverting Input: If unused connect in unity gain.
Independent Amplifier Non-Inverting Input: If unused connect to SGND.
Direct VOUT Connect: for per-cycle internal clamp node and feed-forward ramp.
Power Ground: VIN and VOUT power returns.
I
3A
O
4A
I
VSP
5A
I
VOUT
PGND
6A,B
Block2
Power
Power
ZVS Regulators
Page 5 of 36
Rev 1.6
02/2021
PI332x-00
Package Pinout
SGND
SGND
SGND
PGND
PGND
PGND
TEST5
SGND
SGND
PGND
PGND
PGND
PWRG0
PGND
PGND
PGND
PGND
PGND
TEST4
PGND
PGND
PGND
PGND
PGND
TEST3
PGND
PGND
PGND
PGND
PGND
EA0
EAIN
VDIFF
VSN
COMP
TRK
TEST2
TEST1
SYNC0
SYNC1
VDR
EN
1
2
SGND
SGND
SGND
SGND
SGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
3
4
VSP
PGND
VOUT
5
VOUT
PGND
6
7
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
8
9
10
11
12 PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
13
14
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
10x14mm SiP
Pin Block Name
Group of pins
VIN
A8-10, B8-10, C8-10, D8-10, E8-10, F8-10, G8-10, H8-10, J8-10, K8-10
A14, B14, C14, D14, E14, F14, G14, H14, J14, K14
A12, B12, C12, D12, E12, F12, G12, H12, J12, K12
B5, C4-6, D4-6, E4-6, F2-6, G2-6, H2-6, J2-6, K6
A6, B6
VS1
PGND
PGND
VOUT
SGND
B2-4, C2-3, D1-3, E2-3
ZVS Regulators
Page 6 of 36
Rev 1.6
02/2021
PI332x-00
PI332x-00 Common Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP, VIN = 24V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Differential Amp
[b]
[b]
Open Loop Gain
96
5
120
7
140
12
1
dB
MHz
mV
V
Small Signal Gain-Bandwidth
Input Offset
0.5
Common Mode Input Range
Differential Mode Input Range
Input Bias Current
–0.1
2.5
2
V
–1
–1
1
µA
mA
Output Current
1
Maximum VOUT
IVDIFF = –1mA
4.85
V
Minimum VOUT
IVDIFF = –1mA
20
50
mV
pF
[b]
Capacitive Load Range for Stability
Slew Rate
0
11
V/µs
PWRGD
VOUT Rising Threshold
VPG_HI%
78
75
84
81
90
% VOUT_DC
VOUT Falling Threshold
PWRGD Output Low
VPG_LO%
VPG_SAT
87
% VOUT_DC
V
Sink = 4mA
VIN_DC > 10V
0.4
VDR
Voltage Setpoint
External Loading
VVDR
IVDR
4.9
0
5.05
5.2
2
V
See Application Description for details
mA
Enable
High Threshold
Low Threshold
VEN_HI
VEN_LO
VEN_HYS
0.9
0.7
100
1.0
0.8
200
1.1
0.9
300
V
V
Threshold Hysteresis
mV
Pull Up Voltage Level for
Source Current
VEN_PU
2
V
Pull Up Current
IEN_PU_POS
VIN > 8V, excluding tFR_DLY
50
µA
Reliability
MIL-HDBK-217, 25°C, Ground Benign: GB
Telcordia SR-332, 25°C, Ground Benign: GB
14.6
201
MHrs
MHrs
MTBF
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3”
dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
ZVS Regulators
Page 7 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP, VIN = 24V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Specifications
Input Voltage
Input Current
VIN_DC
IIN_DC
14
24
42
V
A
VIN = 24V, TCASE = 25°C, IOUT = 22A
Short at terminals
3.35
Input Current At Output Short
(Fault Condition Duty Cycle)
IIN_Short
5
mA
Input Quiescent Current
Input Quiescent Current
Input Voltage Slew Rate
Input capacitance, Internal
IQ_VIN
IQ_VIN
VIN_SR
CIN_INT
Disabled
0.94
3.2
1.6
1
mA
mA
V/µs
µF
Enabled, no load, TCASE = 25°C
[b]
Effective value VIN = 24V, 25°C
0.7
Output Specifications
[b]
EAIN Voltage Total Regulation
Output Voltage Trim Range
Line Regulation
VEAIN
0.975
2.2
0.990
3.3
1.005
4.0
V
[b] [c]
VOUT_DC
V
ΔVOUT / ΔVIN At 25°C, 14V < VIN < 42V
ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 20A
0.10
0.10
67
%
Load Regulation
%
Output Voltage Ripple
Output Current
VOUT_AC
IOUT = 20A, COUT = 8 x 100µF, 20MHz BW [d]
mVP-P
[e]
IOUT_DC
0
22
A
Current Limit
IOUT_CL
Typical current limit based on nominal 230nH inductor.
25.1
A
[b]
Maximum Array Size
Output Current, Array of 2
Output Current, Array of 3
NPARALLEL
3
Modules
IOUT_DC_ARRAY2 Total array capability, [b] see applications section for details
IOUT_DC_ARRAY3 Total array capability, [b] see applications section for details
0
0
A
A
[g]
[g]
Protection
Input UVLO Start Threshold
Input UVLO Stop Hysteresis
Input UVLO Response Time
Input OVLO Stop Threshold
Input OVLO Start Hysteresis
Input OVLO Response Time
VUVLO_START
VUVLO_HYS
12.9
1.21
1.25
47
13.8
1.75
V
V
0.85
µs
V
VOVLO
44
VOVLO_HYS
tf
Hysteresis active when OVLO present for at least tFR_DLY
Above set VOUT
0.5
0.9
1.3
V
1.25
µs
Output Overvoltage Protection,
Relative
VOVP_REL
20
%
Output Overvoltage Protection,
Absolute
VOVP_ABS
4.3
4.7
V
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3”
dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Page 8 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP, VIN = 24V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Timing
[f] While in Discontinuous Conduction Mode (DCM) only,
SYNCI grounded
Switching Frequency
Fault Restart Delay
fs
470
500
30
530
kHz
ms
tFR_DLY
Synchronization Input (SYNCI)
–50% and +10% relative to set switching frequency (fS),
while in DCM operating mode only. [c] and [f]
Synchronization Frequency Range
SYNCI Threshold
fSYNCI
250
4.5
550
kHz
V
VSYNCI
2.5
Synchronization Output (SYNCO)
SYNCO High
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Source 1mA
Sink 1mA
20pF load
20pF load
V
V
SYNCO Low
0.5
SYNCO Rise Time
SYNCO Fall Time
10
10
ns
ns
Soft Start, Tracking and Error Amplifier
TRK Active Range (Nominal)
TRK Enable Threshold
VTRK
VTRK_OV
VEAIN_OV
ITRK
0
1.4
60
V
mV
mV
µA
mA
nF
20
40
30
40
80
TRK to EAIN Offset
120
70
Charge Current (Soft Start)
Discharge Current (Fault)
TRK Capacitance, Internal
Soft-Start Time
50
ITRK_DIS
CTRK_INT
tSS
VTRK = 0.5V
8.7
47
CTRK_EXT = 0µF
0.6
0.94
5.06
0.6
56
1.6
ms
mS
V
Error Amplifier Transconductance
PSM Skip Threshold
GMEAO
PSMSKIP
CEAIN_INT
ROUT
EAIN Capacitance, Internal
Error Amplifier Output Impedance
Internal Compensation Capacitor
Internal Compensation Resistor
pF
[b]
1
MΩ
pf
CHF
56
5
RZI
kΩ
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3”
dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
ZVS Regulators
Page 9 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.)
97
95
93
91
89
87
10
9
8
7
6
5
4
3
2
1
0
85
83
81
79
77
2
4
6
8
10
12
14
16
16
16
18
20
20
20
22
22
22
2
4
6
8
10
12
14
16
18
20
20
20
22
22
22
Load Current (A)
14V
Load Current (A)
VIN:
24V
42V
VIN:
24V
14V
42V
Figure 1 — System efficiency, nominal trim,
Figure 4 — System power dissipation, nominal trim,
board temperature = 25°C
board temperature = 25°C
95
93
91
89
87
85
83
81
79
77
10
9
8
7
6
5
4
3
2
1
0
2
4
6
8
10
12
14
18
2
4
6
8
10
12
14
16
18
Load Current (A)
Load Current (A)
14V
VIN:
24V
42V
VIN:
24V
14V
42V
Figure 2 — System efficiency, low trim,
Figure 5 — System power dissipation, low trim,
board temperature = 25°C
board temperature = 25°C
97
95
93
91
89
87
10
9
8
7
6
5
4
3
2
1
0
85
83
81
79
77
2
4
6
8
10
12
14
18
2
4
6
8
10
12
14
16
18
Load Current (A)
Load Current (A)
VIN:
24V
14V
42V
VIN:
24V
14V
42V
Figure 3 — System efficiency, high trim,
Figure 6 — System power dissipation, high trim,
board temperature = 25°C
board temperature = 25°C
ZVS Regulators
Page 10 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.)
97
95
93
91
89
87
10
9
8
7
6
5
4
3
2
1
0
85
83
81
79
77
2
4
6
8
10
12
14
16
16
16
18
20
20
20
22
22
22
2
4
6
8
10
12
14
16
18
20
20
20
22
22
22
Load Current (A)
14V
Load Current (A)
VIN:
24V
42V
VIN:
24V
14V
42V
Figure 7 — System efficiency, nominal trim,
Figure 10 — System power dissipation, nominal trim,
board temperature = 90°C
board temperature = 90°C
95
93
91
89
87
85
83
81
79
77
10
9
8
7
6
5
4
3
2
1
0
2
4
6
8
10
12
14
18
2
4
6
8
10
12
14
16
18
Load Current (A)
Load Current (A)
14V
VIN:
24V
42V
VIN:
24V
14V
42V
Figure 8 — System efficiency, low trim,
Figure 11 — System power dissipation, low trim,
board temperature = 90°C
board temperature = 90°C
97
95
93
91
89
87
10
9
8
7
6
5
4
3
2
1
0
85
83
81
79
77
2
4
6
8
10
12
14
18
2
4
6
8
10
12
14
16
18
Load Current (A)
Load Current (A)
VIN:
24V
14V
42V
VIN:
24V
14V
42V
Figure 9 — System efficiency, high trim,
Figure 12 — System power dissipation, high trim,
board temperature = 90°C
board temperature = 90°C
ZVS Regulators
Page 11 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.)
97
95
93
91
89
87
10
9
8
7
6
5
4
3
2
1
0
85
83
81
79
77
2
4
6
8
10
12
14
16
16
16
18
20
20
20
22
22
22
2
4
6
8
10
12
14
16
18
20
20
20
22
22
22
Load Current (A)
14V
Load Current (A)
VIN:
24V
42V
VIN:
24V
14V
42V
Figure 13 — System efficiency, nominal trim,
Figure 16 — System power dissipation, nominal trim,
board temperature = –40°C
board temperature = –40°C
96
94
92
90
88
86
84
82
80
78
76
74
10
9
8
7
6
5
4
3
2
1
0
2
4
6
8
10
12
14
18
2
4
6
8
10
12
14
16
18
Load Current (A)
Load Current (A)
14V
VIN:
24V
42V
VIN:
24V
14V
42V
Figure 14 — System efficiency, low trim,
Figure 17 — System power dissipation, low trim,
board temperature = –40°C
board temperature = –40°C
99
97
95
93
91
89
87
85
83
81
79
77
10
9
8
7
6
5
4
3
2
1
0
2
4
6
8
10
12
14
18
2
4
6
8
10
12
14
16
18
Load Current (A)
Load Current (A)
VIN:
24V
14V
42V
VIN:
24V
14V
42V
Figure 15 — System efficiency, high trim,
Figure 18 — System power dissipation, high trim,
board temperature = –40°C
board temperature = –40°C
ZVS Regulators
Page 12 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.)
CH2
CH1
CH1
CH2
CH1 VOUT: 50mV/div
CH2 IIN: 1A/div
Timebase: 4ms/div
CH1 IOUT: 5A/div
CH2 VOUT: 200mV/div
Timebase: 200µs/div
Figure 19 — Transient response: 50 – 100% load, at 1A/µs.
nominal line, nominal trim,
Figure 22 — Output short circuit, nominal line
COUT = 8 x 100µF ceramic
CH1
CH1
CH1 VOUT: 20mV/div
Timebase: 2µs/div
CH1 VOUT: 20mV/div
Timebase: 2µs/div
Figure 20 — Output voltage ripple: nominal line, nominal trim,
Figure 23 — Output voltage ripple: nominal line, nominal trim,
100% load, COUT = 8 x 100µF ceramic
50% load, COUT = 8 x 100µF ceramic
525
500
475
450
425
400
375
350
325
300
275
250
22
20
18
16
14
12
10
8
6
4
2
0
Notes:
1. SiP is based on VS1 and VIN paths only.
2. Inductor is based on two leads and base
with inclusion of GEL 30 interface
resistance (0.15mm thick; 3.5W/m-K
thermal conductivity).
225
200
0
2
4
6
8
10 12
Load Current (A)
24V
14 16 18
20
22
20
40
60
80
100
120
Temperature of Isothermal PCB (ºC)
VIN:
14V
42V
Figure 21 — Switching frequency vs. load, nominal trim
Figure 24 — System thermal specified operating area: max IOUT at
nominal trim vs. temperature at locations noted
ZVS Regulators
Page 13 of 36
Rev 1.6
02/2021
PI332x-00
PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.)
18
16
14
12
10
8
CH1
CH2
CH3
CH4
4
6
8
10
12
14
16
18
20
22
Output Current (A)
CH1 VIN: 10V/div
CH2 TRK: 2V/div
CH3 VOUT: 2V/div Timebase: 2.00ms/div
CH4 EN: 2V/div
24V
VIN
:
14V
42V
Figure 25 — Small-signal modulator gain vs. VEAO, nominal trim
Figure 27 — Start up from VIN applied, nominal line, nominal trim,
typical timing, PI3323 shown
6
5
4
3
2
1
0
CH1
CH2
CH3
CH4
4
6
8
10
12
14
16
18
20
22
Output Current (A)
CH1 VIN: 10V/div
CH2 EN: 2V/div
CH3 VOUT: 2V/div
CH4 PWRGD: 2V/div
Timebase: 400µs/div
24V
VIN
:
14V
42V
Figure 26 — rEQ_OUT vs VEAO, nominal trim
Figure 28 — Start up from EN, VIN pre-applied, nominal line,
nominal trim, typical timing, PI3323 shown
ZVS Regulators
Page 14 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5.0VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP, VIN = 24V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Specifications
Input Voltage
Input Current
VIN_DC
IIN_DC
14
24
42
V
A
VIN = 24V, TCASE = 25°C, IOUT = 20A
Short at terminals
4.41
Input Current At Output Short
(Fault Condition Duty Cycle)
IIN_Short
5
mA
Input Quiescent Current
Input Quiescent Current
Input Voltage Slew Rate
Input capacitance, Internal
IQ_VIN
IQ_VIN
VIN_SR
CIN_INT
Disabled
0.94
4.2
1.6
1
mA
mA
V/µs
µF
Enabled, no load, TCASE = 25°C
[b]
Effective value VIN = 24V, 25°C
0.7
Output Specifications
[b]
EAIN Voltage Total Regulation
Output Voltage Trim Range
Line Regulation
VEAIN
0.975
4.0
0.990
5.0
1.005
6.5
V
[b] [c]
VOUT_DC
V
ΔVOUT / ΔVIN At 25°C, 14V < VIN < 42V
ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 20A
0.10
0.10
55.7
%
Load Regulation
%
Output Voltage Ripple
Output Current
VOUT_AC
IOUT = 20A, COUT = 12 x 47µF, 20MHz BW [d]
mVP-P
[e]
IOUT_DC
0
20
A
Current Limit
IOUT_CL
Typical current limit based on nominal 230nH inductor.
24
A
[b]
Maximum Array Size
Output Current, Array of 2
Output Current, Array of 3
NPARALLEL
3
Modules
IOUT_DC_ARRAY2 Total array capability, [b] see applications section for details
IOUT_DC_ARRAY3 Total array capability, [b] see applications section for details
0
0
A
A
[g]
[g]
Protection
Input UVLO Start Threshold
Input UVLO Stop Hysteresis
Input UVLO Response Time
Input OVLO Stop Threshold
Input OVLO Start Hysteresis
Input OVLO Response Time
VUVLO_START
VUVLO_HYS
12.9
1.21
1.25
47
13.8
1.75
V
V
0.85
µs
V
VOVLO
44
VOVLO_HYS
tf
Hysteresis active when OVLO present for at least tFR_DLY
Above set VOUT
0.5
0.9
1.3
V
1.25
µs
Output Overvoltage Protection,
Relative
VOVP_REL
20
%
Output Overvoltage Protection,
Absolute
VOVP_ABS
6.7
7.37
V
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3”
dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Page 15 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5.0VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP, VIN = 24V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Timing
[f] While in Discontinuous Conduction Mode (DCM) only,
SYNCI grounded
Switching Frequency
Fault Restart Delay
fs
564
600
30
636
kHz
ms
tFR_DLY
Synchronization Input (SYNCI)
–50% and +10% relative to set switching frequency (fS),
while in DCM operating mode only. [c] and [f]
Synchronization Frequency Range
SYNCI Threshold
fSYNCI
300
4.5
660
kHz
V
VSYNCI
2.5
Synchronization Output (SYNCO)
SYNCO High
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Source 1mA
Sink 1mA
20pF load
20pF load
V
V
SYNCO Low
0.5
SYNCO Rise Time
SYNCO Fall Time
10
10
ns
ns
Soft Start, Tracking and Error Amplifier
TRK Active Range (Nominal)
TRK Enable Threshold
VTRK
VTRK_OV
VEAIN_OV
ITRK
0
1.4
60
V
mV
mV
µA
mA
nF
20
40
30
40
80
TRK to EAIN Offset
120
70
Charge Current (Soft Start)
Discharge Current (Fault)
TRK Capacitance, Internal
Soft-Start Time
50
ITRK_DIS
CTRK_INT
tSS
VTRK = 0.5V
8.7
47
CTRK_EXT = 0µF
0.6
0.94
7.6
0.8
56
1.6
ms
mS
V
Error Amplifier Transconductance
PSM Skip Threshold
GMEAO
PSMSKIP
CEAIN_INT
ROUT
EAIN Capacitance, Internal
Error Amplifier Output Impedance
Internal Compensation Capacitor
Internal Compensation Resistor
pF
[b]
1
MΩ
pf
CHF
56
5
RZI
kΩ
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3”
dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
ZVS Regulators
Page 16 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5VOUT) Electrical Characteristics (Cont.)
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
18
18
18
20
20
20
2
4
6
8
10
Load Current (A)
24V
12
14
16
18
18
18
20
20
20
VIN:
14V
42V
VIN:
14V
42V
Figure 29 — System efficiency, nominal trim,
Figure 32 — System power dissipation, nominal trim,
board temperature = 25°C
board temperature = 25°C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
2
4
6
8
10
Load Current (A)
24V
12
14
16
VIN:
14V
42V
VIN:
14V
42V
Figure 30 — System efficiency, low trim,
Figure 33 — System power dissipation, low trim,
board temperature = 25°C
board temperature = 25°C
97
11
10
9
96
95
94
93
92
91
90
89
88
87
8
7
6
5
4
86
85
84
83
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
2
4
6
8
10
Load Current (A)
24V
12
14
16
VIN:
14V
42V
VIN:
14V
42V
Figure 31 — System efficiency, high trim,
Figure 34 — System power dissipation, high trim,
board temperature = 25°C
board temperature = 25°C
ZVS Regulators
Page 17 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5VOUT) Electrical Characteristics (Cont.)
96
95
94
93
92
91
90
89
88
87
86
85
84
83
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
18
18
18
20
20
20
2
4
6
8
10
Load Current (A)
24V
12
14
16
18
18
18
20
20
20
VIN:
14V
42V
VIN:
14V
42V
Figure 35 — System efficiency, nominal trim,
Figure 38 — System power dissipation, nominal trim,
board temperature = 90°C
board temperature = 90°C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
2
4
6
8
10
Load Current (A)
24V
12
14
16
VIN:
14V
42V
VIN:
14V
42V
Figure 36 — System efficiency, low trim,
Figure 39 — System power dissipation, low trim,
board temperature = 90°C
board temperature = 90°C
97
11
10
9
96
95
94
93
92
91
90
89
88
87
8
7
6
5
4
86
85
84
83
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
2
4
6
8
10
Load Current (A)
24V
12
14
16
VIN:
14V
42V
VIN:
14V
42V
Figure 37 — System efficiency, high trim,
Figure 40 — System power dissipation, high trim,
board temperature = 90°C
board temperature = 90°C
ZVS Regulators
Page 18 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5VOUT) Electrical Characteristics (Cont.)
97
10
9
8
7
6
5
4
3
2
1
0
95
93
91
89
87
85
83
81
2
4
6
8
10
Load Current (A)
24V
12
14
16
18
18
18
20
20
20
2
4
6
8
10
Load Current (A)
24V
12
14
16
18
18
18
20
20
20
VIN:
14V
42V
VIN:
14V
42V
Figure 41 — System efficiency, nominal trim,
Figure 44 — System power dissipation, nominal trim,
board temperature = –40°C
board temperature = –40°C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
2
4
6
8
10
Load Current (A)
24V
12
14
16
VIN:
14V
42V
VIN:
14V
42V
Figure 42 — System efficiency, low trim,
Figure 45 — System power dissipation, low trim,
board temperature = –40°C
board temperature = –40°C
97
11
10
9
96
95
94
93
92
91
90
89
88
87
8
7
6
5
4
86
85
84
83
3
2
1
2
4
6
8
10
Load Current (A)
24V
12
14
16
2
4
6
8
10
Load Current (A)
24V
12
14
16
VIN:
14V
42V
VIN:
14V
42V
Figure 43 — System efficiency, high trim,
Figure 46 — System power dissipation, high trim,
board temperature = –40°C
board temperature = –40°C
ZVS Regulators
Page 19 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5VOUT) Electrical Characteristics (Cont.)
CH1
CH2
CH2
CH1
CH1 VOUT: 500mV/div
CH2 IIN: 1A/div
Timebase: 4ms/div
CH1 IOUT: 5A/div
CH2 VOUT: 200mV/div
Timebase: 200µs/div
Figure 47 — Transient response: 50 – 100% load, at 1A/µs.
nominal line, nominal trim,
Figure 50 — Output short circuit, nominal line
COUT = 12 x 47µF ceramic
CH1
CH1
CH1 VOUT: 20mV/div
Timebase: 2µs/div
CH1 VOUT: 20mV/div
Timebase: 2µs/div
Figure 48 — Output voltage ripple: nominal line, nominal trim,
Figure 51 — Output voltage ripple: nominal line, nominal trim,
100% load, COUT = 12 x 47µF ceramic
50% load, COUT = 12 x 47µF ceramic
625
600
575
550
525
500
475
450
425
400
375
350
22
20
18
16
14
12
10
8
6
4
2
0
Notes:
1. SiP is based on VS1 and VIN paths only.
2. Inductor is based on two leads and base
with inclusion of GEL 30 interface
resistance (0.15mm thick; 3.5W/m-K
thermal conductivity).
325
300
0
2
4
6
8
10
12
14
16
18
20
20
40
60
80
100
120
Load Current (A)
Temperature of Isothermal PCB (ºC)
24V
VIN:
14V
42V
Figure 49 — Switching frequency vs. load, nominal trim
Figure 52 — System thermal specified operating area: max IOUT at
nominal trim vs. temperature at locations noted
ZVS Regulators
Page 20 of 36
Rev 1.6
02/2021
PI332x-00
PI3325-00 (5VOUT) Electrical Characteristics (Cont.)
20
18
16
14
12
10
8
CH1
CH2
CH3
CH4
6
4
2
0.8
1.2
VIN
1.6
2
2.4
2.8
VEAO (V)
CH1 VIN: 10V/div
CH2 TRK: 2V/div
CH3 VOUT: 2V/div Timebase: 2.00ms/div
CH4 EN: 2V/div
24V
:
14V
42V
Figure 53 — Output current vs. VEAO, nominal trim
Figure 56 — Start up from VIN applied, nominal line, nominal trim,
typical timing, PI3325 shown
20
18
16
14
12
10
8
CH1
CH2
CH3
CH4
6
4
2
0.8
1.2
VIN
1.6
2.0
2.4
2.8
VEAO (V)
CH1 VIN: 10V/div
CH2 TRK: 2V/div
CH3 VOUT: 2V/div
Timebase: 400µs/div
24V
:
14V
42V
CH4 PWRGD: 2V/div
Figure 54 — Small signal modulator gain vs. VEAO, nominal trim
Figure 57 — Start up from EN, VIN pre-applied, nominal line,
nominal trim, typical timing, PI3325 shown
50
45
40
35
30
25
20
15
10
5
0
0.8
1.2
VIN
1.6
2.0
2.4
2.8
VEAO (V)
24V
:
14V
42V
Figure 55 — rEQ_OUT vs VEAO, nominal trim
ZVS Regulators
Page 21 of 36
Rev 1.6
02/2021
PI332x-00
Soft Start
Functional Description
The PI332x-00 includes an internal soft-start capacitor to
control the rate of rise of the output voltage. See the Electrical
Characteristics Section for the default value. Connecting an
external capacitor from the TRK pin to SGND will increase the
start-up ramp period. See, “Soft Start Adjustment and Track,” in
the Applications Description section for more details.
The PI332x-00 is a family of highly integrated ZVS Buck regulators.
The PI332x-00 has an output voltage that can be set within a
prescribed range shown in Table 1. Performance and maximum
output current are characterized with a specific external power
inductor (see Table 3).
Output Voltage Selection
The PI332x-00 output voltage is set with REA1 and REA2 as shown
in Figure 58. Table 1 defines the allowable operational voltage
ranges for the PI332x-00 family. Refer to the Output Voltage Set
Point Application Description for details.
L1
VIN
VS1
VOUT
VSP
VIN
VOUT
CIN
COUT
ZVS Buck
PGND
VDR
VSN
SYNCO
SYNCI
PWRGD
EN
VDIFF
TRK
REA1
REA2
EAIN
EAO
Output Voltage
Device
TESTx
SGND
COMP
Nominal
Range
CCOMP
PI3323-00-BGIZ
PI3325-00-LGIZ
3.3V
2.2 – 4.0V
4.0 – 6.5V
5.0V
Table 1 — PI332x-00 family output voltage ranges
Figure 58 — ZVS Buck with required components
For basic operation, Figure 58 shows the connections and
Output Current Limit Protection
The PI332x-00 has a current limit protection, which prevents
the output from sourcing current higher than the regulator’s
maximum rated current. If the output current exceeds the Current
Limit (IOUT_CL) for 1024μs, a slow current limit fault is initiated and
the regulator is shutdown which eliminates output current flow.
After Fault Restart Delay (tFR_DLY), a soft-start cycle is initiated.
This restart cycle will be repeated indefinitely until the excessive
load is removed.
components required. No additional design or settings are required.
ENABLE (EN)
EN is the enable pin of the converter. The EN Pin is referenced to
SGND and permits the user to turn the regulator on or off. The
EN default polarity is a positive logic assertion. If the EN pin is
left floating or asserted high, the converter output is enabled.
Pulling EN pin below VEN_LO with respect to SGND will disable the
regulator output.
The PI332x-00 also has short circuit protection which can rapidly
stop switching to protect against catastrophic failure of an external
component such as a saturated inductor. If short-circuit protection
is triggered the PI332x-00 will complete the current cycle and stop
switching. The module will attempt to soft start after Fault Restart
Delay (tFR_DLY).
Remote Sensing
If remote sensing is required, the PI332x-00 product family is
equipped with a general purpose op-amp. This amplifier can allow
full differential remote sense by configuring it as a differential
follower and connecting the VDIFF pin to the EAIN pin.
Input Undervoltage Lockout
If VIN falls below the input Undervoltage Lockout (UVLO) threshold,
but remains high enough to power the internal bias supply, the
PI332x-00 will complete the current cycle and stop switching. The
system will soft start once the input voltage is reestablished and
after the Fault Restart Delay.
ZVS Regulators
Page 22 of 36
Rev 1.6
02/2021
PI332x-00
Input Overvoltage Lockout
Pulse Skip Mode (PSM)
If VIN exceeds the input Overvoltage Lockout (OVLO) threshold
(VOVLO), while the controller is running, the PI332x-00 will
complete the current cycle and stop switching. If VIN remains above
OVLO for at least tFR_DLY, then the input voltage is considered
reestablished once VIN goes below VOVLO-VOVLO_HYS. If VIN goes
below OVLO before tFR_DLY elapses, then the input voltage is
considered reestablished once VIN goes below VOVLO. The system
will soft start once the input voltage is reestablished and after the
Fault Restart Delay.
PI332x-00 features a Pulse Skip Mode (PSM) to achieve high
efficiency at light loads. The regulators are set up to skip pulses
if EAO falls below a PSM threshold (PSMSKIP). Depending on
conditions and component values, this may result in single pulses
or several consecutive pulses followed by skipped pulses. Skipping
cycles significantly reduces gate drive power and improves light
load efficiency. The regulator will leave PSM once the EAO rises
above the Pulse Skip Mode threshold.
Variable Frequency Operation
Output Overvoltage Protection
Each PI332x-00 is preprogrammed to a base operating frequency,
with respect to the power stage inductor (see Table 2), to operate
at peak efficiency across line and load variations. At low-line
and high-load applications, the base frequency will decrease to
accommodate these extreme operating ranges. By stretching the
frequency, the ZVS operation is preserved throughout the total
input line voltage range therefore maintaining optimum efficiency.
The PI332x-00 family is equipped with output Overvoltage
Protection (OVP) to prevent damage to input voltage sensitive
devices. If the output voltage exceeds VOVP-REL or VOVP-ABS, the
regulator will complete the current cycle and stop switching. The
system will resume operation once the output voltage falls below
the OVP threshold and after Fault Restart Delay.
Overtemperature Protection
Thermal Characteristics
The PI332x features an overtemperature protection (OTP), which
will not engage until after the product is operated above the
maximum rated temperature. The OTP circuit is only designed to
protect against catastrophic failure due to excessive temperatures
and should not be relied upon to ensure the device stays within
the recommended operating temperature range. Thermal shut
down terminates switching and discharges the soft-start capacitor.
The PI332x will restart after the excessive temperature has
decreased by 30°C.
Figure 59(a) and 59(c) thermal impedance models that can predict
the maximum temperature of the hottest component for a given
operating condition. This model assumes that all customer PCB
connections are at one temperature, which is PCB equivalent
Temperature TPCB °C.
The SiP model can be simplified as shown in Figure 59(b). which
assumes all PCB nodes are at the same temperature.
ZVS Regulators
Page 23 of 36
Rev 1.6
02/2021
PI332x-00
Maximum SiP Internal Temperature
INT ( oC )
T
Thermal Resistance
SiP Case Top
Thermal Resistances
θINT-VIN
oC / W
θINT-VS1
oC / W
θINT-PGND1
oC / W
θINT-PGND2
oC / W
θINT-SGND
oC / W
SiP PCB Pads
SiP Power
Dissipaꢁon
PDSiP (W)
θINT-TOP oC / W
SiP Case Top
Temperature
TTOP oC
TVS1
oC
TPGND2
oC
TVIN
oC
TPGND1
oC
TSGND
oC
SiP PCB Pad
Temperatures
(a)
Maximum SiP Internal Temperature
TINT ( oC )
Thermal Resistance
Thermal Resistance
SiP Case Top
SiP PCB Equivalent
SiP Power
Dissipaꢀon
PDSIP (W)
θINT-PCB oC / W
θINT-TOP oC / W
SiP PCB Common
Temperature
TPCB oC
Case Top
Temperature
TTOP oC
(b)
Maximum Inductor Internal Temperature
TINT ( oC )
Thermal Resistance
Inductor Case Top
θINT-TOP oC / W
Thermal Resistance
Inductor Case Boꢀom
θINT-BOTTOM oC / W
Thermal Resistances
Inductor PCB Pads
θINT-LEAD1
oC / W
θINT-LEAD2
θINT-TAB
oC / W
oC / W
Inductor Power
Dissipaꢀon
PDIND (W)
Inductor Case Top
Temperature
TTOP oC
Inductor Case Boꢀom
Temperature
TVOUT
oC
TVS1
oC
Inductor PCB Pad
Temperatures
TTAB
oC
TBOTTOM oC
(c)
Figure 59 — PI332x-00 thermal model (a), SiP simplified version (b) and inductor thermal model (c)
ZVS Regulators
Page 24 of 36
Rev 1.6
02/2021
PI332x-00
Where the symbol in Figure 59(a) and (b) is defined as the following:
θINT-TOP the thermal impedance from the hottest component inside the SiP to the top side
the thermal impedance from the hottest component inside the SiP to the customer PCB, assuming all pins are
θINT-PCB
at one temperature.
θINT-VIN
the thermal impedance from the hottest component inside the SiP to the circuit board VIN pads.
θINT-VS1
the thermal impedance from the hottest component inside the SiP to the circuit board VS1 pads.
the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND1 pads.
PGND1 is pins 12A-K.
θINT-PGND1
θINT-PGND2
θINT-SGND
the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND2 pads .
PGND2 is pins 2F-J, 3F-J, 4C-J, 5B-J and 6C-K.
the thermal impedance from the hottest component inside the SiP to the circuit board at the SGND pads.
Where the symbol in Figure 59(c) is defined as the following:
θINT-TOP the thermal impedance from the hot spot to the top surface of the core.
θINT-BOT
the thermal impedance from the hot spot to the bottom surface of the core.
θINT-TAB
the thermal impedance from the hot spot to the metal mounting tab on the core body, if applicable.
the thermal impedance from the hot spot to one of the mounting leads.
Since the leads are the same thermal impedance, there is no need to specify by explicit pin number.
θINT-LEAD1
θINT-LEAD2
the thermal impedance from the hot spot to the other mounting lead.
The following equation can predict the junction temperature
based on the heat load applied to the SiP and the known ambient
conditions with the simplified thermal circuit model:
TTOP
TPCB
θINT-PCB
1
PD +
+
θINT-TOP
TINT
=
(1)
1
+
θINT-TOP
θINT-PCB
Simplified SiP
Thermal Impedances
Detailed SiP Thermal Impedances
Product
System
θINT-TOP
θINT-PCB
θINT-TOP
θINT-VIN
θINT-VS1
θINT-PGND1
θINT-PGND2
θINT-SGND
(°C / W)
(°C / W)
(°C / W)
(°C / W)
(°C / W)
(°C / W)
(°C / W)
(°C / W)
PI332x-00
1.7
110
3.4
4.8
33
33
91
110
Table 2 — PI332x-00 SiP thermal impedance
Effective Thermal Impedances
Inductor Part
Number
Product
System
θINT-LEAD1, θINT-LEAD2
θINT-TAB
(°C / W)
θINT-TOP
θINT-BOTTOM
(°C / W)
(°C / W)
(°C / W)
PI332x-00
FP2207R1-R230-R
11
9.4
6.8
N/A
Table 3 — Inductor effective thermal model parameters
ZVS Regulators
Page 25 of 36
Rev 1.6
02/2021
PI332x-00
SiP Power Dissipation as Percentage of Total System Losses
100
90
80
70
60
50
14
18
22
26
30
34
38
42
VIN (V)
IOUT
:
<5% Rated Load
30% Rated Load
100% Rated Load
Figure 60 — PI3323-00-LGIZ
100
90
80
70
60
50
40
14
18
22
26
30
34
38
42
VIN (V)
IOUT
:
<5% Rated Load
30% Rated Load
100% Rated Load
Figure 61 — PI3325-00-LGIZ
ZVS Regulators
Page 26 of 36
Rev 1.6
02/2021
PI332x-00
There is typically either proportional or direct tracking implemented
within a design. For proportional tracking between several
Application Description
regulators at start up, simply connect all PI332x-00 device TRK pins
together. This type of tracking will force all connected regulators to
start up and reach regulation at the same time (see Figure 63a).
Output Voltage Set Point
The PI332x-00 family of buck regulators utilizes VREF, an internal
reference for regulating the output voltage. The output voltage
setting is accomplished using external resistors as shown in
Figure 62. Select R2 to be at or around 1kΩ for best noise
immunity. Use Equations 2 and 3 to determine the proper value
based on the desired output voltage.
VOUT
1
V
OUT 2
(a)
Parent VOUT
VOUT
VOUT
2
R1
(b)
t
EAIN
CEAIN-INT
-
+
VREF
R2
EAO
Figure 63 — PI332x-00 tracking responses
CHF
RZI
COMP
For Direct Tracking, choose the PI332x-00 with the highest output
voltage as the parent and connect the parent to the TRK pin of the
other PI332x-00 regulators through a divider (Figure 64) with the
same ratio as the child’s feedback divider.
Figure 62 — External resistor divider network
R1 + R2
VOUT = VREF
R1 = R2 •
•
(2)
(3)
Parent VOUT
R2
V
OUT – VREF
VREF
R1
PI332x
TRK
Child
R2
where VREF = VEAIN
SGND
Soft Start Adjust and Tracking
The TRK pin offers a means to increase the regulator’s soft-start
time or to track with additional regulators. The soft-start slope is
controlled by an internal capacitor and a fixed charge current to
provide a Soft-Start Time tSS for all PI332x-00 regulators. By adding
an additional external capacitor to the TRK pin, the soft-start
time can be increased further. The following equation can be
used to calculate the proper capacitor for a desired soft-start time
in excess of tSS:
Figure 64 — Voltage divider connections for direct tracking
All connected PI332x-00 regulator soft-start slopes will track with
this method. Direct tracking timing is demonstrated in Figure 63b.
All tracking regulators should have their Enable (EN) pins connected
together to work properly.
CTRK = (tTRK • ITRK )– CTRK_INT
(4)
where tTRK is the soft-start time and ITRK is a 50µA internal charge
current (see Electrical Characteristics for limits).
In applications such as battery or super-capacitor charging where
the load is pre-biased, the PI332x can start into output voltages up
to the externally applied trim setpoint, or the minimum absolute
OVP, provided the value does not exceed 6V. For start up into
loads which are pre-biased above 6V, an ORing FET or equivalent
sub-circuit is required to decouple the buck output from the
load during start up. In any application with a CV type load,
the regulator must be configured in a constant-current mode of
operation; the built-in current limit is a fault protection only.
ZVS Regulators
Page 27 of 36
Rev 1.6
02/2021
PI332x-00
Inductor Pairing
Parallel Operation
Multiple PI332x-00 can be connected in parallel to increase the
output capability of a single output rail. When connecting modules
in parallel, each EAO, TRK and EN pin should be connected
together. EAIN pins should remain separated, each with an REA1
and REA2, to reject noise differences between different modules'
SGND pins. Current sharing will occur automatically in this manner
so long as each inductor is the same value. Refer to the Electrical
Characteristics table for maximum array size and array rated
output current. Current sharing may be considered independent
of synchronization and/or interleaving. Modules do not have to be
interleaved or synchronized to share current.
The PI332x-00 utilizes an external inductor. This inductor has
been optimized for maximum efficiency performance. Table 3
details the specific inductor value and part number utilized for
each PI332x-00.
Product
System
Value
(nH)
Max Operating
Temp (°C)
MFR
Part Number
Eaton
Pulse
Eaton
Pulse
FP2207R1-R230-R
PA4792.231HLT
FP2207R1-R230-R
PA4792.231HLT
PI3323-00
PI3325-00
230
230
125
125
Due to the high output current capability of a single module and
Critical Conduction Mode (CrCM) occurring at approximately 50%
rated load, interleaving is not supported.
Table 3 — PI332x-00 Inductor pairing
Use of the PI332x-00 SYNCI pin is practical only under a limited
set of conditions. Synchronizing to another converter or to a fixed
external clock source can result in a significant reduction in output
power capability or higher than expected ripple.
The same inductor model may have different effective thermal
impedances, depending on the model ZVS Buck paired with it. The
thermal impedances are used in a virtual model of the inductor
to estimate the maximum temperature, and the location of the
maximum temperature may vary depending on the ZVS Buck
model that the inductor is used with. This is because the effective
thermal impedances are not only based on the geometry and
materials used in the inductor, but include how the inductor power
dissipation is distributed among core losses, DC copper losses and
AC copper losses. This distribution is dependent on the ZVS Buck
model that uses the inductor.
Filter Considerations
The PI332x-00 requires low impedance ceramic input capacitors
(X7R/X5R or equivalent) to ensure proper start up and
high-frequency decoupling for the power stage. The PI332x-00
will draw nearly all of the high-frequency current from the
low-impedance ceramic capacitors when the main high-side
MOSFET(s) are conducting. During the time the MOSFET(s) are off,
the input capacitors are replenished from the source. Table 6 shows
the recommended input and output capacitors to be used for the
PI332x-00 as well as per capacitor RMS ripple current and the input
and output ripple voltages. Table 5 lists the recommended input
and output ceramic capacitors manufacturer and part numbers. It
is very important to verify that the voltage supply source as well as
the interconnecting lines are stable and do not oscillate.
L1_1
VIN
VS1
VOUT
VSP
VSN
VDIFF
TRK
EAIN
EAO
COMP
VIN
EN
VOUT
CIN_1
COUT_1
ZVS Buck
#1
PGND
VDR
SYNCO
SYNCI
PWRGD
EN
REA1_1
REA2_1
TRK
EAO
TESTx
SGND
CCOMP_1
Input filter case 1 — Inductive source and local, external,
input decoupling capacitance with negligible ESR
(i.e., ceramic type):
L1_2
VIN
VS1
VOUT
VSP
VSN
VDIFF
TRK
EAIN
EAO
COMP
VIN
EN
VOUT
CIN_2
COUT_2
ZVS Buck
PGND
VDR
SYNCO
SYNCI
PWRGD
EN
The voltage source impedance can be modeled as a series
RLINE LLINE circuit. The high performance ceramic decoupling
capacitors will not significantly damp the network because of their
low ESR; therefore in order to guarantee stability the following
conditions must be verified:
#2
REA1_2
REA2_2
TRK
EAO
TESTx
SGND
CCOMP_2
LLINE
RLINE
>
(5)
Figure 65 — PI332x-00 parallel operation
CIN_INT + CIN_EXT • rEQ_IN
(
)
RLINE << rEQ_IN
(6)
Where rEQ_IN can be calculated by dividing the lowest line voltage
by the full load input current. It is critical that the line source
impedance be at least an octave lower than the converter’s
dynamic input resistance, Equation 6. However, RLINE cannot
be made arbitrarily low otherwise Equation 5 is violated and
the system will show instability, due to an under-damped
RLC input network.
ZVS Regulators
Page 28 of 36
Rev 1.6
02/2021
PI332x-00
Input filter case 2 — Inductive source and local, external
input decoupling capacitance with significant RCIN_EXT ESR
(i.e., electrolytic type):
2. No direct connection is allowed. Any noise source that can
disturb the VDR voltage can also affect the internal controller
operation. A series impedance is required between the VDR pin
and any external circuitry.
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor LLINE
.
3. All loads must be locally decoupled using a 0.1μF ceramic
capacitor. This capacitor must be connected to the VDR output
through a series resistor no smaller than 1kΩ, which forms a
low-pass filter.
Notice that the high performance ceramic capacitors CIN_INT within
the PI332x-00 should be included in the external electrolytic
capacitance value for this purpose. The stability criteria will be:
Additional System Design Considerations
rEQ_IN > RC
(7)
1. Inductive loads: As with all power electronic applications,
consideration must be given to driving inductive loads that
may be exposed to a fault in the system which could result
in consequences beyond the scope of the power supply
primary protection mechanisms. An inductive load could be a
filter, fan motor or even excessively long cables. Consider an
instantaneous short circuit through an un-damped inductance
that occurs when the output capacitors are already at an
initial condition of fully charged. The only thing that limits the
current is the inductance of the short circuit and any series
resistance. Even if the power supply is off at the time of the
short circuit, the current could ramp up in the external inductor
and store considerable energy. The release of this energy will
result in considerable ringing, with the possibility of ringing
nodes connected to the output voltage below ground. The
system designer should plan for this by considering the use of
other external circuit protection such as load switches, fuses
and transient voltage protectors. The inductive filters should
be critically damped to avoid excessive ringing or damaging
voltages. Adding a high-current Schottky diode from the output
voltage to PGND close to the PI332x-00 is recommended for
these applications.
IN_EXT
LLINE
< rEQ_IN
(8)
CIN_INT • RC
IN_EXT
Equation 8 shows that if the aggregate ESR is too small – for
example by using very high quality input capacitors (CIN_EXT) – the
system will be under-damped and may even become destabilized.
As noted, an octave of design margin in satisfying Equation 7
should be considered the minimum. When applying an electrolytic
capacitor for input filter damping the ESR value must be chosen to
avoid loss of converter efficiency and excessive power dissipation in
the electrolytic capacitor.
VDR Bias Regulator
The VDR internal bias regulator is a ZVS switching regulator
that resides internal to the PI332x-00 SiP. It is intended primarily
to power the internal controller and driver circuitry. The power
capability of this regulator is sized for the PI332x-00, with adequate
reserve for the application it was intended for.
It may be used for as a pullup source for open collector applications
and for other very low power uses with the following restrictions:
2. Low-voltage operation: There is no isolation from an SELV
(Safety-Extra-Low-Voltage) power system. Powering low voltage
loads from input voltages as high as 60V may require additional
consideration to protect low voltage circuits from excessive
voltage in the event of a short circuit from input to output. A
fast TVS (transient voltage suppressor) gating an external load
switch is an example of such protection.
1. The total external loading on VDR must be less than IVDR
.
Manufacturer
Murata
Part Number
Value
47µF
Description
GRM32ER71A476KE15
GRM32ER71A476K
47μF 10V 1210 X7R
4.7μF 80V 1210 X7R
100μF 6.3V 1210 X7S
Murata
4.7µF
100µF
Murata
GRM32EC70J107ME15K
Table 5 — Recommended input and output capacitor components
Transient
CIN
Ripple
Current
COUT
Ripple
Current
(IRMS)
Load
Step
(% Rating)
(1A/µs)
Load
Current
(A)
VIN
Ripple
(mVpp)
VOUT
Ripple
(mVpp)
Deviation
Excluding
Ripple
VOUT
Recovery
Time (µs)
Product
CIN
COUT
(IRMS
)
(mVpk)
8 x
4.7µF
PI3323-00
PI3325-00
22
20
8 x 100µF
12 x 47µF
10.85
10.43
14.5
540
512
67
50 – 100
50 – 100
110
90
<90
<80
6 x
4.7µF
13.25
55.7
Table 6 — Recommended input and output capacitor quantity and performance at nominal line, nominal trim.
ZVS Regulators
Page 29 of 36
Rev 1.6
02/2021
PI332x-00
Layout Guidelines
To optimize maximum efficiency and low noise performance
from a PI332x-00 design, layout considerations are necessary.
Reducing trace resistance and minimizing high-current loop
returns along with proper component placement will contribute to
optimized performance.
VIN
CIN
A typical buck converter circuit is shown in Figure 66. The potential
areas of high parasitic inductance and resistance are the circuit
return paths, shown as LR below.
COUT
Figure 68 — Current flow: Q2 closed
Figure 69 illustrates the tight path between CIN and COUT (and VIN
and VOUT) for the high AC return current. The PI332x-00 evaluation
board uses a layout optimized for performance in this way.
VIN
CIN
COUT
Figure 66 — Typical buck regulator
The path between the COUT and CIN capacitors is of particular
importance since the AC currents are flowing through both of
them when Q1 is turned on. Figure 67, schematically, shows the
reduced trace length between input and output capacitors. The
shorter path lessens the effects that copper trace parasitics can
have on the PI332x-00 performance.
PGND
VOUT
Inductor
VS1
ZVS-
Buck
SIP
VIN
PGND
VIN
CIN
COUT
Figure 69 — Recommended layout for optimized AC current
within the SiP, inductor and ceramic input and
output capacitors
Figure 67 — Current flow: Q1 closed
When Q1 is on and Q2 is off, the majority of CIN’s current is used
to satisfy the output load and to recharge the COUT capacitors.
When Q1 is off and Q2 is on, the load current is supplied by the
inductor and the COUT capacitor as shown in Figure 68. During this
period CIN is also being recharged by the VIN. Minimizing CIN loop
inductance is important to reduce peak voltage excursions when
Q1 turns off. Also, the difference in area between the CIN loop and
COUT loop is vital to minimize switching and GND noise.
ZVS Regulators
Page 30 of 36
Rev 1.6
02/2021
PI332x-00
LGA Recommended PCB Footprint and Stencil
E1
D1
L
D1
E1
L
Recommended receiving footprint for PI332x-00 10 x 14mm package. All pads should have a final copper size of 0.55 x 0.55mm,
whether they are solder-mask defined or copper defined, on a 1 x 1mm grid. All stencil openings are 0.45mm when using either a 5mil or
6mil stencil.
ZVS Regulators
Page 31 of 36
Rev 1.6
02/2021
PI332x-00
LGA Package Drawings
E1
A
K
G
E
D
A
1
2
3
4
5
6
7
D
D1
8
9
1
10
11
12
13
14
E
DETAIL B
1
DETAIL A
M
A
L
M
2
L1
M
M
A
3
A2
A
DETAIL B
SEATING PLANE
METALLIZED
PAD
A1
SOLDER MASK
DETAIL A
A
A1
A2
L
D
E
AND POSITION
D1
E1
L1
ZVS Regulators
Page 32 of 36
Rev 1.6
02/2021
PI332x-00
BGA Recommended PCB Footprint and Stencil
E1
e
PIN 1
e
b
D1
FOR PCB LAND PATTERN
BB 10.5x14.5mm SiP
DIMENSIONSAL REFERENCES
REF.
b
MIN.
0.59
NOM.
0.64
MAX.
0.69
D1
E1
e
13.00 BSC.
9.00 BSC.
1.00 BSC.
ZVS Regulators
Page 33 of 36
Rev 1.6
02/2021
PI332x-00
BGA Package Drawings
A
K
J H G F E D C B A
PIN 1 INDEX
CORNER
DETAIL B
1
2
3
PIN 1 INDEX
CORNER
4
5
6
D
7
8
D1
9
10
11
12
13
14
2
e
e
2
E
B
(4X)
aaa C
E1
BUMPS UP VIEW
BUMPS DOWN VIEW
4
nX Øb
DETAIL A
M
0.25
C
A B
M
0.1
C
e
DETAIL B
A3
bbb
C
DIMENSIONAL REFERENCES
REF.
A
A1
A3
D
D1
E
MIN.
2.96
0.44
1.95
NOM.
3.05
MAX.
3.14
0.54
2.05
0.49
A
C
2.00
14.50
13.00 BSC
10.50
9.00 BSC
0.64
6
SEATING PLANE
E1
b
A1
0.59
0.69
DETAIL DETAIL A
SCALE 25 : 1
aaa
bbb
ddd
e
MD/ME
n
0.20
0.25
5
ddd
C
0.15
1.00 BSC
14/10
110
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. 'e' REPRESENTS THE BASIC SOLDER BALL GRID PITCH.
3. 'M' REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE.
AND SYMBOL 'n' IS THE NUMBER OF BALLS AFTER DEPOPULATING.
4. 'b' IS MEASURABLE AT THE MAXIMUM SOLDER BALL DIAMETER AFTER REFLOW
PARALLEL TO PRIMARY DATUM
5. DIMENSION 'ddd' IS MEASURED PARALLEL TO PRIMARY DATUM
6. PRIMARY DATUM AND SEATING PLANE ARE DEFINED BY THE SPERICAL
CROWNS OF THE SOLDER BALLS.
C
.
C
.
C
7. THE OVERALL PACKAGE THICKNESS "A" ALREADY CONSIDERS COLLAPSE BALLS
8. DIMENSIONING AND TOLERANCING PER ASME Y14.5M 1994.
9. REFERENCE TO JEDEC MO-234B.
10.RoHS COMPLIANT PER CST-0001 LATEST REVISION.
ZVS Regulators
Page 34 of 36
Rev 1.6
02/2021
PI332x-00
Revision History
Revision
1.0
Date
Description
Page Number(s)
12/05/17
02/06/18
Initial release
n/a
14
1.1
Added typical start-up waveforms
Updated figure 28
Removed note
14
20
1.2
1.3
07/25/19
04/17/20
Added PI3323-00 part numbers, and BGIZ, BGMZ, BGMP options
Updated PI3325 enabled input quiescent current
Added BGA drawings
1, 3, 8 – 14, 22, 26, 28, 29
8
33, 34
1.4
1.5
1.6
06/22/20
08/12/20
02/22/21
Updated to add recommended Pulse Electronics inductor
Updated terminology
28
27
Updated to include PI3323-00-LGMZ, PI3325-00-LGMZ
1, 3, 7, 8, 9, 15, 16
Please note: Pages added in Rev 1.3.
ZVS Regulators
Page 35 of 36
Rev 1.6
02/2021
PI332x-00
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accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor
makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves
the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by
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Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Visit http://www.vicorpower.com/dc-dc-converters-board-mount/cool-power-pi33xx-and-pi34xx for the latest product information.
Vicor’s Standard Terms and Conditions and Product Warranty
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, and Product Warranty which are available on Vicor’s webpage
(http://www.vicorpower.com/termsconditionswarranty) or upon request.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used
herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to
result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms
and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemnifies
Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property
rights is granted by this document. Interested parties should contact Vicor’s Intellectual Property Department.
The products described on this data sheet are protected by U.S. Patents. Please see www.vicorpower.com/patents for the latest
patent information.
Contact Us: http://www.vicorpower.com/contact-us
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
www.vicorpower.com
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
©2017 – 2021 Vicor Corporation. All rights reserved. The Vicor name is a registered trademark of Vicor Corporation.
All other trademarks, product names, logos and brands are property of their respective owners.
ZVS Regulators
Page 36 of 36
Rev 1.6
02/2021
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