PRM48BH480M250A00 [VICOR]
PRM⢠Regulator; PRMA ?? ¢稳压器
| 型号： | PRM48BH480M250A00 |
| 厂家： | 
VICOR CORPORATION |
| 描述： | PRM⢠Regulator |
| 文件： | 总44页 (文件大小：1343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRM48BH480 250A00
PRM™ Regulator
FEATURES
48V input (38V to 55V), non‐isolated ZVS buck‐boost regulator
20V to 55V adjustable output range
250W output power in 0.57in2 footprint
96.7% typical efficiency, at full load
1670 W/in3 (102 W/cm3) Power Density
5.28 MHrs MTBF (MIL‐HDBK‐217Plus Parts Count)
Pin selectable operating mode
Adaptive Loop
Remote Sense / Slave
Half VIChip Package
22.0mm x 16.5mm x 6.73mm
TYPICAL APPLICATIONS
PRODUCT RATINGS
High Density Power Supply DC-DC rail outputs
High Density ATE system DC-DC power
Telecom NPU and ASIC core power
Communications Systems
VIN = 38V to 55V
POUT = 250W
IOUT = 5.21A
VOUT= 48V
(20V to 55V Trim)
Non-isolated and isolated power converters
DESCRIPTION
The VIChip™ PRM™ Regulator is a high efficiency converter, operating from a 38 to 55 Vdc input to generate a regulated
20 to 55 Vdc output. The ZVS buck – boost topology enables high switching frequency (~1.03 MHz) operation with high
conversion efficiency. High switching frequency reduces the size of reactive components enabling power density up to
1670 W/in3.
The Half VIChip package is compatible with standard pick-and-place and surface mount assembly processes with a planar
thermal interface area and superior thermal conductivity.
In a Factorized Power Architecture™ system, the PRM and downstream VTM™ current multiplier minimize distribution and
conversion losses in a high power solution, providing an isolated, regulated output voltage.
The PRM48BH480[x]250A00 has two selectable modes of regulation depending on the application requirements.
In Adaptive Loop operation, the PRM48BH480[x]250A00 utilizes a unique feed-forward scheme that enables precise regulation
of an isolated POL voltage without the need for remote sensing and voltage feedback.
In Remote Sense operation, the internal regulation circuitry is disabled, and an external control loop and current sensor
maintain regulation. This affords flexibility in the design of both voltage and current compensation loops to optimize
performance in the end application.
Rev. 1.0
11/2012
- 1 -
PRM48BH480 250A00
TYPICAL APPLICATIONS
PRM
ENABLE
TRIM
VAUX
VTM
REF/
REF_EN
ON/OFF CONTROL
VOUT
VTM Startup Pulse
AL
VC
TM
PC
VC
VT
IFB
+OUT
Adaptive Loop Temperature Feedback
SGND
SHARE/
CONTROL NODE
RTRIM
RAL
COUT
SGND
VIN
38V to 55V
+IN
-IN
+OUT
-OUT
+IN
-IN
LF
VF: 20V to 55V
CIN
CF
-OUT
SGND
GND
PRIMARY
SECONDARY
SEC_GND
ISOLATION BOUNDRY
SGND
Typical Application: PRM48BH480[x]250A00 + VTM Adaptive Loop Configuration
Voltage Sense
VREF
IN
OUT
GND
SGND
VOLTAGE SENSE AND ERROR AMPLIFIER
(SINGLE ENDED)
PRM
ENABLE
TRIM
VAUX
SGND
VOLTAGE REFERENCE WITH SOFT START
REF/
REF_EN
VTM
ON/OFF CONTROL
VTM Startup Pulse
SGND
AL
VC
TM
PC
VC
VT
IFB
+OUT
VOUT
SHARE/
CONTROL NODE
SGND
V+
V-
VOUT
+IN
COUT
SGND
-IN
VIN
38V to 55V
+IN
-IN
+OUT
-OUT
+IN
-IN
LF
External Current Sense and Feedback
CIN
CF
-OUT
SECONDARY
SGND
GND
[1]
PRIMARY
GND
[1]
ISOLATION BOUNDRY
SGND
Typical Application: PRM48BH480[x]250A00 + VTM non-Isolated Remote Sense Configuration
[1] Non-Isolated Configuration: –Out connected to -IN
Rev. 1.0
11/2012
- 2 -
PRM48BH480 250A00
PIN CONFIGURATION
PIN DESCRIPTIONS
Pin
Signal Name
Type
Function
Number
SHARE
BIDIR
INPUT
INPUT
Parallel sharing control bus for master-Slave configuration.
(Adaptive Loop / Slave operation)
A1
A3
CONTROL NODE
(Remote Sense operation)
Modulator control node input. Driven by external error amplifier in Remote Sense
operation.
VT
VTM TM input for temperature compensation. Leave disconnected for Remote
Sense operation.
(Adaptive Loop operation)
B2
B4
C1
ENABLE
VAUX
BIDIR
OUTPUT
INPUT
Enables power supply when allowed to float high. 5.0V during normal operation.
9.0V auxiliary bias voltage.
TRIM
Selects operating mode. Adjusts output voltage in Adaptive Loop operation.
IFB
Current sense input for current limit and overcurrent protection in Remote Sense
operation. Leave disconnected for Adaptive Loop operation.
C3
INPUT
(Remote Sense operation)
D2
D4
E1
NC
SGND
NC
n/a
INPUT
n/a
Do not connect this pin.
Signal ground, reference for analog controls. Kelvin connected internally to –IN
and -OUT.
Do not connect this pin.
REF
OUTPUT
Reference voltage for internal error amplifier in Adaptive Loop operation.
(Adaptive Loop operation)
E3
F2
REF_EN
(Remote Sense operation)
Powers and enables external control circuit voltage reference in Remote Sense
operation.
OUTPUT
INPUT
AL
Adaptive Loop gain control. Sets the magnitude of the Adaptive Loop load line in
Adaptive Loop operation. Leave disconnected for Remote Sense operation.
(Adaptive Loop operation)
F4
VC
OUTPUT
Bias voltage to power VTM module during start up
Positive input power terminal
INPUT
POWER
G1,G2
+IN
OUTPUT
POWER
G3,G4
H1,H2
H3,H4
+OUT
-IN
Positive output power terminal
INPUT
POWER RETURN
Negative input power terminal. Connected internally to –OUT.
Negative output power terminal. Connected internally to -IN.
OUTPUT
POWER RETURN
-OUT
Rev. 1.0
11/2012
- 3 -
PRM48BH480 250A00
PART ORDERING INFORMATION
PART ORDERING INFORMATION
Output Voltage x 10 Temperature Grade
Input Voltage
Device Type
Package Type
Output Power Revision
Version
Range
PRM
48B
H
480
T
250
A
A
00
T = -40 to 125 °C
M = -55 to 125 °C
H = Half VIC
SMD
PRM = PRM
48B = 38V – 55V
480 = 48V
250 = 250W
00 = AL / RS
STANDARD MODELS
PART NUMBER
VIN
PACKAGE TYPE
VOUT
TEMPERATURE
-40 to 125 °C
POWER
VERSION
PRM48BH480T250A00
PRM48BH480M250A00
Half VIC
SMD
48V
(20V to 55V)
AL / RS
(Pin Selectable)
38V – 55V
250W
-55 to 125 °C
Rev. 1.0
11/2012
- 4 -
PRM48BH480 250A00
ABSOLUTE MAXIMUM RATINGS
The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions.
Operating beyond rated operating conditions for extended period of time may affect device reliability. All voltages are specified
relative to SGND unless otherwise noted. Positive pin current represents current flowing out of the pin.
ABSOLUTE MAXIMUM RATINGS
Parameter
Comments
Min
Max
Unit
-0.3
10.5
V
SHARE /
CONTROL NODE
………………………………………………………………………...........................................................................................................................................
+/- 10
mA
-0.3
-1
5.5
+/- 10
80
V
mA
V
ENABLE
………………………………………………………………………...........................................................................................................................................
Continuous, non-Operating ...............................................................................................................................................................................................
100ms, non-Operating .......................................................................................................................................................................................................
+IN to –IN
100
V
-0.5
10.5
+/- 100
+/- 100
5.7
V
mA
mA
V
VAUX
………………………………………………………………………..........................................................................................................................................
SGND
IFB
………………………………………………………………………..........................................................................................................................................
………………………………………………………………………..........................................................................................................................................
………………………………………………………………………..........................................................................................................................................
Remote Sense Operation ..................................................................................................................................................................................................
Adaptive Loop Operation ...................................................................................................................................................................................................
………………………………………………………………………...........................................................................................................................................
………………………………………………………………………...........................................................................................................................................
………………………………………………………………………...........................................................................................................................................
-0.5
-0.3
3.6
V
REF / REF_EN
10
mA
mA
V
3.4
TRIM
AL
-0.3
-0.3
-0.3
-0.5
3.6
3.6
V
VT
4.8
V
18
V
VC to –OUT
………………………………………………………………………...........................................................................................................................................
+/- 1.8
A
+OUT to –OUT
Output Current
………………………………………………………………………...........................................................................................................................................
………………………………………………………………………...........................................................................................................................................
TGrade……………………………………………………........................................................................................................................................................
M Grade ………………………………………………….......................................................................................................................................................
T Grade …………………………………………………........................................................................................................................................................
M Grade …………………………………………………........................................................................................................................................................
-1
62
V
7.3
A
-40
-55
-40
-65
125
125
125
125
ºC
ºC
ºC
ºC
Internal Operating
Temperature
Storage
Temperature
Rev. 1.0
11/2012
- 5 -
PRM48BH480 250A00
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted;
Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
POWER INPUT SPECIFICATION
Input Voltage Range
VIN Slew Rate
VIN
dVIN/dt
VINIT
tINIT
Continuous, operating
38
48
55
V
V/ms
V
0 ≤ VIN ≤ 55V
0.001
1000
Initialization Voltage
Initialization Delay
Internal micro controller initialization voltage
From VIN first crossing VINIT
10
7.0
2.4
14.5
5.4
2
5.0
9.0
3.5
20
ms
W
No Load Power Dissipation
Input Quiescent Current
Input Current
PNL
ENABLE HIGH, VIN = 48 V
IQC
ENABLE LOW, VIN = 48V
mA
A
IIN_DC
CIN_INT
RCIN
IOUT = 5.21A, VIN =48 V, VOUT = 48 V
Effective value, VIN = 48 V (see Fig. 13)
Effective value, VIN =48 V
5.6
Input Capacitance (Internal)
Input Capacitance (Internal) ESR
F
mΩ
3
POWER OUTPUT SPECIFICATION
Output Current
Output Power
IOUT
Standalone and Master operation, see Figure 1, SOA
Standalone and Master operation, see Figure 1, SOA
VIN = 48V VOUT = 48V, IOUT = 2.61A, TINT = 25°C
Over line, load, trim and temperature, exclusive of burst mode
From VIN first crossing VIN_UVLO+_SUPV to ENABLE high; tINIT expired
From ENABLE released to ENABLE high, VIN applied, tOFF, and tiNIT expired
From ENABLE high to startup sequence complete
VIN = 48V, VOUT = 48V, IOUT = 5.21A, TINT = 25°C
VIN = 48V, VOUT = 48V, IOUT = 2.61A, TINT = 25°C
VIN = 38V to 55V , VOUT = 48V, IOUT = 5.21A, TINT = 25°C
VIN = 38V to 55V , IOUT = 5.21A, TINT = 25°C, over trim
VIN = 48V, VOUT = 48V, IOUT = 5.21A, TINT = 100°C
VIN = 48V, VOUT = 48V, IOUT = 2.61A, TINT = 100°C
VIN = 38V to 55V , VOUT = 48V, IOUT = 5.21A, TINT = 100°C
VIN = 38V to 55V , IOUT = 5.21A, TINT = 100°C, over trim
>50% load and VOUT =48 V; over temperature
>50% load; over temperature and trim
5.21
250
A
POUT
W
0.935
1.03
20
1.065
1.065
MHz
MHz
Switching Frequency
FSW
0.70
Turn-ON Delay
tON
µs
Startup Sequence Timeout
tSTARTUP_SEQ
17
ms
%
95.7
94.7
95.0
92.0
95.5
94.5
95.0
91.5
94.5
89.0
96.7
95.7
%
Efficiency Ambient
ηAMB
%
%
96.5
95.8
%
%
Efficiency Hot
ηHOT
%
%
%
Efficiency Over Temperature
η
%
Output Discharge current
IOD
Average Value
0.5
1000
2.5
2
mA
mV
nH
F
mΩ
Output Voltage Ripple
VOUT_PP
LOUT_PAR
COUT_INT
RCOUT
VIN =48 V, VOUT = 48 V, IOUT =5.21A, COUT_EXT = 0 F, 20 MHz BW
Frequency @ 1.00 MHz, Simulated J-Lead model
Effective value, VOUT = 48 V (see Fig. 13)
1500
Output Inductance (Parasitic)
Output Capacitance (Internal)
Output Capacitance (Internal) ESR
Effective value, VOUT = 48 V
3
Rev. 1.0
11/2012
- 6 -
PRM48BH480 250A00
ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted;
Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted.
POWER OUTPUT SPECIFICATIONS: ADAPTIVE LOOP OPERATION
Output Voltage Setpoint
Output Voltage Trim Range
Output Voltage Rise Time
VOUT_SET
VOUT
No load, trim Inactive, Adaptive Loop load line inactive
47.04
20
48
48.96
55
V
V
tRISE_VOUT
From soft start initiated to output voltage settled
Adaptive Loop load line inactive
1.7
1.8
1.90
ms
Output Voltage Load Regulation
Output Voltage Line Regulation
Total Regulation Error
VOUT_REG_LOAD
VOUT_REG_LINE
VOUT_REG_TOTAL
0.02
0.02
0.2
0.2
0.2
3
%
%
%
%
Adaptive Loop load line inactive
PRM Output Voltage, Adaptive Loop load line inactive
VTM output voltage, total Adaptive Loop regulation, VOUT = 48 V, trim inactive
1
Total AL Regulation Error
Output Current Limit
VOUT_REG_AL
VTM output voltage, total Adaptive Loop regulation, trim active, exclusive of external resistor
tolerances
5
%
A
VIN = 48V, VOUT = 48V, TINT = 25°C, Constant current limit after supervisory limit detection time
tLIM_SUPV
5.7
6.5
7.3
ILIMIT
Over line, load, trim and temperature
5.2
7.3
47
A
Load Capacitance (Electrolytic)
Load Capacitance (Ceramic)
Load Transient Voltage Deviation
CLOAD_ALEL
CLOAD_CER
VTRANS
0.1Ω ≤ ESR ≤1.0ꢀ, See Figure 31, total capacitance (CLOAD_ALEL + CLOAD_CER) ≤ 47uF
2mΩ ≤ ESR ≤ 200mꢀ, See Figure 31
F
F
V
25
10% ↔ 100% load step, 10 A/µsec, 0 uF Cout, deviation from initial setpoint
4.8
10% to100% load step, 10 A/µsec, 0 uF Cout, Recovery to 90% of final value, Adaptive Loop
load line inactive
100
500
s
s
Load Transient Recovery Time
tTRANS
10% to 100% load step, 10 A/µsec, 0 uF Cout, Recovery to 90% of final value, Adaptive Loop
load line active, VAL=1.25V
POWER OUTPUT SPECIFICATIONS: SLAVE OPERATION
Slave operation within an array, up to 5°C case temperature differential, master-slave
configuration
4.16
3.6
A
A
Rated Current Within an Array
Rated Power Within an Array
IOUT_ARRAY
Slave operation within an array, up to 30°C case temperature differential, master-slave
configuration
Slave operation within an array, up to 5°C case temperature differential, master-slave
configuration
200
W
POUT_ARRAY
Slave operation within an array, up to 30°C case temperature differential, master-slave
configuration
175
15
W
%
%
Equal input, and output voltage at full load; VIN = 48 V, VOUT = 48 V
Equal input and output voltage at full load; Over line and trim,
with 25°C ≤ TC ≤ 100°C ≤ 5°C part-part temp mismatch
Current Sharing Difference (Master
to Slave)
15
IOUT_SHARE_MS
Equal input, and output voltage at full load; Over line and trim,
with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch
20
5
%
%
%
Equal input, output, and SHARE voltage at full load; VIN = 48 V, VOUT = 48 V
Equal input, output and SHARE voltage at full load; Over line and trim,
with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch
Current Sharing Difference (Slave to
Slave)
10
IOUT_SHARE_SS
Equal input, output, and SHARE voltage at full load; Over line and trim,
with25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp mismatch
15
%
Maximum Array Size
NPRMS_PARALLEL
Maximum number of parallel devices, master-slave configuration
5
PRMs
POWER OUTPUT SPECIFICATIONS: REMOTE SENSE OPERATION
Output Voltage Range
VOUT
20
55
4.7
3.6
225
175
5
V
A
Remote Sense operation within an array, up to 5°C case temperature differential
Remote Sense operation within an array, up to 30°C case temperature differential
Remote Sense operation within an array, up to 5°C case temperature differential
Remote Sense operation within an array, up to 30°C case temperature differential
Equal input, output, and CONTROL NODE voltage at full load; VIN = 48 V, VOUT = 48 V
Rated Current Within an Array
IOUT_ARRAY
A
W
W
%
Rated Power Within an Array
POUT_ARRAY
Equal input, output and CONTROL NODE voltage at full load; Over line and trim,
with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch
10
15
%
%
Current Sharing Difference
Maximum Array Size
IOUT_SHARE_RS
Equal input, output, and CONTROL NODE voltage at full load; Over line and trim,
with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch (worst case)
Maximum number of parallel devices, Remote Sense configuration, CONTROL NODE
externally driven
NPRMS_PARALLEL
10
PRMs
Rev. 1.0
11/2012
- 7 -
PRM48BH480 250A00
ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted;
Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted.
POWERTRAIN PROTECTIONS
Input Undervoltage Turn-ON
Input Undervoltage Turn-OFF
Input Undervoltage Hysteresis
Input Overvoltage Turn-ON
Input Overvoltage Turn-OFF
Input Overvoltage Hysteresis
Output Overvoltage Threshold
Minimum Current Limited Vout
Overtemperature Shutdown Setpoint
Output Power Limit
VIN_UVLO+
VIN_UVLO-
VUVLO_HYST
VIN_OVLO+
VIN_OVLO-
VOVLO_HYST
VOUT_OVP+
VOUT_UVP
TINT_OTP
24.5
22.7
2.2
26.0
2.5
V
V
Instantaneous powertrain shutdown, detected after tBLNK
(VIN_UVLO+) - (VIN_UVLO-
22.0
1.8
)
V
56.0
62.6
63.6
1.0
V
Instantaneous powertrain shutdown, detected after tBLNK
(VIN_OVLO+) - (VIN_OVLO-
67.3
1.4
V
)
0.7
V
Instantaneous powertrain shutdown, detected after tBLNK
56.0
57.9
60.0
12
V
V
Instantaneous powertrain shutdown, detected after tBLNK
125
250
ºC
W
V
PPROT
Short Circuit Vout Threshold
VSC_VOUT
8.8
9.5
Short Circuit Vout Recovery
Threshold
VSC_VOUTR
VSC_VCN
VSC_VCN
V
V
V
Short Circuit CONTROL NODE
Threshold
7.2
6.9
Short Circuit CONTROL NODE
Recovery Threshold
Short Circuit Timeout
tSC
Short circuit fault detected after VSC_VOUT and VSC_VCN thresholds persist for this time
Excludes tOFF
5
ms
ms
Short Circuit Recovery Time
tSCR
75
Overcurrent (IFB ), and Input
Over/Undervoltage Blanking Time
tBLNK
50
120
2
150
s
s
Overtemperature, Output
Overvoltage and ENABLE Shutdown
Response Time (Hardware)
tPROT
POWERTRAIN SUPERVISORY LIMITS
Input Undervoltage Turn-ON
(Supervisory)
VIN_UVLO+_SUPV
VIN_UVLO-_SUPV
VUVLO_HYST_SUPV
VIN_OVLO+_SUPV
VIN_OVLO-_SUPV
VOVLO_HYST_SUPV
Powertrain shutdown, after supervisory detection tLIM_SUPV
35.8
33.6
2.2
37.0
2.5
V
V
V
V
V
V
Input Undervoltage Turn-OFF
(Supervisory)
Powertrain shutdown, after supervisory detection tLIM_SUPV
32.2
1.9
Input Undervoltage Hysteresis
(Supervisory)
(VIN_UVLO+_SUPV) - (VIN_UVLO-_SVPV
)
Input Overvoltage Turn-ON
(Supervisory)
Powertrain shutdown after supervisory detection tLIM_SUPV
Powertrain shutdown after supervisory detection tLIM_SUPV
56.0
57.7
58.9
1.2
Input Overvoltage Turn-OFF
(Supervisory)
60.0
1.7
Input Overvoltage Hysteresis
(Supervisory)
(VIN_OVLO+_SUPV) - (VIN_OVLO-_SUPV
)
0.8
T Grade
M Grade
-40
-55
150
ºC
ºC
s
Undertemperature Shutdown
Setpoint (Supervisory)
TINT_UTP
Supervisory Limit Response Time
tLIM_SUPV
Rev. 1.0
11/2012
- 8 -
PRM48BH480 250A00
SIGNAL SPECIFICATIONS
Specifications apply over all line and load conditions, TINT = 25 ºC and output voltage from 20V to 55V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TINT < 125 ºC (T-grade).
ENABLE
• The ENABLE pin enables and disables the PRM
• In PRM array configurations, ENABLE pins should be connected in order to synchronize startup
• ENABLE is 5.0V with 1.8mA source capability during normal operation
Signal Type
State
Attribute
Symbol
Conditions / Notes
Min
4.7
Typ
Max
5.3
Unit
ENABLE voltage
VENABLE
5.0
V
Regular
ENABLE available
current
Operation
IENABLE_OP
1.8
mA
Analog Output
ENABLE source current
Minimum time to start
IENABLE_EN
tOFF
After tOFF
90
15
A
Startup
Startup
13.5
16.5
3.2
ms
ENABLE enable
threshold
VENABLE_EN
2.5
2.4
V
ENABLE disable
threshold
Digital Input / Output
Digital Output
VENABLE_DIS
RENABLE_EXT
IENABLE_FAULT
0.97
V
ꢀ
Standby
Fault
ENABLE resistance
(external)
Resistance to SGND required to disable the PRM
ENABLE voltage 1 V or above
235
4
ENABLE sink current to
SGND
mA
VAUX: AUXILARY VOLTAGE SOURCE
• Intended to power auxiliary circuits
• 9.0V during normal operation with 5mA source capability
Signal Type
State
Attribute
VAUX Voltage
Symbol
Conditions / Notes
Min
8.6
Typ
Max
9.5
Unit
VVAUX
9.0
V
Regular
Operation
VAUX Available Current
VAUX Voltage Ripple
IVAUX
5
mA
mV
Iout = 0A, CVAUX_EXT = 0. Maximum specification includes
powertrain operation in burst mode.
VVAUX_PP
100
30
400
Analog Output
VAUX Capacitance
(External)
CVAUX_EXT
tFR_VAUX
0.04
F
s
Transition
VAUX Fault Response
Time
From fault recognition to VAUX = 1.5 V
VC: VTM CONTROL
• Pulsed voltage source used to power and synchronize downstream VTM during startup
• 14 V, 10 ms typical voltage pulse
Signal Type
State
Attribute
VC Voltage
Symbol
Conditions / Notes
Min
13
Typ
Max
18
Unit
Connected to VTM VC or equivalent, IVC = 115mA, CVC
3.2uF
=
VVC_START
14
V
VC Available Current
VC duration
IVC_START
tVC
VC =14 V, VIN > 20 V
200
7
mA
ms
Analog Output
Startup
10
20
16
VC Slew Rate
dVC/dt
Connected to VTM or equivalent, IVC = 115mA, CVC = 3.2uF
0.02
0.25
V/s
ENABLE to VC delay
tENABLE-VC
s
Rev. 1.0
11/2012
- 9 -
PRM48BH480 250A00
SGND: SIGNAL GROUND
• All control signals must be referenced to this pin, with the exception of VC
• SGND is internally connected to –IN and –OUT
Signal Type
State
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
100
Unit
Maximum Allowable
Current
Analog Input / Output
Any
ISGND
-100
mA
TRIM
• TRIM is used to select operating mode and trim the output voltage in Adaptive Loop operation
• Internal pullup to VCC_INT through10kꢀ resistor
• When pulled below 0.45V during power up, Remote Sense / Slave operation is selected
• When allowed to pull up above 0.55 during power up, Adaptive Loop operation is selected
• Operating mode is latched during power up and cannot be changed unless input power is cycled
Signal Type
State
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
3.36
Unit
Internally generated
VCC
VCC_INT
3.20
3.28
V
Normal
Operation
Internal Pullup
Resistance to VCC_INT
RTRIM_INT
0.5% tolerance resistor
9.83
100
10
10.18
200
kꢀ
µs
V
Mode Detection Delay
tMODE_DETECT
VRS_MODE_EN
From ENABLE high to mode detected, after VIN first applied
140
Analog Input
Remote Sense Enable
Threshold
Pull below this value during application of power to enable
Remote Sense / Slave operation
0.45
Mode Detect
Remote Sense Disable
Threshold
Pull above this value during application of power to enable
Adaptive Loop operation
VRS_MODE_DIS
0.55
V
TRIM (ADAPTIVE LOOP OPERATION ONLY)
• Provides dynamic trim control over the PRM output voltage in Adaptive Loop operation
• Sampled prior to every startup to detect if trim is active or inactive
• Output voltage is equal to 20 times the voltage at the TRIM pin when applied TRIM voltage is within the active range
• Trim state is latched during normal operation and cannot be changed until startup is initiated
Signal Type
State
Attribute
Symbol
VTRIM_EN
VTRIM_DIS
Conditions / Notes
Min
Typ
Max
3.10
Unit
V
Trim Enable Threshold
Trim Disable Threshold
Pull below this value during startup to enable trim control
Pull above this value during startup to disable trim control
3.20
10
V
Minimum Trim Disable
Resistance
RTRIM_DIS_MIN
CTRIM_EXT
Minimum TRIM resistance required to disable trim
Mꢀ
Startup
Trim Capacitance
(External)
100
pF
µs
Trim Sample Delay
TRIM Pin Analog Range
TRIM Gain
tENABLE_TRIM
VTRIM_RANGE
GTRIM
From ENABLE high to TRIM sampled
See Figure 26
100
140
200
Analog Input
1.00
2.75
VOUT / VTRIM, VTRIM applied within active range
Vout accuracy, exclusive of external resistor tolerance
20
V/V
%
Trim Accuracy
%
0.5
2
ACC_TRIM
Normal
VOUT referred trim
resolution
Operation
VOUT_RES
200
mV
Trim latency
tTRIM_LAT
BWTRIM
60
120
1.2
240
s
Trim Bandwidth
-3dB point
kHz
Rev. 1.0
11/2012
- 10 -
PRM48BH480 250A00
AL: ADAPTIVE LOOP (ADAPTIVE LOOP OPERATION ONLY)
• Provides Adaptive Loop load line programming in Adaptive Loop operation
• Internal pullup to VCC_INT through10kꢀ resistor
• Sampled prior to every startup to detect if Adaptive Loop load line is active or inactive
• Leave open to disable Adaptive Loop load line
• Not used in Remote Sense operation
Signal Type
State
Attribute
Symbol
VAL_EN
Conditions / Notes
Min
Typ
Max
3.10
Unit
V
AL Enable Threshold
AL Disable Threshold
Pull below this value during startup to enable AL load line
Pull above this value to disable AL load line
VAL_DIS
3.20
V
Minimum AL Disable
Resistance
RAL_DIS_MIN
Minimum AL resistance required to disable AL load line
10
Mꢀ
Startup
AL Capacitance
(External)
CAL_EXT
100
pF
AL Sample Delay
tENABLE_AL
VCC_INT
From ENABLE high to AL sampled
0.5 % tolerance resistor
100
140
200
µs
Internally generated VCC
3.20
3.28
3.36
V
Internal Pullup
Resistance to VCC_INT
RAL_INT
9.83
0
10
10.18
3.10
kꢀ
Analog Input
AL Pin Analog Range
AL Gain
VAL_RANGE
GAL
V
Positive correction slope, VT inactive
1.0
0.5
3
ꢀ/V
Normal
Operation
Full load slope accuracy exclusive of external resistor
tolerance
AL Load Line Accuracy
AL load line resolution
%
2
%
mꢀ
V
ACC_LL_AL
LLAL_RES
Maximum output referred
compensation
VOUT_AL_MAX
Maximum increase from no load setpoint, VOUT ≤ 55V
5
AL Latency
tAL_LAT
BWAL
60
120
1.2
240
s
AL Bandwidth
-3dB point
kHz
VT: VTM TEMPERATURE (ADAPTIVE LOOP OPERATION ONLY)
• VTM temperature compensation for Adaptive Loop regulation
• Adjusts the slope of the Adaptive Loop load line to account for changes in VTM output resistance over temperature
• Connect to TM pin of compatible downstream VTM to enable temperature compensation
• Leave disconnected to disable temperature compensation
Signal Type
State
Attribute
Symbol
RVT_INT
VVT_EN
Conditions / Notes
Min
Typ
Max
2.1
Unit
kꢀ
V
Internal Resistance to
SGND
80
VT Enable Threshold
VT Disable Threshold
Pull below this value to disable VT temperature
compensation
VVT_DIS
TVT_DIS
1.9
V
VT Disable Default
Temperature
Default AL temperature setting when VT disabled
25
°C
Normal
Operation
VT analog range
VVT_OP
TCVT
2.18
3.98
V
Analog Input
VT within active range, referenced to 2.98V
30
%/V
VT Temperature
Coefficient
VTM TM voltage applied, .01V/°K, referenced to
25C
TCVT
0.3
%/C
VT Resolution
VT Latency
Bandwidth
TCVT_RES
tVT_LAT
VTM TM voltage applied, .01V/°K
0.4
120
1.5
°C
s
60
240
BWVT
-3dB point
kHz
Rev. 1.0
11/2012
- 11 -
PRM48BH480 250A00
REF / REF_EN
REF: REFERENCE (ADAPTIVE LOOP OPERATION ONLY)
• Functions as REF pin in Adaptive Loop operation
• REF represents the internal voltage reference for the voltage control circuit
• VOUT approximately equal to 20 times REF voltage
Signal Type
State
Attribute
REF Voltage
Symbol
Conditions / Notes
VOUT = 48V, Trim inactive
Min
Typ
Max
Unit
VREF
2.4
V
REF to VOUT Scale
Factor
GREF_VOUT
VOUT / VREF
20
V/V
Regular
Operation
REF Resistance
(External)
RREF_EXT
CREF_EXT
10
Mꢀ
Analog Output
REF Capacitance
(External)
200
pF
REF Voltage Ripple
ENABLE to REF Delay
VAUX to REF Delay
VREF_PP
tENABLE_REF
tVAUX_REF
includes burst mode, 20MHz BW
ENABLE low to REF low
25
120
1
mV
s
ms
Transition
VAUX = 8.1 V to REF soft start ramp initiated
REF_EN: REFERENCE ENABLE (REMOTE SENSE AND SLAVE OPERATION ONLY)
• Functions as REF_EN pin in Remote Sense and Slave operation
• REF_EN signals successful startup and powertrain ready to operate
• Intended to power and enable the external feedback circuit reference in Remote Sense operation
• 3.25V, 4mA regulated voltage source
Signal Type
State
Attribute
Symbol
VREF_EN
Conditions / Notes
Min
Typ
3.25
50
Max
3.37
100
Unit
V
REF_EN Voltage
REF_EN unloaded
2.72
REF_EN Source
Impedance
ROUT_REF_EN
ꢀ
REF_EN Available
Current
Regular
Operation
IREF_EN
4
mA
REF_EN Capacitance
(External)
Analog Output
CREF_EN_EXT
VREF_EN_PP
tENABLE_REF_EN
tVAUX_REF_EN
includes burst mode, 20MHz BW
includes burst mode
0.1
F
mV
ms
ms
REF_EN Voltage Ripple
25
1
ENABLE to REF_EN
Delay
ENABLE low to REF_EN low
VAUX = 8.1 V to REF_EN high
Transition
VAUX to REF_EN Delay
1
Rev. 1.0
11/2012
- 12 -
PRM48BH480 250A00
SHARE / CONTROL NODE
SHARE (ADAPTIVE LOOP AND SLAVE OPERATION ONLY)
• Functions as SHARE pin in master slave array configuration
• Current share bus for array operation (master/slave scheme)
• Sources current and provides SHARE signal in master operation
• Sinks constant current when externally driven in active range (Slave operation)
Signal Type
State
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
7.40
Unit
SHARE Voltage Active
Range
VSHARE
0.79
V
Standalone /
Master
Operation
SHARE Available
Current
Analog Output
ISHARE
RSHARE
VSHARE > 0.79V
2.5
mA
kꢀ
mA
SHARE Resistance to
SGND
93.3
0.50
Slave
Operation
Analog Input
SHARE Sink Current
ISHARE_SINK
VSHARE > 0.79V
0.25
0.75
CONTROL NODE (REMOTE SENSE OPERATION ONLY)
• Functions as CONTROL NODE pin in Remote Sense operation
• Modulator control node voltage sets power train timing
• Driven by external error amplifier in Remote Sense operation
• Sinks constant current when externally driven in active range
• Sources current, and clamps voltage to 0.79V when pulled below active range
Signal Type
State
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
7.40
Unit
CONTROL NODE
Voltage Active Range
VCN
0.79
V
CONTROL NODE
Source Current
ICN_LOW
ICN_SINK
RCN
VCN < 0.79V
VCN > 0.79V
2.5
mA
mA
kꢀ
Regular
Operation
Analog Input
CONTROL NODE Sink
Current
0.25
0.50
93.3
0.75
CONTROL NODE
Resistance to SGND
IFB: CURRENT FEEDBACK (REMOTE SENSE OPERATION ONLY)
• Functions as IFB pin in Remote Sense operation
• A voltage proportional to the PRM output current must be supplied externally to the IFB pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp)
• Overcurrent protection trip will cause instantaneous powertrain shutdown, detected after tBLNK
•Not used for Adaptive Loop operation
Signal Type
State
Attribute
Symbol
Conditions / Notes
VIN = 48V V; VOUT = 48V TINT = 25 °C
Over Line, Trim, and Temperature
Min
1.90
1.85
Typ
Max
2.10
2.15
Unit
V
2.00
Current Limit (clamp)
Threshold
VIFB_IL
V
Not Production Tested; Guaranteed by Design; TINT = 25 °C
2.58
2.09
2.09
2.69
2.80
2.17
2.17
V
V
Overcurrent Protection
Threshold
Regular
Operation
VIFB_OC
Analog Input
Not Production Tested; Guaranteed by Design; Over Line,
Trim, and Temperature
IFB Input Impedance
RIFB
2.13
2.0
kꢀ
Current Limit Bandwidth
BWIL
kHz
NC: NO CONNECT
• Reserved for factory use only
• No connections should be made to these pins
Rev. 1.0
11/2012
- 13 -
PRM48BH480 250A00
FUNCTIONAL BLOCK DIAGRAM
+IN
+OUT
Q3
Q1
Q2
Cout
Cin
L
-IN
-OUT
Q4
PGND
Internal
VCC
Regulator
30.1k
VCC
Error Amplifer
Modulator
1.58k
OTP
Enable
2.5mA Min
3.3V Linear
Regulator
0.5mA
Voltage Reference
3.3V
SHARE/
10k 10k
CONTROL NODE
VT
2.1k
VAUX
IFB
ENABLE
TRIM
NC
10k
20k
0.01uF
30.1
Control and Monitoring
SGND
0.01uF
1000pF
Overvoltage
Lockout
REF/
REF_EN
NC
Output
Overvoltage
Protection
AL
Undervoltage
Lockout
VC
10k
0.01uF
2200pF
60.4k
57.6k
35.7k
Current
Limit
1000pF
10
k
Output
Short
Circuit
Adaptive
Loop
IN
OUT
6800
pF
SGND
PGND
SGND
Rev. 1.0
11/2012
- 14 -
PRM48BH480 250A00
HIGH LEVEL FUNCTIONAL STATE DIAGRAM
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application of
Vin
VIN > UVLO+
STARTUP SEQUENCE
tON expired
ENABLE: 1.8mA to HIGH
STANDBY SEQUENCE
ENABLE rising edge
VC Pulse
ENABLE: 10uA to LOW
REF_EN active
tOFF expired
ENABLE: 90uA to HIGH
Adaptive loop and trim modes latched
RS mode latched at first ENABLE
Powertrain Stopped
after Vin applied only
Powertrain Active
ENABLE falling edge,
Output OVP,
or OTP detected
tSTARTUP_SEQ
expired
Input OVLO or UVLO,
Output UVP,
Fault
Auto-
or UTP detected
recovery
ENABLE falling edge,
Output OVP or
OTP detected
FAULT SEQUENCE
SUSTAINED
OPERATION
Input OVLO or UVLO,
ENABLE pulsed: 25mA to
LOW
Output UVP,
or UTP detected
ENABLE: 1.8mA to HIGH
Powertrain Active
Powertrain Stopped
Short Circuit detected
Rev. 1.0
11/2012
- 15 -
PRM48BH480 250A00
TIMING DIAGRAMS (Adaptive Loop operation page 1)
Module Inputs are shown in blue; Module Outputs are shown in brown.
Rev. 1.0
11/2012
- 16 -
PRM48BH480 250A00
TIMING DIAGRAMS (Adaptive Loop operation page 2)
Rev. 1.0
11/2012
- 17 -
PRM48BH480 250A00
TIMING DIAGRAMS (Remote Sense operation page 1)
Rev. 1.0
11/2012
- 18 -
PRM48BH480 250A00
TIMING DIAGRAMS (Remote Sense operation page 2)
Rev. 1.0
11/2012
- 19 -
PRM48BH480 250A00
TYPICAL PERFORMANCE CHARACTERISTICS
The following figures present typical performance at TC = 25ºC, unless otherwise noted.
Current
Power
Figure 1 DC Safe Operating Area (SOA)
Figure 4: Total efficiency and power dissipation vs. VIN and IOUT
V
OUT = 20 V, TCASE = -40 °C
Figure 2: No Load Power Dissipation vs. VIN, module enabled
Figure 5: Total efficiency and power dissipation vs. VIN and IOUT
VOUT = 20 V, TCASE = 25 °C
Figure 6: Total efficiency and power dissipation vs. VIN and IOUT
OUT = 20 V, TCASE = 100 °C
Figure 3: No Load Power Dissipation vs. VIN, module disabled
V
Rev. 1.0
11/2012
- 20 -
PRM48BH480 250A00
Figure 7: Total efficiency and power dissipation vs. VIN and IOUT
Figure 10: Total efficiency and power dissipation vs. VIN and IOUT
V
OUT = 48 V, TCASE = -40 °C
V
OUT = 55 V, TCASE =-40 °C
Figure 8: Total efficiency and power dissipation vs. VIN and IOUT
Figure 11: Total efficiency and power dissipation vs. VIN and IOUT
VOUT = 48 V, TCASE = 25 °C
VOUT = 55 V, TCASE = 25 °C
Figure 9: Total efficiency and power dissipation vs. VIN and IOUT
OUT = 48 V, TCASE = 100 °C
Figure 12: Total efficiency and power dissipation vs. VIN and IOUT
OUT = 55 V, TCASE =100 °C
V
V
Rev. 1.0
11/2012
- 21 -
PRM48BH480 250A00
INPUT AND OUTPUT
CAPACITANCE
Figure 13 Effective Internal Input and Output Capacitance vs. Voltage
Figure 16 Output Power vs. SHARE / CONTROL NODE Voltage;
IN = 48 V, VOUT = 48 V, TCASE = 25 °C
– Ceramic Type
V
Switching
Frequency
(kHz))
Input Charge
(µC)
Figure 14: Power Train Switching Frequency and Periodic Input
Figure 17: Typical SHARE / CONTROL NODE Voltage vs. TCASE and
Charge vs. VIN, VOUT; IOUT = 5.21 A
IOUT; VIN = 48 V, VOUT =48 V
Switching
Frequency
(kHz))
Output Charge
(µC)
Figure 15: Power Train Switching Frequency and Periodic Output
Charge vs. VIN, VOUT; IOUT = 5.21 A
Rev. 1.0
11/2012
- 22 -
PRM48BH480 250A00
GCN
(dB)
req
(Ω)
Figure 18 Powertrain Characteristics vs. IOUT, VIN
Figure 21 Magnitude of powertrain dynamic input impedance
Resistive Load, VOUT = 20V
vs. IOUT, VIN; VOUT = 20 V
GCN
(dB)
req
(Ω)
Figure 19 Powertrain Characteristics vs. IOUT, VIN
Figure 22 Magnitude of powertrain dynamic input impedance
Resistive Load, VOUT = 48V
vs. IOUT, VIN; VOUT = 48 V
GCN
(dB)
req
(Ω)
Figure 20 Powertrain Characteristics vs. IOUT, VIN
Figure 23 Magnitude of powertrain dynamic input impedance
Resistive Load, VOUT = 55V
vs. IOUT, VIN; VOUT = 55 V
Rev. 1.0
11/2012
- 23 -
PRM48BH480 250A00
GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions, TINT = 25 ºC and output voltage from 20V to 55V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TINT < 125 ºC (T-grade).
Attribute
Symbol
Conditions / Notes
MECHANICAL
Min
Typ
Max
Unit
21.8
(.86)
22.0
(0.87)
16.5
22.3
(.88)
mm
in
Length
Width
L
W
H
16.3
16.8
mm
in
(0.64)
6.48
(0.65)
6.73
(0.66)
6.98
mm
in
Height
(0.255)
(0.265)
2.44
(0.275)
No heat sink
cm3
in3
g
Volume
Weight
Vol
W
(0.15)
7
Nickel
0.51
0.02
2.03
0.15
Lead Finish
Palladium
Gold
m
0.003
0.050
THERMAL
T Grade
M Grade
-40
-55
125
125
ºC
ºC
Operating Internal Temperature
TINT
θINT-CASE
θINT-LEAD
2
9
5
ºC/W
ºC/W
Ws/ºC
Thermal Impedance
Thermal Capacity
ASSEMBLY
3
lbs
Peak Compressive Force Applied to
Case (Z-axis)
Supported by J-Lead only
lbs /
in2
5.33
125
125
T Grade
-40
-65
ºC
ºC
Storage Temperature
Moisture Sensitivity Level
ESD Rating
TST
M Grade
MSL 6, 245C Reflow
MSL5, 225C Reflow
MSL
Human Body Model, "JEDEC JESD 22-A114C.01"
Charged Device Model, "JEDEC JESD 22-C101D"
1000
400
V
SOLDERING
Under MSL 6 conditions above
Under MSL 5 conditions above
245
225
150
2
ºC
ºC
Peak Temperature During Reflow
Maximum Time Above 217 ºC
Peak Heating Rate During Reflow
Peak Cooling Rate Post Reflow
s
1.5
2.5
ºC / s
ºC / s
3
RELIABILITY AND AGENCY APPROVALS
Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled
MIL-HDBK-217Plus Parts Count - 25C Ground Benign, Stationary, Indoors / Computer Profile
CTUVUS EN60950-1, UL/CSA 60950-1
5.28
5.28
MHrs
MHrs
MTBF
Agency Approvals / Standards
CE Mark Low Voltage Directive (2006/95/EC)
ROHS 6 of 6
Rev. 1.0
11/2012
- 24 -
PRM48BH480 250A00
VC: VTM Control
PIN FUNCTIONS
This output pin is used to temporarily provide VCC voltage to
connected VTMs during start up. The pulse is nominally 14V,
10 ms wide. A VTM can self-power once its input voltage
reaches 26V. The PRM output must be checked to make sure
it reaches this threshold voltage before the VC pulse expires.
+IN, -IN
Input power pins
+OUT, -OUT
TRIM
Output power pins. Module cannot sink current.
The TRIM pin is used to select the operating mode and to trim
the PRM output when Adaptive Loop operating mode is
selected. The TRIM pin has an internal pull-up to VCC_INT
through a 10 kꢀ resistor.
ENABLE
This pin turns the supply on and off. The pin is both an input
and an output and can provide the following features:
Delayed Start: upon application of voltage (>UVLO) to the
module power input and after toff, the ENABLE pin will
source a constant 90μA current.
Operating Mode Select:
If TRIM is pulled below 0.45 V during the first startup after VIN
is applied, Remote Sense / Slave operation is selected.
Otherwise, Adaptive Loop operation is selected.
This selection persists until VIN is removed from the part, and is
not changed by fault or disable events.
Output enable: When ENABLE is allowed to pull up above
the enable threshold, the ENABLE pin will pull up to 5.0V
with 1.8mA source capability, and the module will be
enabled.
‐
Output Voltage Trim:
Sets the output voltage of the PRM in Adaptive Loop
operation.
If TRIM is permitted to pull up to 3.20 V or higher during start
up, trim is disabled, and the output is set to the nominal of 48V.
If TRIM is held between 1.00 V to 2.75 V during start up, trim
is enabled, and the output is scaled by a factor of 20 resulting
in an output voltage range of 20 V to 55 V.
Output disable: ENABLE may be pulled down externally in
order to disable the module. Pull down resistance should
be less than 235ꢀ to SGND.
Fault detection flag: The ENABLE 5.0V voltage source is
internally turned off when a fault condition is latched.
ENABLE control should be implemented using an open
collector configuration. It is not recommended to drive this pin
externally.
This selection persists until the PRM is restarted with the
ENABLE pin, or due to fault auto-recovery.
AL: Adaptive Loop (Adaptive Loop operation)
VAUX: Auxiliary Voltage Source
This input pin allows you to set the Adaptive Loop load line.
Every volt on this pin represents 1.0 ꢀ of positive output slope.
There is an internal 10 kꢀ pullup resistor to VCC_INT. If AL is
permitted to pull up to 3.20 V or higher during start up, the
Adaptive Loop load line is disabled.
Use this pin to power external devices with a non-isolated
9.0 V supply, with up to 5 mA load capability, switched with
ENABLE input. Do not place a capacitor over 0.04 µF on this
pin.
This selection persists until the PRM is restarted with the
ENABLE pin, or due to fault auto-recovery.
SGND: Signal Ground
This is a low current pin which provides a Kelvin connection to
the PRM’s internal signal ground. Use this pin as the ground
reference for external circuitry and signals to avoid voltage
drops caused by high currents on power returns. In array
configurations, SGND pins should be star connected at a
single point. A series resistor (~1ꢀ) to the star location is
recommended to decouple return currents.
VT: VTM Temperature (Adaptive Loop operation)
This pin is used in the Adaptive Loop compensation algorithm
to account for the VTM output resistance variation as a
function of temperature. The VTM TM pin provides this
voltage, scaled as the temperature in K (Kelvin) divided by
100, so 25 °C is 2.98 V. Leave disconnected or pull below
1.9V to disable. The adjustment is fixed at 0.3 %/°C relative to
the value at 25 °C
Rev. 1.0
11/2012
- 25 -
PRM48BH480 250A00
REF: Reference (Adaptive Loop operation)
and the equivalent output resistance vary as a function of line,
load and output voltage. As the load increases, the powertrain
pole moves to higher frequency. As a result, the closed loop
crossover frequency will be the highest at full load and lowest
at minimum load. Figure 24 shows a reference AC small-signal
model.
This output pin allows you to monitor the internal reference
voltage in Adaptive Loop operation. During normal operation it
represents the output voltage scaled by a factor of 20.
In Adaptive Loop operation this pin is for monitoring purposes
only and should not be driven or loaded externally.
+
CIN_INT
REF_EN: Reference Enable (Remote Sense operation)
VIN
rEQ_IN
In Remote Sense operation this pin outputs a regulated 3.25V,
4mA voltage source. It is enabled only after successful start up
of the PRM powertrain REF_EN is intended to power the
output current transducer and also the voltage reference for
the external control loop. Powering the reference generator
with REF_EN helps provide a controlled start up, since the
output voltage of the system is able to track the reference level
as it comes up.
-
+
+
VCN · GCN
COUT_INT
RCN
rEQ_OUT
ICN_Low
-
SHARE (Adaptive Loop and Slave operation)
Figure 24 – PRM48BH480[x]250A00 AC small signal
model
This bus sets the output current level for all the PRM modules
when operating in an array (master-slave configuration).
Connect them together among the modules in the shared bus.
One PRM should be configured as a master by connecting
TRIM for Adaptive Loop operation. All other PRMs should be
configured as slaves by pulling their respective TRIM pins low.
This pin can be used to monitor the error voltage externally.
0 to 100% load is represented by a voltage between 0.79 V
and 7.40.
IFB: Current Feedback (Remote Sense operation)
In Remote Sense operation, IFB is the input for the module
output overcurrent protection and current limit features.
A
voltage proportional to the powertrain output current must be
applied to IFB in order for overcurrent protection to operate
properly.
If the IFB voltage exceeds the IFB pin’s overcurrent protection
threshold, the powertrain will stop switching. If the IFB voltage
falls below the overcurrent protection threshold within tBLANK
time, then the powertrain will immediately resume switching.
Otherwise a fault is detected.
The current limit threshold for the IFB pin is set lower than the
protection threshold. When the IFB pin average voltage
exceeds the current limit threshold, an internal integrator will
activate a clamp amplifier which overrides the modulator input
maximum level. This causes the powertrain to maintain a
constant output current.
The bandwidth of this current limit integrator is significantly
slower than that of the CONTROL NODE input. Therefore this
current limit cannot be used in lieu of properly compensating
the (external) control loop to avoid exceeding maximum
current or power ratings for the device.
CONTROL NODE (Remote Sense operation)
In Remote Sense operation, this is the input to the modulator
which determines the powertrain timing and ultimately the
module output power. An internal 0.5 mA current sink is
always active. The bi-directional buffer between CONTROL
NODE and the modulator has two states. In normal operation,
CONTROL NODE will be above the 0.79 V switching
threshold, and will drive the modulator through the buffer. An
internal 7.4V clamp determines the maximum output power
that can be requested of the modulator.
When CONTROL NODE falls below 0.79 V, the converter will
stop switching. An internal circuit clamps the modulator input
to 0.79 V, and a buffer will source up to 2.5 mA out of the pin
at that clamp level. For this reason, the output impedance of
the amplifier driving CONTROL NODE must be taken into
account. A rail-to-rail operational amplifier with low output
impedance is always recommended.
The powertrain small signal (plant) response consists of a
single pole determined by the load resistance, the powertrain
equivalent output resistance, and the total output capacitance
(internal and external to the module). Both the modulator gain
Rev. 1.0
11/2012
- 26 -
PRM48BH480 250A00
To configure the part for Adaptive Loop operation, leave the
TRIM pin disconnected, or apply a voltage/resistance within
the specified range.
DESIGN GUIDELINES
The PRM48BH480[x]250A00 regulator is specifically designed
to provide a controlled Factorized Bus distribution voltage for
powering downstream VTM Transformer — fast, efficient,
isolated, low noise Point-of-Load (POL) converters.
The operating mode is detected and latched during the first
start up after VIN is applied. This selection persists until VIN is
removed from the part, and is not changed by fault or disable
events. Changing the operating mode can only be done by
removing VIN.
The PRM48BH480[x]250A00 can be configured for two
operating modes depending on the type of regulation required.
DESIGN GUIDELINES (Adaptive Loop operation)
In Adaptive Loop operation the regulation circuitry is enabled
within the device and regulates the voltage at the output
terminals. The PRM48BH480[x]250A00 has a programmable
Adaptive Loop load line which can be used to compensate for
downstream VTM output resistance allowing for precise point
of load regulation without the need for remote sensing.
In Adaptive Loop operation, the internal voltage control
circuitry is enabled and the voltage at the output terminals is
regulated. The part is nominally set to provide a fixed 48V
output, and the TRIM pin can be used to adjust the output over
the range of 20 V to 55 V.
In Remote Sense operation, the internal regulation circuitry is
disabled and the voltage regulation circuitry is provided
externally allowing for remote sensing directly at the point of
load. In certain applications Remote Sense operation can
improve regulation accuracy, and allow for operating with high
amounts of load capacitance and optimizing load transient
response.
When used with a VTM, the AL pin provides ability to program
an Adaptive Loop load line to compensate for the output
resistance (ROUT) of a downstream VTM, while the VT pin
provides temperature compensation to account for changes in
the VTM ROUT over temperature.
Trim Mode and Output Trim Control (Adaptive Loop
operation)
Operating Mode Selection
The operating mode is selected through use of the TRIM pin.
In Adaptive Loop operation, during any start up and after
ENABLE transitions high, the TRIM pin voltage is sampled to
determine if trim is active or inactive. If the sampled TRIM
voltage is higher than 3.20V then the PRM will disable trim. In
this case, for all subsequent operation the output voltage will
be programmed to the nominal output of 48V and the TRIM pin
will be ignored during normal operation.
When the part is first enabled after VIN is applied, the TRIM
voltage is sampled. The TRIM pin has an internal pull up
resistor to VCC_INT, so unless external circuitry pulls the pin
voltage lower, it will float up to VCC_INT
.
If TRIM is pulled lower than 0.45V during the first startup after
VIN is applied, the part will be configured for
If the sampled TRIM voltage is between
1.0 V and 3.10 V then the PRM will activate trim mode and it
will remain in this mode as long as the PRM is operating.
Remote Sense / Slave operation, where the internal voltage
regulation circuitry is disabled. In this case, for all subsequent
operation the part will output a voltage dependent on the
SHARE / CONTROL NODE voltage provided externally (either
from an external regulation circuit or master PRM).
This selection persists until the PRM is restarted with the
ENABLE pin, or due to fault auto-recovery.
To configure the part for Remote Sense or Slave operation,
connect the TRIM pin to SGND. It is recommended to make
this connection through a 0ꢀ jumper for troubleshooting
purposes.
If the sampled TRIM voltage is higher than 0.55V during the
first startup after VIN is applied, then the part will be configured
for Adaptive Loop operation, and the internal voltage regulation
circuitry is enabled. The PRM will output a voltage dependent
on the TRIM voltage, and will remain in this mode for as long
as VIN is applied.
Rev. 1.0
11/2012
- 27 -
PRM48BH480 250A00
VCCINT
Recommended Range
10K
TRIM
VTRIM
Mi cro
Controller
RTRIM
SGND
Unspecified
Operation
Figure 25: TRIM Connection
The output as a function of VTRIM is defined by equation (1) for
1.00 V ≤ VTRIM ≤ 2.75 V, and allows for an output voltage
ranging from 20V to 55V.
The TRIM pin is pulled up internally to VCC_INT thorough a 10
kꢀ resistor. VTRIM can be actively set with a DAC that is
ground referenced to SGND. VTRIM can be passively set by
connecting a resistor, RTRIM, from TRIM to SGND such that the
voltage divider made with VCC_INT and the 10 kꢀ pull up yields
the desired VTRIM. The formula for calculating this resistor is
provided in Equation (1a).
Figure 26: PRM VOUT vs. VTRIM
When trim is enabled the voltage at this pin is sampled at 120
µs intervals to determine the trim level. The output can be
dynamically trimmed during normal operation, however it is not
recommended to use this pin in an external analog feedback
loop.
ꢀꢁꢂꢃ ꢄ ꢀꢃꢅꢆꢇ ∙ 20
(1)
Refer to Table 1 for a summary of the TRIM pin functionality
and the recommended voltage/resistance that should be
applied to this pin.
ꢉꢊꢋꢌ∙ꢍ
ꢉꢊꢋꢌ∙ꢍ
ꢖꢗꢎ_ꢘꢙꢎ
ꢎꢏꢐꢑ
ꢈꢃꢅꢆꢇ ꢄ ꢍ
ꢄ ꢚꢊ∙ꢍ
(1a)
ꢔꢕꢍ
ꢔꢍ
ꢖꢗꢎ_ꢘꢙꢎ
ꢒꢒ
ꢎꢏꢐꢑ
ꢒꢒ_ꢐꢓꢎ
ꢐꢓꢎ
For 1.00 V≤ VTRIM ≤ 2.75 V
Where VOUT_SET is the desired output voltage
The output voltage tranfer function saturates for applied TRIM
voltages above approximately 2.75V as illustrated in Figure 26
to prevent the output from being driven above its rated output
voltage.
When TRIM is set lower than 1.00 V the output voltage is not
specified and stable operation is not guaranteed.
TRIM PIN FUNCTION SUMMARY
Operating State
VTRIM
RTRIM
<1 kΩ
Detected and Latched
After application of VIN when
ENABLE first transitions high
After application of VIN when
ENABLE first transitions high
Remote Sense / Slave Operation
Adaptive Loop Operation
<0.45V
>0.55V[2]
> 3 kΩ [2]
Trim Active
OUT = 20* VTRIM
1.00 V to 2.75 V
>3.2 V
4.32 kΩ to 49.9 kΩ
>10 MΩ
V
Adaptive Loop Operation
Trim Mode
At every start up when
ENABLE transitions high
Trim Inactive
VOUT = 48V
Table 1: TRIM Pin Function Summary
[2] It is not recommended to configure TRIM with a voltage less than 1.00V in Adaptive Loop operation
Rev. 1.0
11/2012
- 28 -
PRM48BH480 250A00
Adaptive Loop Compensation (Adaptive Loop operation)
accordingly increases the output voltage of the PRM in order to
regulate the PRM’s output resistance to a fixed negative
resistance, RLL_AL, settable by way of the AL pin. RLL_AL should
be sized to exactly cancel the ROUT of the VTM at 25°C. The
AL engine is also able to account for the positive temperature
coefficient of ROUT by way of its VT pin which will be explained
shortly.
A factorized power system naturally has a DC load line
associated with it since the regulator stage (PRM) is positioned
before the isolation and voltage transformation stage (VTM.)
Consider for a moment a factorized power system that has the
following parameters:
VF = 40V
VTM=1/4
ROUT_VTM =10mohm @ 25°C
K
At no load the output voltage at the load will be equal to 10V
(VF • KVTM). With increasing load current, the output voltage at
the load will drop at a rate proportional to the VTMs ROUT. It
should be noted that the ROUT has a positive temperature
coefficient and so the DC load line changes with temperature.
Compensated VTM Output
Adaptive Loop compensation brings
output into regulation
If the presence of this load line is acceptable for your
application, then the PRM can be configured by way of the
TRIM pin alone. Please refer to the Trimming the Output
Voltage section for details. In this case both the AL and VT
pins should be left open.
Figure 27: Adaptive Loop Compensation Illustration
If the presence of this load line is undesirable, the load line can
be eliminated by way of the PRM’s Adaptive Loop (AL) engine.
The AL engine measures the output current of the PRM and
PRM
ENABLE
TRIM
AL
VAUX
REF/
REF_EN
ON/OFF CONTROL
VTM
VOUT
VTM Startup Pulse
VC
TM
PC
VC
VT
IFB
+OUT
Adaptive Loop Temperature Feedback
SGND
SHARE/
CONTROL NODE
RTRIM
RAL
COUT
SGND
CIN
VIN
38V to 55V
+IN
-IN
+OUT
-OUT
+IN
-IN
LF
VF: 20V to 55V
CF
-OUT
SGND
GND
PRIMARY
SECONDARY
SEC_GND
ISOLATION BOUNDRY
SGND
Figure 28: PRM-VTM Adaptive Loop Example
Rev. 1.0
11/2012
- 29 -
PRM48BH480 250A00
Setting the Adaptive Loop Load Line (Adaptive Loop
operation)
Similar to TRIM, AL is sampled during every start up to
determine if the Adaptive Loop load line is enabled or disabled.
If the AL pin is allowed to pull up to 3.20V or higher during start
up, then then the PRM will disable the Adaptive Loop load line
as long as the PRM remains operating. In this case, for all
subsequent operation the output voltage will be remain at the
set voltage, and the AL pin will be ignored.
To determine an appropriate value for the compensation slope
(RLL_AL) it helps to reflect the VTM’s output resistance to the
input side of the VTM. A resistance on the output side of the
VTM is scaled by the VTMs transformer ratio (KVTM) squared
as defined by equation (2):
This selection persists until the PRM is restarted with the
ENABLE pin, or due to fault auto-recovery.
ꢉ
ꢈꢛꢛ_ꢜꢛ ꢄ ꢈꢁꢂꢃ_ꢅꢝꢞꢛ ꢄ ꢈꢁꢂꢃ_ꢍꢃꢇ_ꢚꢟꢠ ∙ ꢡꢢ ꢤꢚ
(2)
ꢣꢎꢑ
When AL is enabled, the voltage at this pin is sampled at
120 µs intervals to determine the load line. The load line can
be adjusted during normal operation, however it is not
recommended to use this pin in an external analog feedback
loop.
Where
R
OUT_VTM is the VTM output resistance at 25°C
KVTM is the VTM transformer ratio VIN/VOUT
For our hypothetical VTM from above (with KVTM = 1/4 and
OUT_VTM = 10mꢀ) the output resistance reflected over to the
R
Adaptive Loop Temperature Compensation (Adaptive
Loop operation)
input would be equal to 160 mꢀ. For this example, RLL_AL
should be set to -160 mꢀ to approximately cancel at 25°C the
inherent load line from the VTM.
By connecting the VT pin of the PRM to the VTM’s TM pin, the
PRM is able to monitor the internal temperature of the VTM.
Knowing the VTM’s internal temperature and the temperature
coefficient of the VTM’s ROUT, which is preprogrammed into the
PRM’s microcontroller, the AL engine is able to scale the
nominal value of RLL_AL (set by the AL pin) to track the VTM’s
R
LL_AL is set by the voltage difference between the AL pin and
SGND pin, VAL, per the following formula:
Rꢥꢥ_ꢦꢥ ꢄꢕVꢦꢥ ꢕ∙ ꢡꢧ1.0ꢤꢕΩ/V
(3)
R
OUT over temperature. In this way the output resistance of the
VAL ≤ 3.10V
Where VAL is the voltage on the AL pin
PRM can be tuned to cancel the output resistance of the VTM
with the addition of a single resistor across the AL pin and a
connection of the VTM’s TM pin to the PRM’s VT pin.
V
V
AL is sampled by a 10-bit ADC, whose input is connected to
CC_INT through a 10 kꢀ pull up resistor. This pull up disables
The VTM TM voltage is equal to the VTM internal sensed
temperature in Kelvin divided by 100. For a temperature range
of -55 °C to 125 °C the TM voltage will range from
2.18 V to 3.98 V. The Adaptive Loop temperature
compensation is pre-programed into the internal
microcontroller and is 0.3 %/°C assuming the VT pin is
connected to the TM pin of a compatible VTM
the AL engine when the AL pin is left open. VAL can be actively
set with a DAC that is ground referenced to SGND. VAL can be
passively set by connecting a resistor, RAL, from AL to SGND
such that the voltage divider made with VCC_INT and the 10 kꢀ
pull up yields the desired VAL. The formula for calculating this
resistor is provided in Equation (4).
ꢉꢊꢋꢌꢕ∙ꢍ
ꢨꢩꢕ
The TM pin has an internal pull down to SGND, and
temperature compensation is disabled for VT voltages less
than 1.9V. To disable temperature compensation, leave the
VT pin unconnected and open circuit. When disabled, the
temperature defaults 25 °C.
ꢈꢜꢛ ꢄ ꢍ
(4)
ꢔꢕꢍ
ꢒꢒ_ꢐꢓꢎ
ꢨꢩ
VCCINT
10K
AL
VAL
Micro
Controller
RAL
SGND
Figure 29: AL Connections
Rev. 1.0
11/2012
- 30 -
PRM48BH480 250A00
Stability Considerations and External Capacitance
(Adaptive Loop operation)
2.18V to 3.98V
(-55C to 125C)
20K
VT
In Adaptive Loop operation, the internal voltage regulation is
enabled which has a pre-determined, fixed compensation
network. The compensation is designed to be stable over a
fixed set of operating and load conditions including load
capacitance.
VTM TM
MICRO
CONTROLLER
60.4k
Besides internal output capacitors, external output capacitors
also contribute to the closed loop frequency response, thus
should be identified and understood, in order to maintain the
control loop stability. This includes capacitance placed directly
on the PRM output, as well as capacitance on the output of
any downstream VTM (if used) reflected to its input.
SGND
Figure 30: VT Connections
Figure 32 illustrates the requirements for external capacitors of
both the capacitance and ESR value. As shown in
Figure 32 (a), the maximum capacitance value of ceramic
capacitor is 25 µF, and the capacitance of a combination of
ceramic and electrotype capacitors needs to be less than 47
µF. As shown in Figure 32 (b) and (c), the ESR value of
electrotype capacitors needs to be between 0.1 ꢀ and 1.0 ꢀ;
the ESR value of ceramic capacitors needs to be between
2 mꢀ and 200 mꢀ.
Compensation slope
increases with
temperature based on VT
feedback
Compensated VTM Output
VTM ROUT increases with
temperature
Figure 31: Adaptive Loop Temperature Compensation
Illustration
The discussion thus far only considered the case where the AL
engine is used to compensate for the ROUT of the VTM. The AL
engine can be more generally used to account for distribution
resistances in both the factorized bus and the VTM’s output
distribution bus. For more information on how to apply the AL
engine towards this end please contact Vicor’s Applications
Engineering department.
ESR
(Ohm)
ESR
(Ohm)
CCER (uF)
25
CCER ≤ 25
0.1 ≤ ESR ≤ 1
1
CCER + CEL < 47
0.02 ≤ ESR ≤ 0.2
0.2
0.02
0.1
47
22
ESRCER
ESREL
CEL(uF)
(a) Maxium Capacitance limits
(b) ESREL requirements
(c) ESRCER requirements
Figure 32: Output Capacitance Limits
Rev. 1.0
11/2012
- 31 -
PRM48BH480 250A00
Current Limit (Adaptive Loop operation)
In Adaptive Loop operation, the current limit is controlled by
the internal microcontroller. The current limit approximates a
“brick-wall” limit where the output current is prevented from
crossing the current limit threshold by reducing the output
voltage. The current limit threshold is pre-programmed into the
internal microcontroller and cannot be changed externally.
When the internal sensed current crosses the current limit
threshold, the current limit will be activated after the detection
time tLIM_SUPV. Once activated, the microcontroller will reduce
the error amplifier reference voltage (represented by REF) in
order to maintain the output current at the limit value. Current
limit is able to reduce the output down to VOUT_UVP, below which
the device will shut down do to output under voltage protection.
Figure 34: PRM Example 100% to 10% Load Transient
Response, Adaptive Loop Load Line Disabled
Soft Start Timing and Start up (Adaptive Loop operation)
When the Adaptive Loop load line is enabled, the voltage will
recover to the value determined by the set point and Adaptive
Loop load line settings as illustrated in Figure 35.
In Adaptive Loop operation, the PRM has an internal soft start
sequence which is initiated at every start up. This allows the
PRM to start into fully discharged load capacitance. The soft
start sequence ramps the output by modulating the error
amplifier reference voltage (REF). The result is that the PRM
output will rise at a controlled rate until the final voltage
setpoint is reached. The total ramp time is typically 1.8ms
independent of the output trim level. This soft start ramp time
is preprogrammed into the microcontroller and cannot be
changed externally.
Load Transient Response (Adaptive Loop Operation)
In Adaptive Loop operation, response time is dependent on the
internal compensation. When the Adaptive Loop load line is
disabled, the PRM output voltage will recover to the initial set
value as illustrated in Figure 33 and Figure 34.
Figure 35: PRM Example 10% to 100% Load Transient
Response, Adaptive Loop Load Line Enabled, VAL = 1.25V
Actual response times are model dependent and will change
based on the load step magnitude, load capacitance and
operating conditions.
Because the compensation is fixed internally the load transient
response cannot be altered for Adaptive Loop operation.
In order to improve the load transient response performance,
the part can be configured for Remote Sense operation with an
external voltage control loop optimized for the specific intended
operating conditions. Remote Sense operation is described in
a later section.
Figure 33: PRM Example 10% to 100% Load Transient
Response, Adaptive Loop Load Line Disabled
Rev. 1.0
11/2012
- 32 -
PRM48BH480 250A00
Arrays (Adaptive Loop / Slave operation)
SHARE pins must be connected together to enable
sharing. The bandwidth requirements of SHARE are
low enough that the bus can be considered a lumped
element, rather than a transmission line, and so star
connections to the master PRM with stubs, as well as
daisy chain connections are permitted.
In Adaptive Loop operation a master-slave configuration is
used for arrays. Up to 5 PRMs of the same type may be
placed in parallel to expand the power capacity of the system.
One PRM is designated as the master and contains the active
control loop which considers control pin inputs and drives
SHARE. The other PRMs listen to SHARE and act as slave
powertrains only. The following high-level guidelines must be
followed in order for the resultant system to start up and
operate properly, and to avoid overstress or exceeding any
absolute maximum ratings.
The resistances between slave unit SHARE pins and
the master’s should be well matched, to avoid
introducing additional sharing mismatches. The
SHARE bus should not be routed under any PRM.
SHARE bus parasitic capacitance to +IN or +OUT
should be minimized.
One PRM must be designated as a master through
configuring the TRIM pin voltage within the
recommended range.
SGND of the master PRM is the reference for all
control loop functions. The SGND pins of each slave
PRMs should be connected to the SGND reference
node on the board through a 1 ꢀ resistor.
All other PRMs must be designated as slave PRMs by
tying TRIM pins to SGND. It is recommended to make
this connection through a 0ꢀ jumper for
troubleshooting purposes.
When operating within an array, the master PRM is
rated for full power while the slave PRMs are de-rated
to the array rated power and current values provided
for Slave operation(POUT_ARRAY,IOUT_ARRAY). The
number of PRMs required to achieve a given array
capacity must consider these de-ratings to avoid
overstressing any PRM in the array.
All PRMs in the array must be powered from a
common power source so that the input voltage to
each PRM is the same. The IN pins of all PRMs must
be connected together.
An independent fuse for each PRM +IN connection is
required to maintain safety certifications (see Fusing
section).
Adaptive Loop design procedures above will hold for
an array, in general, although some parameters must
be scaled against the number of PRMs in the system.
An independent inductor for each PRM +IN connection
is recommended when used in an array, to control
circulating currents among the PRM inputs and reduce
the impact of beat frequencies.
Arrays of more than 5 PRMs may be possible through use of
external circuitry. Please contact Vicor Applications for
assistance with array sizing above 5 units.
Mismatches in both inductance, and resistance from
the common power source to each PRM should be
minimized.
ENABLE pins must be connected together for start up
synchronization and proper fault response of the array.
Rev. 1.0
11/2012
- 33 -
PRM48BH480 250A00
Setting the Output Current Limit and Overcurrent
Protection Level (Remote Sense operation)
DESIGN GUIDELINES (Remote Sense operation)
In Remote Sense operation, the PRM48BH480[x]250A00 is an
intelligent powertrain module designed to fully exploit external
output voltage feedback and current sensing sub-circuits.
These two external circuits are illustrated in Figure 36, which
shows an example of the PRM in a standalone application with
local voltage feedback and high side current sensing.
In general, these circuits include a precision voltage reference,
an operational amplifier which provides closed loop feedback
compensation, and a high side current sense circuit which
includes a shunt and current sense IC.
In Remote Sense operation, the internal current sensing is
disabled, and an external current sense amplifier must be
implemented to provide feedback to the IFB pin.
The current limit and overcurrent protection set points are
linked, and scale together against the current sense shunt, and
the gain of the current sense amplifier. The output of the
current sense IC provides the IFB voltage which has VIFB_IL and
VIFB_OC thresholds for the two functions respectively. The set
points are therefore defined by:
The following design procedures refer to the circuit shown in
Figure 36.
VIFB _ IL
IIL
(6)
RS GCS
Setting the Output Voltage Level (Remote Sense
operation)
and
VIFB _ OC
The output voltage setpoint is a function of the voltage
reference and the output voltage sense ratio. With reference to
Figure 36, R1 and R2 form the output voltage sensing divider
which provides the scaled output voltage to the negative input
of the error amplifier; a dedicated reference IC provides the
reference voltage to the positive input of the error amplifier.
Under normal operation, the error amplifier will keep the
voltages at the inverting and non-inverting inputs equal, and
therefore the output voltage is defined by:
IOC
(7)
RS GCS
where GCS is the gain of the current sense amplifier.
R1 R2
(5)
VOUT Vref
R2
Note that the component R1 will also factor into the
compensation as described in a later section.
It is important to apply proper slew rate to the reference
voltage rise when the control loop is initially enabled. The
recommended range for reference rise time is 1 ms to 9 ms.
The lower rise time limit will ensure optimized modulator timing
performance during start up, and to allow the current limit
feature (through IFB pin) to fully protect the device during
power-up. The upper rise time limit is needed to guarantee a
sufficient factorized bus voltage is provided to any downstream
VTM input before the end of the VC pulse.
Rev. 1.0
11/2012
- 34 -
PRM48BH480 250A00
C2
C1
R3
-
Vref
+
R2
R1
CONTROL
VAUX
+IN
RS
F1
NODE
+OUT
PRMTM
Regulator
CIN_EXT
COUT_EXT
CIN_INT
COUT_INT
-IN
-OUT
SGND
IFB REF_EN
Vref
I sense
IC
Vref IC
Figure 36: Remote Sense Example
Rev. 1.0
11/2012
- 35 -
PRM48BH480 250A00
Control Loop Compensation Requirements (Remote
Sense operation)
The system poles and zeros of the closed loop can then be
defined as follows:
In order to properly compensate the control loop, all
components which contribute to the closed loop frequency
response should be identified and understood. Figure 24
shows the AC small signal model for the module. Modulator
DC gain GCN and powertrain equivalent resistance rEQ_OUT are
shown. These modeling parameters will support a design cut-
off frequency up to 50kHz.
Standard Bode analysis should be used for calculating the
error amplifier compensation and analyzing the closed loop
stability. The recommended stability criteria are as follows:
Powertrain pole, assuming the external capacitor
ESR is negligible:
rEQ _ OUT RLOAD
RC
OUT _ EXT
rEQ _ OUT RLOAD
Main pole frequency:
1) Phase Margin > 45º : for the closed loop response, the
phase should be greater than 45º where the gain crosses 0dB.
2) Gain Margin > 10dB : The closed loop gain should be lower
than -10dB where the phase crosses 0º.
1
FP
rEQ_OUT RLOAD
2π
COUT _ INT COUT _ EXT
rEQ_OUT RLOAD
3) Gain Slope = -20dB/decade : The closed loop gain should
have a slope of -20dB/decade at the crossover frequency.
Compensation Mid‐Band Gain:
The compensation characteristics must be selected to meet
these stability criteria. Refer to Figure 37 for a local sense,
voltage-mode control example based on the configuration in
Figure 36. In this example, it is assumed that the maximum
crossover frequency (FCMAX) has been selected to occur
between B and C. Type-2 compensation (Curve IJKL) is
sufficient in this case.
R3
GMB 20log
R1
(8)
(9)
Compensation Zero:
The following data must be gathered in order to proceed:
Modulator Gain GCN: See Figures 18, 19, 20
Powertrain equivalent resistance rEQ: See Figures 18,
19, 20
1
FZ1
Internal output capacitance: see Figure 13
External output capacitance value
2 πR3C1
Compensation Pole:
In the case of ceramic capacitors, the ESR can be considered
low enough to push the associated zero well above the
frequency of interest. Applications with high ESR capacitor
may require a different type of compensation, or cascade
control.
1
FP2
R3 C1 C2
2π
C1 C2
and for FP2>>FZ1 (C1 + C2 ≈ C1):
1
FP2
(10)
2 R3 C2
Rev. 1.0
11/2012
- 36 -
PRM48BH480 250A00
Midband Gain Design: R1,R3 (Remote Sense operation)
PRM open loop response, and is where the minimum
crossover frequency FCMIN occurs. Based on stability criteria,
the compensation must be in the mid-band at the minimum
crossover frequency, therefore FCMIN will occur where EFG is
equal and opposite of GMB. C1 can be selected using Equation
With reference to Figure 37: curve ABC is the:
minimum output voltage in the application
maximum input voltage expected in the application
maximum load
(9) so that FZ1 occurs prior to FCMIN
.
High Frequency Pole Design: C2 (Remote Sense
operation):
PRM open loop response, and is where the maximum
crossover frequency occurs. In order for the maximum
crossover frequency to occur at the design choice FCMAX, the
compensation gain must be equal and opposite of the
powertrain gain at this frequency. For stability purposes, the
compensation should be in the Mid-band (J-K) at the
crossover. Using Equation (8), the mid-band gain can be
selected appropriately.
Using Equation (10), C2 should be selected so that FP2 is at
least one decade above FCMAX and prior to the gain bandwidth
product of the operational amplifier (10MHz for this example).
For applications with a higher desired crossover frequency the
use of a high gain bandwidth product amplifier may be
necessary to ensure that the real pole can be set at least one
decade above the maximum crossover frequency.
Compensation Zero Design :C1 (Remote Sense operation):
With reference to Figure 37: curve EFG is the:
maximum output voltage in the application
minimum input voltage expected in the application
minimum load in the application
Open Loop Gain vs. Frequency
80
60
40
20
0
Application's op-amp G·BW
I
Compensation Gain
F
E
PRM Open Loop Min Load
B
A
PRM Open Loop Max Load
J
K
L
FCMAX
FCMIN
-20
-40
C
G
Frequency, Log scale
(y-intercept is application specific)
Figure 37 – Reference asymptotic Bode plot for the considered system
Rev. 1.0
11/2012
- 37 -
PRM48BH480 250A00
Arrays (Remote Sense operation)
sharing mismatches. The CONTROL NODE bus
should not be routed under any PRM. Parasitic
capacitance to +IN or +OUT should be minimized.
One PRM should be designated to provide the SGND
reference, VAUX, and REF_EN voltages for the
external circuitry.
In Remote Sense operation up to 10 PRMs of the same type
may be placed in parallel to expand the power capacity of the
system. All PRMs within the array are configured for Remote
Sense operation and are driven by an external control circuit
which considers the control inputs and drives the
CONTROL NODE bus. The following high-level guidelines
must be followed in order for the resultant system to start up
and operate properly, and to avoid overstress or exceeding
any absolute maximum ratings.
The SGND pins of all other PRMs should be
connected to the SGND reference node on the board
through a 1 ꢀ resistor.
When operating within an array, the PRMs are de-
rated to the array rated power and current values
All PRMs must be configured for Remote Sense
operation by tying TRIM pins to SGND. It is
recommended to make this connection through a 0ꢀ
jumper for troubleshooting purposes.
provided for Remote Sense operation (POUT_ARRAY
,
IOUT_ARRAY). The number of PRMs required to achieve a
given array capacity must consider these de-ratings to
avoid overstressing any PRM in the array.
All PRMs in the array must be powered from a
common power source so that the input voltage to
each PRM is the same.
When using VAUX to power external circuitry, total
current draw including CONTROL NODE sink currents
must be taken into account to ensure the maximum
VAUX current is not exceeded. Arrays of more than 5
PRMs may require additional circuitry to provide the
required source current. Contact Vicor Applications
Engineering for more information.
An independent fuse for each PRM +IN connection is
required to maintain safety certifications (see Fusing
section).
An independent inductor for each PRM +IN connection
is recommended when used in an array, to control
circulating currents among the PRM inputs and reduce
the impact of beat frequencies.
Mismatches in both inductance, and resistance from
the common power source to each PRM should be
minimized.
ENABLE pins must be connected together for start up
synchronization and proper fault response of the array.
Reference supply to the control loop voltage reference
and current sense circuitry must be enabled when all
modules’ REF_EN pins have reached their operational
voltage levels.
A single external control circuit must be implemented
as described in the Remote Sense operation design
guidelines. The control circuit should drive the
CONTROL NODE bus.
CONTROL NODE pins must be connected together to
enable sharing. The bandwidth requirements of
CONTROL NODE are low enough that the bus can be
considered a lumped element, rather than a
transmission line, and so star connections as well as
daisy chain connections are permitted.
Each PRM must have its own local current shunt and
current sense circuitry to drive its IFB pin.
The resistances between CONTROL NODE pins
should be well matched, to avoid introducing additional
Rev. 1.0
11/2012
- 38 -
PRM48BH480 250A00
DESIGN GUIDELINES (General Operation)
k
k
Vout
Vout
The following guidelines are general guidelines that apply to
any mode of operation.
d
d
FPA System Considerations
time
time
time
Iout
Iout
There are a few system level design considerations that should
be carefully considered when using a PRM and VTM to
implement a Factorized Power Architecture (FPA) system
time
(a) without Adaptive Loop
(b) with Adaptive Loop
The VC pin of the PRM should be directly connected to the VC
pin of the VTM. The PRM and VTM coordinate the soft start
sequence of the FPA system through this connection. If the VC
pins are not connected the VTM will not start up. When the
PRM is ready to start up, it applies a voltage on VC, which
enables and powers the VTM’s powertrain. The PRM then
proceeds to ramp up its output voltage. After approximately
10ms, VC returns to 0V and the VTM can then derive power
directly from the factorized bus provided that the factorized bus
voltage is above the minimum specified VTM operating input
voltage when the VC pulse expires.
Figure 38 – load step response example and “droop” vs. “kick”
definition. (a) with Adaptive Loop; (b) without Adaptive Loop.
2
k
ln
d
2
(11)
m 100
k
ln
2
d
Burst Mode Operation:
All VTM faults latch the VTM powertrain off. Input power to the
system as a whole must be recycled or the PRM should be
disabled and enabled by way of its ENABLE pin in order to
restart the system. It is recommended that the voltage on the
factorized bus return to zero before the PRM is re-enabled.
Otherwise the soft start of the system may be compromised.
At light loads, the PRM will operate in a burst mode due to
minimum timing constraints. An example burst operation
waveform is illustrated in Figure 39.
For very light loads, and also for higher input voltages, the
minimum time power switching cycle from the powertrain will
exceed the power required by the load. In this case the error
amplifier will periodically drive SHARE/CONROL NODE below
the switching threshold in order to maintain regulation.
Switching will cease momentarily until the error amplifier once
again drives SHARE/CONTROL NODE voltage above the
threshold.
A RL filter should be placed between the PRM and VTM to
locally isolate switching ripple currents that can interfere with
module operation. It is important that the inductance have an
impedance that is much greater than that of the PRM output
capacitance and VTM input capacitance at the switching
frequencies of the devices. A resistor should be placed in
shunt to this inductor to dampen the resultant LC tank. For
most cases 100nH in parallel with 10ꢀ is sufficient to isolate
the switching ripple currents.
Verifying Stability:
A load step transient response can be used in order to
estimate stability.
Figure 38 illustrates an example of a load step response.
Equation (11) can be used to predict the phase margin based
on the ratio of the “kick” to “droop” (as defined in Fig. 38).
Figure 39 – light load burst mode of operation
Rev. 1.0
11/2012
- 39 -
PRM48BH480 250A00
Note that during the bursts of switching, the powertrain
frequency is constant, but the number of pulses as well as the
time between bursts is variable. The variability depends on
many factors including input voltage, output voltages, load
impedance, and error amplifier output impedance.
Lline
(13)
Rline
(
CIN _ INT CIN _ EXT ) rEQ _ IN
In burst mode, the gain of the SHARE/CONTROL NODE input
to the plant which is modeled in the previous sections is time
varying. Therefore the small signal analysis cannot be directly
applied to burst mode operation.
(14)
Rline rEQ _ IN
It is critical that the line source impedance be at least an
octave lower than the converter’s dynamic input resistance
(14). However, RLINE cannot be made arbitrarily low otherwise
equation (13) is violated and the system will show instability,
due to under-damped RLC input network.
Input and Output filter design
Figures 14 and 15 provide the total input and output charge
per cycle, as well as switching frequency, of the PRM at full
load under various input and output voltages conditions.
Figure 13 provides the effective internal capacitance of the
module. A conservative estimate of input and output peak-
peak voltage ripple at nominal line and trim is provided by
equation (12):
Inductive source and local, external input decoupling
capacitance with significant RCIN_EXT ESR (i.e.: electrolytic
type)
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor LLINE. Notice
that, the high performance ceramic capacitors CIN_INT within the
PRM should be included in the external electrolytic
capacitance value for this purpose. The stability criteria will be
IFL 0.4
fSW
CINT CEXT
QTOT
V
(12)
(15)
(16)
rEQ _ IN R
CIN _ EXT
QTOT is the total input (Fig. 14) or output (Fig. 15) charge per
switching cycle at full load, while CINT is the module internal
effective capacitance at the considered voltage (Fig. 13) and
CEXT is the external effective capacitance at the considered
voltage.
Lline
rEQ _ IN
CIN _ EXT RC
IN _ EXT
Equation (16) shows that if the aggregate ESR is too small –
for example by using very high quality input capacitors
(CIN_EXT) – the system will be under-damped and may even
become destabilized. Again, an octave of design margin in
satisfying (15) should be considered the minimum.
Input filter stability
The PRM can provide very high dynamic transients. It is
therefore very important to verify that the voltage supply
source as well as the interconnecting line are stable and do not
oscillate. For this purpose, the converter dynamic input
Layout Considerations
impedance magnitude
is provided in Figures 21, 22,
rEQ _ IN
Application
Note
AN:005
details
board
layout
23. It is recommended to provide adequate design margin with
respect to the stability conditions illustrated in the previous
sections.
recommendations using V•I Chip components, with details on
good power connections, reducing EMI, and shielding of
control signals and techniques to reference them to SGND.
Avoid routing control signals (ENABLE, TRIM, AL etc.) directly
underneath the PRM. It is critical that all control signals (aside
from VC and VT) are referenced to SGND, both for routing and
for pull-down and bypassing purposes. VC and VT provide
control and feedback from a VTM, and must be referenced to –
OUT of the PRM (-IN of the VTM)
Inductive source and local, external input decoupling
capacitance with negligible ESR (i.e.: ceramic type)
The voltage source impedance can be modeled as a series
RLINE LLINE circuit. The high performance ceramic decoupling
capacitors will not significantly damp the network because of
their low ESR; therefore in order to guarantee stability the
following conditions must be verified:
SGND is connected to –IN internally to the PRM. SGND
should not be tied to any other ground in the system.
Rev. 1.0
11/2012
- 40 -
PRM48BH480 250A00
Input Fuse Recommendations
A fuse should be incorporated at the input to each PRM, in
series with the +IN pin. A 10A or smaller input fuse (Littlefuse®
NANO2® 451/453 series) is required to safety agency
conditions of acceptability. Always ascertain and observe the
safety, regulatory, or other agency specifications that apply to
your specific application.
Thermal Considerations
V•IchipTM products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input / output conditions, thermal management and
environmental conditions. Maintaining the top of the
PRM48BH480[x]250A00 case to less than 100ºC will keep all
junctions within the V•I Chip module below 125ºC for most
applications. The percent of total heat dissipated through the
top surface versus through the J-lead is entirely dependent on
the particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a V•I Chip module for an
extended period of time at full load without proper
heat sinking.
Rev. 1.0
11/2012
- 41 -
PRM48BH480 250A00
PRODUCT OUTLINE DRAWING AND REOMMENDED LAND PATTERN
Rev. 1.0
11/2012
- 42 -
PRM48BH480 250A00
REVISION HISTORY
Revision
Date
Description
Page Number(s)
1.0
11/12/2012
Final approved datasheet for initial release
All
Rev. 1.0
11/2012
- 43 -
PRM48BH480 250A00
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully
configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes
no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to
make changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been
checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other
quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government
requirements, testing of all parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR
SIGNATORY, VICOR DISCLAIMS ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY
IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY
WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, INFRINGEMENT OF ANY
PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be
liable for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and
assumes no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor
products and components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design,
testing and operating safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR
CORPORATION. As used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be
reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose
failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per
Vicor Terms and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and
indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property
rights is granted by this document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
Rev. 1.0
11/2012
- 44 -
相关型号：
©2020 ICPDF网 联系我们和版权申明