5962-906021MRC [VISHAY]
4-/8-Channel Wideband Video Multiplexers; 4- / 8通道宽带视频多路复用器
| 型号： | 5962-906021MRC |
| 厂家： | 
VISHAY |
| 描述： | 4-/8-Channel Wideband Video Multiplexers |
| 文件： | 总16页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG534A/538A
Vishay Siliconix
4-/8-Channel Wideband Video Multiplexers
FEATURES
BENEFITS
APPLICATIONS
D Wide Bandwidth: 500 MHz
D Improved System Bandwidth
D Improved Channel Off-Isolation
D Wideband Signal Routing and
Multiplexing
D Very Low Crosstalk: –97 dB @ 5 MHz
D Video Switchers
D ATE Systems
D On-Board TTL-Compatible Latches with D Simplified Logic Interfacing
Readback
D High-Speed Readback
D Optional Negative Supply
D Infrared Imaging
D Allows Bipolar Signal Swings
D Reduced Insertion Loss
D Ultrasound Imaging
D Low rDS(on): 45
ꢀ
D Single-Ended or Differential Operation
D Latch-up Proof
D Allows Differential Signal Switching
DESCRIPTION
The DG534A is a digitally selectable 4-channel or dual
2-channel multiplexer. The DG538A is an 8-channel or dual
4-channel multiplexer. On-chip TTL-compatible address
decoding logic and latches with data readback are included to
simplify the interface to a microprocessor data bus. The low
on-resistance and low capacitance of the these devices make
them ideal for wideband data multiplexing and video and audio
signal routing in channel selectors and crosspoint arrays. An
optional negative supply pin allows the handling of bipolar
signals without dc biasing.
The DG534A/DG538A are built on a D/CMOS process that
combines n-channel DMOS switching FETs with low-power
CMOS control logic, drivers and latches. The low-capacitance
DMOS FETs are connected in a “T” configuration to achieve
extremely high levels of off isolation. Crosstalk is reduced to
–97 dB at 5 MHz by including a ground line between adjacent
signal paths. An epitaxial layer prevents latch-up.
For more information refer to Vishay Siliconix applications
note AN502.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG534ADJ
Dual-In-Line
DG534ADN
PLCC
GND
NC
1
2
20
19
18
17
16
15
14
13
12
11
D
A
D
B
3
2
1
20 19
V+
V–
3
S
4
5
6
7
8
18
17
16
15
14
S
B1
A1
S
A1
S
B1
4
GND
GND
GND
GND
5
S
A2
S
B2
V
L
S
A2
S
B2
6
4/2
RS
4/2
RS
V
L
7
NC
Latch/Drivers
I/O
EN
8
Latches/Drivers
Top View
WR
9
9
10 11 12 13
A
1
A
0
10
Top View
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
1
DG534A/538A
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG538ADJ
Dual-In-Line
DG538ADN
PLCC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
D
B
D
A
V–
3
V+
S
B1
4
3
2
1 28 27 26
4
S
A1
GND
5
GND
S
B2
5
6
25
24
23
22
21
20
19
GND
GND
6
S
A2
S
B2
S
A2
GND
7
GND
GND
7
GND
S
B3
8
S
A3
S
B3
8
S
A3
GND
9
GND
GND
9
GND
S
B4
V
L
10
11
S
A4
S
V
B4
10
11
12
13
14
S
A4
8/4
L
Latch/Drivers
8/4
RS
I/O
EN
12 13 14 15 16 17 18
Latch/Drivers
Top View
WR
A
0
1
A
2
A
Top View
TRUTH TABLE Ċ DG534A
I/O
A1
A0
EN
WR
RS
4/2a
On Switch
X
X
X
0
0
0
0
0
0
1
X
X
X
0
X
X
X
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
Maintains previous state
X
X
0
0
0
0
0
0
0
1
X
None (latches cleared)
None
X
X
0
0
S
A1
S
A2
S
B1
S
B2
S
A1
S
A2
0
1
0
D
and D may be
B
A
connected externally
1
0
0
Latches Transparent
1
1
0
X
X
0
1
1
1
and S
and S
B1
B2
Note b
Note c
Logic “0” = V v 0.8 V
AL
Logic “1” = V w 2.4 V
AH
X = Don’t Care
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
2
DG534A/538A
Vishay Siliconix
TRUTH TABLE Ċ DG538A
I/O
A2
A1
A0
EN
WR
RS
8/4a
On Switch
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Maintains previous state
None (latches cleared)
None
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
0
S
A1
S
A2
S
A3
S
A4
S
B1
S
B2
S
B3
S
B4
S
A1
S
A2
S
A3
S
A4
0
0
0
D
and D should be
B
A
connected externally
0
0
Latches Transparent
0
0
1
and S
and S
and S
and S
B1
B2
B3
B4
1
1
1
Note b
Note c
Logic “0” = V v 0.8 V
AL
Logic “1” = V w 2 V
AH
X = Don’t Care
Notes:
a. Connect D and D together externally for single-ended operation.
A
B
b. With I/O high, A and EN pins become outputs and reflect latch contents. See timing diagrams for more detail.
n
c. 8/4 can be either “1” or “0” but should not change during these operations.
ORDERING INFORMATION
Temperature Range
DG534A
Package
Part Number
20-Pin Plastic DIP
20-Pin PLCC
DG534ADJ
–40 to 85_C
DG534ADN
–55 to 125_C
20-Pin Sidebraze
DG534AAP/883, 5962-906021MRC
DG538A
28-Pin Plastic DIP
28-Pin PLCC
DG538ADJ
–40 to 85_C
DG538ADN
–55 to 125_C
28-Pin Sidebraze
DG538AAP/883, 5962-8976001MXA
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
3
DG534A/538A
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +21 V
V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +21 V
V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to +0.3 V
Storage Temperature
(A Suffix) . . . . . . . . . . . . . . . . . . . –65 to 150_C
(D Suffix) . . . . . . . . . . . . . . . . . . . –65 to 125_C
a
Power Dissipation (Package)
b
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW
V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to (V+) + 0.3 V
c
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V ) + 0.3 V
L
d
Sidebraze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW
or 20 mA, whichever occurs first
Notes:
V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V–) + 14 V
S
D
a. All leads soldered or welded to PC board.
b. Derate 8.3 mW/_C above 75_C.
c. Derate 6 mW/_C above 75_C.
d. Derate 16 mW/_C above 75_C.
or 20 mA, whichever occurs first
Current (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Current(S or D) Pulsed l ms 10% Duty . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
Mind Maxd Mind Maxd Unit
D Suffix
–40 to 85_C
V+ = 15 V, V– = –3 V, V = 5 V
L
Parameter
Symbol
Tempb Typc
WR = 0.8 V, RS, EN= 2 V
Analog Switch
g
Analog Signal Range
V
V– = –5 V
Full
–5
8
–5
8
V
ANALOG
Drain-Source
On-Resistance
Room
Full
45
90
120
90
120
r
DS(on)
I
V
= –10 mA, V = 0 V
S
S
= 0.8 V, V
= 2 V
ꢀ
AIL
AIH
Resistance Match
Between Channels
Sequence Each Switch On
ꢁ
r
Room
9
9
DS(on)
Source Off
Leakage Current
Room
Full
0.05
0.1
–5
–50
5
50
–5
–50
5
50
I
I
V
S
V
S
= 8 V, V = 0 V, EN = 0.8 V
D
S(off)
Drain Off
Leakage Current
Room
Full
–20
–500
20
500
–20
–100
20
100
= 0 V, V = 8 V, EN = 0.8 V
D
nA
D(off)
Drain On
Leakage Current
Room
Full
0.1
–20
–1000
20
1000
–20
–200
20
200
I
V = V = 8 V
S D
D(on)
Digital Control
Input Voltage High
Input Voltage Low
V
Full
Full
2
2
AIH
V
V
0.8
0.8
AIL
Room
Full
–0.1
–1
–10
1
10
–1
–10
1
10
Address Input Current
Address Output Current
I
V
AI
= 0 V, or 2 V or 5 V
ꢂ
A
AI
V
= 2.7 V
= 0.4 V
Room
Room
–21
–2.5
–2.5
AO
I
mA
AO
V
3.5
2.5
2.5
AO
Dynamic Characteristics
PLCC
DIP
Room
Room
Room
Room
Room
Room
28
31
3
40
45
5
40
45
4
On State Input
Capacitance
C
S(on)
C
S(off)
C
D(off)
See Figure 11
See Figure 12
g
PLCC
DIP
Off State Input
pF
g
Capacitance
4
5
PLCC
DIP
6
10
8
Off State Output
g
Capacitance
8
10
Room
Full
160
300
500
300
500
Transition Time
t
TRANS
See Figure 4
Break-Before-Make
Interval
Room
Full
80
50
25
50
25
t
OPEN
ns
Room
Full
150
105
–70
300
500
300
500
EN, WR Turn On Time
t
See Figure 2 and 3
ON
Room
Full
175
300
175
300
EN, Turn Off Time
Charge Injection
t
See Figure 2
See Figure 5
OFF
Qi
Room
pC
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
4
DG534A/538A
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 15 V, V– = –3 V, V = 5 V
L
Parameter
Symbol
Tempb Typc
Mind Maxd Mind Maxd Unit
WR = 0.8 V, RS, EN= 2 V
Dynamic Characteristics (Cont’d)
R
L
= 75 ꢀ ꢃ f = 5 MHz
EN = 0.8 V
See Figure 8
PLCC
DIP
Room
Room
–75
–65
f
Chip Disabled Crosstalk
X
TALK(CD)
R
= 10 ꢀ
= 10 kꢀ
IN
PLCC
DIP
Room
Room
–97
–87
R
L
f = 5 MHz
SeeFigure 9
f
Adjacent Input Crosstalk
X
TALK(AI)
R
R
= 75 ꢀ , R = 75 ꢀ
f = 5 MHz
See Figure 7
PLCC
DIP
Room
Room
–80
–70
IN
L
R
IN
= 10 ꢀ
dB
PLCC
DIP
Room
Room
–77
–72
R
L
= 10 kꢀ
f = 5 MHz
See Figure 7
All Hostile Crosstalk
Differential Crosstalk
X
TALK(AH)
= 75 ꢀ , R = 75 ꢀ
PLCC
DIP
Room
Room
–77
–72
IN
L
f = 5 MHz
See Figure 7
R
IN
= 10 ꢀ , R = 10 kꢀ
L
Room
–84
f = 5 MHz, See Figure 10
X
TALK(DIFF)
R
IN
= R = 75 ꢀ
L
Room
Room
–84
f = 5 MHz, See Figure 10
Bandwidth
BW
R
L
= 50 ꢀ , See Figure 6
500
MHz
Power Supplies
Positive Supply Current
Room
Full
0.6
0.6
2
5
2
5
I+
Any One Channel Selected with Ad-
dress Inputs at GND or 5 V
mA
Room
Full
–1.8
–2
–1.8
–2
Negative Supply Current
I–
V+ to V–
V– to GND
V+ to GND
Full
Full
Full
Full
10
–5.5
10
21
0
10
–5.5
10
21
0
Functional Check of
Maximum Operating
Supply Voltage Range
Functional Test Only
V
21
500
21
500
Logic Supply Current
Timing
I
L
150
ꢂ
A
Room
Full
–22
60
Reset to Write
t
RW
50
200
100
50
50
200
100
50
WR, RS
Minimum Pulse Width
Room
Full
t
MPW
A , A , EN
Room
Full
20
0
1
t
t
DW
WD
Data Valid to Strobe
See Figure 1
ns
A , A , EN
Room
Full
–20
0
1
Data Valid after Strobe
e
Address Bus Tri-State
Address Bus Output
Address Bus Input
t
Room
Room
Room
25
95
AZ
t
AO
t
110
AI
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Defined by system bus requirements.
f.
Each individual pin shown as GND must be grounded.
g. Guaranteed by design, not subject to production test.
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
5
DG534A/538A
Vishay Siliconix
CONTROL CIRCUITRY
S
A1
S
A2
S
A3
S
A4
D
A
D
B
S
B1
S
B2
S
B3
S
B4
S
A1
S
B1
– S
– S
A4
B4
V–
D , D
A
B
V–
Decode
A
0
A
0
A
1
A
1
A
2
A
2
EN
V–
Latch
V
REF
8/4
I/O
Decode
Tri-State
Buffer
V
L
V–
V
REF
V
*
V
REF
V
REF
V
REF
V
REF
V
REF
REF
V
L
*
V+
I/O
V–
EN
A
0
A
1
A
2
RS
WR
V
L
*Typical all Readback (A , EN) pins
X
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
6
DG534A/538A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Supply Currents vs. Temperature
Leakage vs. Temperature
1 ꢂA
1.4
V+ = 15 V
V– = –3 V
V+ = 15 V
V– = –3 V
= 5 V
1.0
I+
V
L
= 5 V
100 nA
10 nA
V
L
0.6
0.2
I
L
I
D(on)
1 nA
I
D(off)
–0.2
–0.6
–1.0
–1.4
100 pA
10 pA
1 pA
I–
I
S(off)
–40
–20
0
20
40
60
80 100 120
–40
–20
0
20
40
60
80 100 120
Temperature (_C)
Temperature (_C)
Address, EN Output Current vs. Temperature
r
vs. V–, V+
DS(on)
8
0
70
V
V
I
= 0 V
= 5 V
= –10 mA
D
L
S
(Source)
V
AO
= 0.4 V
V+ = 10 V
60
–8
V+ = 12 V
50
40
–16
V
= 2.7 V
AO
V+ = 15 V
(Sink)
V+ = 15 V
V– = –3 V
–24
–32
V
= 5 V
L
30
–40 –20
0
20
40
60
80 100 120
–6
–5
–4
–3
–2
–1
0
Temperature (_C)
V– – Negative Supply (V)
r
vs. V and Temperature
Adjacent Input Crosstalk vs. Frequency
DS(on)
D
200
180
160
–100
–80
V+ = 15 V
V– = –3 V
V+ = 15 V
V– = –3 V
DIP
V
I
= 5 V
= – 10 mA
V
L
= 5 V
L
S
R
R
= 10 ꢀ
= 10 kꢀ
IN
L
140
120
PLCC
25_C
–60
100
80
125_C
–40
–20
60
40
20
–55_C
–2
0
2
4
6
8
10
1
10
f – Frequency (MHz)
100
V
D
– Drain Voltage (V)
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
7
DG534A/538A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Adjacent Input Crosstalk vs. Frequency
Adjacent Input Crosstalk vs. Frequency
–100
–100
–80
V+ = 15 V
V– = –3 V
V
L
= 5 V
PLCC
–80
–60
R
IN
= R = 75 ꢀ
L
DIP
PLCC
–60
DIP
V+ = 15 V
V– = –3 V
–40
–20
–40
–20
V
L
= 5 V
R
R
= 10 ꢀ
= 10 kꢀ
IN
L
1
10
f – Frequency (MHz)
100
1
10
100
f – Frequency (MHz)
All Hostile Crosstalk vs. Frequency
All Hostile Crosstalk vs. Frequency
–100
–80
–100
–80
PLCC
PLCC
DIP
DIP
–60
–60
V+ = 15 V
V– = –3 V
V+ = 15 V
V– = –3 V
–40
–20
–40
–20
V
L
= 5 V
V
L
= 5 V
R
R
= 10 ꢀ
= 10 kꢀ
IN
R
IN
= R = 75 ꢀ
L
L
1
10
100
1
10
100
f – Frequency (MHz)
f – Frequency (MHz)
Differential Crosstalk vs. Frequency
Differential Crosstalk vs. Frequency
–100
–80
–100
–80
PLCC
PLCC
DIP
–60
–60
DIP
V+ = 15 V
V– = –3 V
V+ = 15 V
V– = –3 V
–40
–20
–40
–20
V
L
= 5 V
V
L
= 5 V
R
R
= 10 ꢀ
= 10 kꢀ
R
R
= 75 ꢀ
= 75 ꢀ
IN
IN
L
L
1
10
100
1
10
100
f – Frequency (MHz)
f – Frequency (MHz)
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
8
DG534A/538A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Switching Times vs. Temperature
Transition Time vs. Temperature
225
250
225
200
175
150
125
200
175
t
ON
t
TRANS
150
125
100
75
t
OFF
t
BBM
100
75
50
–40 –20
0
20
40
60
80
100 120
–40 –20
0
20
40
60
80
100 120
Temperature (_C)
Temperature (_C)
OUTPUT TIMING REQUIREMENTS
t
MPW
3 V
0 V
WR
t
WD
t
DW
3 V
0 V
A , A , A , EN
Don’t Care
Write Data
Don’t Care
0
1
2
Writing Data to Device
3 V
WR
0 V
3 V
A , A , A , EN
0
1
2
Don’t Care
New Data
Don’t Care
0 V
3 V
0 V
RS
t
t
RW
MPW
Delay Time Required after Reset before Write
3 V
0 V
WR
3 V
A , A , A , EN
Hi Z
Hi Z
Driven Bus
Device Data* Out
Driven Bus
0
1
2
0 V
3 V
I/O
0 V
t
t
AZ
AO
t
AI
Reading Data From Device
FIGURE 1.
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
9
DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+15 V
+
Logic Input
t <20 ns
10 ꢂF
100 nF
r
t <20 ns
f
3 V
0 V
+5 V
50%
EN
V+
V
L
S
Bn
+1 V
A
0
S – S
A1 Bn-1
A , A
1
8/4, 4/2
WR
2
V
OUT
90%
RS
EN
D
D
A
Switch
Output
V
O
B
I/O
GND V–
0 V
1 kꢀ
45 pF
t
t
OFF
ON
+
10 ꢂF
100 nF
–3 V
FIGURE 2. EN, CS, CS, Turn On/Off Time
+15 V
+
Logic Input
10 ꢂF
100 nF
+1 V
t <20 ns
t <20 ns
f
r
+5 V
WR
+3 V
0 V
V+
EN, V , RS
S
A1
L
A
0
A , A
S – S
A2 Bn
1
2
+3 V
0 V
8/4, 4/2
I/O
t
(WR)
ON
V
OUT
90%
Address
Logic
A
0
D
A
V
O
WR
GND
D
B
V–
1 kꢀ
45 pF
+
Logic
Input
10 ꢂF
100 nF
–3 V
FIGURE 3. WR, Turn On Time
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
10
DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+15 V
+
Logic Input
t <20 ns
10 ꢂF
100 nF
r
t <20 ns
f
+5 V
+1 V
A , A , A
3 V
0 V
0
1
2
V+
50%
EN
S
S
A1
V
OUT
V
L
90%
B1
Bn
S
– S
A2
RS
S
1
S
16
A , A , A
0
1
2
Turning Off
Turning On
D
A
BBM Interval
8/4
or
4/2
V
O
D
B
Transition Time
WR
I/O
GND
V–
(t
)
Logic
Input
TRANS
1 kꢀ
45 pF
+
10 ꢂF
100 nF
–3 V
FIGURE 4. Transition Time and Break-Before-Make Interval
+15 V
+
+5 V
10 ꢂF
100 nF
V+
V
L
EN
A , A , A , RS
0
1
2
S
Bn
D
B
V
O
ꢁV
OUT
EN
C
L
= 1000 pF
V
OUT
D
A
8/4
or
ꢁ
V
is the measured voltage error due to
OUT
4/2
WR I/O
GND
V–
charge injection. The charge injection in Cou-
lombs is Q = C x ꢁV
L
OUT
+
10 ꢂF
100 nF
–3 V
FIGURE 5. Charge Injection
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
11
DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+5 V
+15 V
+
10 ꢂF
100 nF
V
L
V+
EN
S
A2
– S
Bn
8/4, 4/2
RS
V
O
D
A
50 ꢀ
S
A1
V
IN
A
to
0
I/O
A
2
WR
GND
V–
+
10 ꢂF
100 nF
–3 V
FIGURE 6. Bandwidth
8/4 or 4/2 = Logic “0”
S
A1
All Channels Off
D
A
S
A1
D
A
S
An
R
IN
S
An
V
OUT
V
OUT
R
L
S
S
B1
R
75 ꢀ
L
S
B1
Bn
D
B
S
Bn
D
B
V
OUT
V
X
+ 20 log
10
V
TALK(AH)
OUT
V
X
+ 20 log
10
Note: S on or any other one channel on.
A1
TALK(CD)
FIGURE 7. All Hostile Crosstalk
FIGURE 8. Chip Disabled Crosstalk
R
IN
10 W
Channels S and S On
4/2 = Logic “1”
A1
B1
V
Sn–1
S
A1
S
S
S
n–1
D
A
V
OUT
S
R
IN
An
V
Sn
R
L
n
S
D
B
B1
Bn
V
V
Sn+1
S
n+1
R
10 ꢀ
R
10 kꢀ
R
L
IN
L
Signal
Generator
V
V
V
Sn ) 1
OUT
V
Sn – 1
X
+ 20 log
TALK(DIFF)
10
X
+ 20 log
or 20 log
10
TALK(AI)
10
V
V
Sn
Sn
FIGURE 9. Adjacent Input Crosstalk
FIGURE 10. Differential Crosstalk
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
12
DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+15 V
V+
+15 V
+5 V
+5 V
D
A
D
S
V+
B
V
L
S
S
V
L
A1
RS
RS
EN
A2
A1
An
B1
Bn
Meter
Meter
8/4 or 4/2
D
S
S
S
A
HP4192A
Impedance
Analyzer
HP4192A
Impedance
Analyzer
D
B
A
0
or Equivalent
or Equivalent
S
A
1
B1
B2
S
A
2
8/4
or
4/2
I/O WR EN
GND
V–
I/O WR
GND
V–
–3 V
–3 V
FIGURE 11. On State Input Capacitance
FIGURE 12. Off State Input/Output Capacitance
OPERATING VOLTAGE RANGE
22
21
20
19
18
17
16
15
Positive Supply Voltage
Allowable Operating Voltage
14
V+ (Volts)
Area
13
12
11
10
(Note b)
0
–5
–4
–3
–2
–1
–5.5
Negative Supply Voltage
V– (Volts)
Notes:
a. Both V+ and V– must have decoupling capacitors mounted as close as possible to the device pins. Typical decoup-
ling capacitors would be 10-ꢂF tantalum bead in parallel with 100-nF ceramic disc.
b. Production tested with V+ = 15 V and V– = –3 V.
a. For V = 5 V "10%, 0.8- or 2-V TTL compatibility is maintained over the entire operating voltage range.
L
FIGURE 13.
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
13
DG534A/538A
Vishay Siliconix
PIN DESCRIPTION
Pin Number
DG534ADJ DG538A
Symbol
Description
D
A
2
2
Analog Output/Input
V+
3
3
Positive Supply Voltage
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input/Output
4 x 1 or 2 x 2 Select
8 x 1 or 4 x 2 Select
Reset
S
4
4
A1
A2
A3
A4
S
S
S
6
6
–
8
–
10
4/2
8/4
RS
WR
7
–
11
–
8
9
12
13
Write command that latches A, EN
A , A , A
11, 10, –
16, 15, 14
Binary address inputs that determine which channel(s) is/are connected to the out-
put(s)
0
1
2
EN
I/O
12
13
17
Enable. Input/Output, if EN = 0, all channels are open
Input/Output control. Used to write to or read from the address latches
Logic Supply Voltage, usually +5 V
Analog Input/Output
18
V
L
14
19
S
B4
S
B3
S
B2
S
B1
–
20
–
22
Analog Input/Output
15
24
Analog Input/Output
17
26
Analog Input/Output
V–
18
27
28
Negative Supply Voltage
D
B
19
Analog Output/Input
GND
1, 5, 16
1, 5, 7, 9, 21, 23, 25
Analog and Digital Grounds. All grounds should be connected externally to optimize
dynamic performance
APPLICATIONS
Device Description
The DG534A/DG538A are improved pin-compatible
replacements for the non-A versions. Improvements include:
higher current readback drivers, readback of the EN bit,
latchup protection
The DG534A/538A D/CMOS wideband multiplexers offer
single-ended or differential functions. A 8/4 or 4/2 logic input
pin selects the single-ended or differential mode.
Frequency Response
To meet the high dynamic performance demands of video,
high definition TV, digital data routing (in excess of 100 Mbps),
etc., the DG534A/538A are fabricated with DMOS transistors
configured in ‘T’ arrangements with second level ‘L’
configurations (see Functional Block Diagram).
A single multiplexer on-channel exhibits both resistance
[rDS(on)] and capacitance [CS(on)]. This RC combination
causes a frequency dependent attenuation of the analog
signal. The –3-dB bandwidth of the DG534A/538A is typically
500 MHz (into 50 ꢀ ). This figure of 500 MHz illustrates that the
switch-channel cannot be represented by a simple RC
combination. The on capacitance of the channel is distributed
along the on-resistance, and hence becomes a more complex
multi-stage network of R’s and C’s making up the total rDS(on)
Use of DMOS technology yields devices with very low
capacitance and low rDS(on). This directly relates to improved
high frequency signal handling and higher switching speeds,
while maintaining low insertion loss figures. The ‘T’ and ‘L’
switch configurations further improve dynamic performance
by greatly reducing crosstalk and output node capacitances.
and CS(on)
.
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
14
DG534A/538A
Vishay Siliconix
APPLICATIONS (CONT'D)
Power Supplies and Decoupling
a. Use extensive ground planes on double sided PCB
separating adjacent signal paths. Multilayer PCB is even
better.
A useful feature of the DG534A/538A is its power supply
flexibility. It can be operated from unipolar supplies (V–
connected to 0 V) if required. Allowable operating voltage
ranges are shown in Figure 13.
b. Keep signal paths as short as practically possible with all
channel paths of near equal length.
c. Use strip-line layout techniques.
Note that the analog signal must not go below V– by more than
0.3 V (see absolute maximum ratings). However, the addition
of a V– pin has a number of advantages:
Improvements in performance can be obtained by using PLCC
parts instead of DIPs. The stray effects of the quad PLCC
package are lower than those of the dual-in-line packages.
Sockets for the PLCC packages usually increase crosstalk.
a. It allows flexibility in analog signal handling, i.e. with V– =
–5 V and V+ = 15 V, up to "5 V ac signals can be
accepted.
+5 V
51 W
+15 V
b. The value of on capacitance (CS(on)) may be reduced by
increasing the reverse bias across the internal FET body to
51 ꢀ
source junction. V+ has no effect on CS(on)
.
+
+
It is useful to note that tests indicate that optimum video
differential phase and gain occur when V– is –3 V.
C
2
C
C
1
C
2
1
c. V– eliminates the need to bias an ac analog signal using
V
L
V+
S
A1
D
A
potential dividers and large decoupling capacitors.
S
S
A2
It is established rf design practice to incorporate sufficient
bypass capacitors in the circuit to decouple the power supplies
to all active devices in the circuit. The dynamic performance
of the DG534/538 is adversely affected by poor decoupling of
power supply pins. Also, since the substrate of the device is
connected to the negative supply, proper decoupling of this pin
is essential.
D
B
DG534A
B1
S
B2
GND V–
C
1
C
2
+
Rules:
51 ꢀ
a. Decoupling capacitors should be incorporated on all
power supply pins (V+, V–, VL).
C
1
C
2
= 1 ꢂF Tantalum
= 100 nF Polyester
b. They should be mounted as close as possible to the
device pins.
–3 V
c. Capacitors should have good frequency characteristics -
tantalum bead and/or ceramic disc types are suitable.
Recommended decoupling capacitors are 1- to 10-ꢂ F
tantalum bead, in parallel with 100-nF ceramic or
polyester.
FIGURE 14. DG534A Power Supply Decoupling
Interfacing
d. Additional high frequency protection may be provided by
51-ꢀ carbon film resistors connected in series with the
power supply pins (see Figure 14).
Logic interfacing is easily accomplished. Comprehensive
addressing and control functions are incorporated in the
design.
Board Layout
The VL pin permits interface to various logic types. The device
is primarily designed to be TTL or CMOS logic compatible with
+5 V applied to VL. The actual logic threshold can be raised
simply by increasing VL.
PCB layout rules for good high frequency performance must
also be observed to achieve the performance boasted by the
DG534A/538A. Some tips for minimizing stray effects are:
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
15
DG534A/538A
Vishay Siliconix
APPLICATIONS (CONT'D)
A typical switching threshold versus VL is shown in Figure 15.
Channel address data can only be entered during WR low,
when the address latches are transparent and I/O is low.
Similarly, address readback is only operational when WR and
I/O are high.
These devices feature an address readback (Tally) facility,
whereby the last address written to the device may be output
to the system. This allows improved status monitoring and
hand shaking without additional external components.
The Siliconix CLC410 Video amplifier is recommended as an
output buffer to reduce insertion loss and to drive coaxial
cables. For low power video routing applications or for unity
gain input buffers CLC111/CLC114 are recommended.
This function is controlled by the I/O pin, which directly
addresses the tri-state buffers connected to the EN and
address pins. EN and address pins can be assigned to accept
data (when I/O = 0; WR = 0; RS = 1), or output data (when I/O =
1; WR = 1; RS = 1), or to reflect a high impedance and latched
state (when I/O = 0; WR = 1; RS = 1).
8
7
6
5
When I/O is high, the address output can sink or source
current. Note that VL is the logic high output condition. This
point must be respected if VL is varied for input logic threshold
shifting.
V
(V)
th
4
3
2
1
0
Further control pins facilitate easy microprocessor interface.
On chip address, data latches are activated by WR, which
serves as a strobe type function eliminating the need for
peripheral latch or memory I/O port devices. Also, for ease of
interface, a direct reset function (RS) allows all latches to be
cleared and switches opened. Reset should be used during
power up, etc., to avoid spurious switch action. See Figure 16.
0
2
4
6
8
10 12 14 16 18
(V)
V
L
FIGURE 15. Switching Threshold Voltage vs. V
L
DG534A
S
S
CLC410
A1
75 ꢀ
B2
D
A
B
A , A
0
1
A
V
= 2
EN
CLC410
D
RS
75 ꢀ
Data Bus
WR
Reset
WR
Address Bus
DG534A
S
S
A1
CLC410
CLC410
75 ꢀ
B2
D
A
B
A , A
0
1
Address
Decoder
EN
I/O
RS
D
WR
75 ꢀ
Video
Bus
Data
Bus
FIGURE 16. DG534A in a Video Matrix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
16
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