CRCW060310K0JNEA_技术文档

SiC403

Vishay Siliconix

microBUCK^®SiC403

6 A, 28 V Integrated Buck Regulator with Programmable LDO

DESCRIPTION

FEATURES

•

High efficiency > 95 %

The Vishay Siliconix SiC403 is an advanced stand-alone

synchronous buck regulator featuring integrated power

MOSFETs, bootstrap switch, and a programmable LDO in a

space-saving MLPQ 5 x 5 - 32 pin package.

6 A continuous output current capability

Integrated bootstrap switch

Programmable 200 mA LDO with bypass logic

Temperature compensated current limit

Pseudo fixed-frequency adaptive on-time control

All ceramic solution enabled

The SiC403 is capable of operating with all ceramic solutions

and switching frequencies up to 1 MHz. The programmable

frequency, synchronous operation and selectable

power-save allow operation at high efficiency across the full

range of load current. The internal LDO may be used to

supply 5 V for the gate drive circuits or it may be bypassed

with an external 5 V for optimum efficiency and used to drive

external n-channel MOSFETs or other loads. Additional

features include cycle-by-cycle current limit, voltage

Programmable input UVLO threshold

Independent enable pin for switcher and LDO

Selectable ultra-sonic power-save mode

Programmable soft-start

Soft-shutdown

soft-start,

under-voltage

protection,

programmable

1 % internal reference voltage

over-current protection, soft shutdown and selectable

power-save. The Vishay Siliconix SiC403 also provides an

enable input and a power good output.

Power good output

Under and over voltage protection

Material categorization: For definitions of compliance

please see www.vishay.com/doc?99912

PRODUCT SUMMARY

Input Voltage Range

Output Voltage Range

Operating Frequency

Continuous Output Current

Peak Efficiency

3 V to 28 V

0.75 V to 5.5 V

200 kHz to 1 MHz

6 A

APPLICATIONS

•

Notebook, desktop, and server computers

Digital HDTV and digital consumer applications

Networking and telecommunication equipment

Printers, DSL, and STB applications

Embedded applications

95 % at 300 kHz

MLPQ 5 mm x 5 mm

Package

Point of load power supplies

TYPICAL APPLICATION CIRCUIT

3.3 V

EN/PSV (Tri-State)

P

GOOD

LDO_EN

V

OUT

31 30 29 28 27 26 25

32

V

OUT

LX

FB

24

23

22

21

20

19

18

17

1

V

OUT

PAD 1

2

3

4

5

6

7

8

V

P

DD

GND

A

GND

A

P

GND

PAD 3

LX

P

FBL

GND

V

IN

PAD 2

V

IN

SS

V

IN

GND

BST

P

SiC403 (MLP 5 x 5-32L)

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

Vishay Siliconix

PIN CONFIGURATION (TOP VIEW)

31 30 29 28 27 26 25

32

LX

1

2

3

4

5

6

7

8

FB

24

23

PAD 1

V

OUT

LX

P

A

V

GND

DD

22

21

GND

PAD 3

A

P

GND

FBL

LX

20

19

18

17

PAD 2

V

P

IN

GND

V

IN

SS

BST

PIN DESCRIPTION

Pin Number

Symbol

Description

Feedback input for switching regulator. Connect to an external resistor divider from output to program

output voltage.

1

FB

2

V_OUT

V_DD

Output voltage input to the controller. Additionally may be used to by pass LDO to supply V_DDdirectly.

Bias for internal logic circuitry and gate drivers. Connect to external 5V power supply or configure

the internal LDO for 5 V.

3

4, 30, PAD 1

5

A_GND

FBL

Analog ground

Feedback input for internal LDO. Connect to an external resistor divider from V_DDto A_GNDto program

LDO output.

6, 9-11, PAD 2

V_IN

SS

Power stage input (HS FET Drain)

7

Connect to an external capacitor to A_GNDto program softstart ramp

Bootstrap pin. A capacitor is connected between BST and LX to provide HS driver voltage.

Not internally connected

8

BST

NC

12

13, 23-25, 28, PAD 3

LX

Switching node (HS FET Source and LS FET Drain)

Not internally connected

14

15-22

26

NC

P_GND

P_GOOD

I_LIM

Power ground (LS FET Source)

Open-drain power good indicator. Externally pull-up resistor is required.

Connect to an external resistor between I_LIMand LX to program over current limit

27

Tri-state pin. Pull low to A_GNDto disable the regulator. Float to enable forced continuous current

mode. Pull high to V_DDto enable power save mode.

29

EN/PSV

31

32

T_ON

ENL

Connect to an external resistor to A_GNDprogram on-time

Enable input for internal LDO. Pull down to A_GNDto disable internal LDO.

ORDERING INFORMATION

Part Number

SiC403CD-T1-GE3

SiC403DB

Package

MLPQ55-32

Evaluation board

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Document Number: 66550

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SiC403

Vishay Siliconix

FUNCTIONAL BLOCK DIAGRAM

6, 9-11, PAD 2

29

EN/PSV

26

P

GOOD

V

IN

V

IN

A

V

DD

GND

4, 30,

PAD 1

V

DD

BST

Reference

Soft Start

8

Control and Status

DL

SS

7

LX

13, 23 to 25,

28, PAD 3

+

-

On-Time

Generator

Gate Drive

Control

FB

V

DD

1

FB Comparator

P

GND

T

ON

31

2

15 to 22

Zero Cross

Detector

V

OUT

I

LIM

Valley1-Limit

27

Bypass Comparator

V

DD

V

DD

V

IN

A

Y

3

B

MUX

LDO

FBL

ENL

32

5

ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)

A

Parameter

Symbol

Min.

- 0.3

- 2

Max.

+ 30

Unit

LX to P_GNDVoltage

V_LX

LX to P_GNDVoltage (transient - 100 ns)

V_LX

V

_INto P_GNDVoltage

V_IN

- 0.3

EN/PSV, P_GOOD, I_LIM, to A_GND

V_DD+ 0.3

+ 6

BST Bootstrap to LX; V_DDto P_GND

V

A_GNDto P_GND

V_AG-PG

+ 0.3

EN/PSV, P_GOOD, I_LIM, V_OUT, V_LDO, FB, FBL to GND

+ (V_DD+ 0.3)

+ (V_DD- 1.5)

+ 35

t_ONto P_GND

BST to P_GND

- 0.3

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is

not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min.

3

Typ.

Max.

28

Unit

Input Voltage

V_IN

V

_DDto P_GND

V_DD

3

5.5

V

_OUTto P_GND

V_OUT

0.75

Note:

For proper operation, the device should be used within the recommended conditions.

THERMAL RESISTANCE RATINGS

Parameter

Symbol

T_STG

T_J

Min.

- 40

-

Typ.

Max.

Unit

Storage Temperature

+ 150

150

Maximum Junction Temperature

Operation Junction Temperature

°C

T_J

- 25

+ 125

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SiC403

Vishay Siliconix

THERMAL RESISTANCE RATINGS

Parameter

Thermal Resistance, Junction-to-Ambient^b

High-Side MOSFET

Low-Side MOSFET

Symbol

Min.

Typ.

Max.

Unit

°C/W

°C

25

20

50

PWM Controller and LDO Thermal Resistance

Peak IR Reflow Temperature

Notes:

T_Reflow

-

260

a. This device is ESD sensitive. Use of standard ESD handling precautions is required.

b. Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters

specififed in the Electrical Characteristics section is not recommended.

ELECTRICAL SPECIFICATIONS

Test Conditions Unless Specified

V

_IN= 12 V, V_DD= 5 V, T_A= + 25 °C for typ.,

- 40 °C to + 85 °C for min. and max.,

T_J= < 125 °C

Parameter

Symbol

Min.

Typ.

Max.

Unit

Input Supplies

V_{IN_UV+}

V_{IN_UV-}

Sensed at ENL pin, rising edge

Sensed at ENL pin, falling edge

EN/PSV = High

2.4

2.6

2.4

0.2

2.8

2.6

0.2

8.5

2.95

V_INUVLO Threshold Voltage^a

V_INUVLO Hysteresis

2.235

2.565

V_{IN_UV_HY}

V_{DD_UV+}

V_{DD_UV-}

V

Measured at V_DDpin, rising edge

Measured at V_DDpin, falling edge

2.5

2.4

3

V

_DDUVLO Threshold Voltage

2.9

V_DDUVLO Hysteresis

V_INSupply Current

V_{DD_UV_HY}

EN/PSV, ENL = 0 V, V_IN= 28 V

20

7

I_IN

Standby mode:

ENL = V_DD, EN/PSV = 0 V

130

3

µA

EN/PSV, ENL = 0 V

EN/PSV = V_DD, no load (f_SW= 25 kHz),

2

V

_DDSupply Current

I_VDD

V_FB> 750 mV

mA

f_SW= 250 kHz, EN/PSV = floating, no load^b

25°C bench testing

10

Controller

FB On-Time Threshold

Frequency Range^b

Bootstrap Switch Resistance

Timing

V_FB-TH

F_PWM

Static V_INand load, - 40 °C to + 85 °C

continuous mode, 25°C bench testing

0.7425 0.750 0.7599

V

kHz



200

1000

10

Continuous mode operation V_IN= 15 V,

On-Time

t_ON

2386

2650

2915

V

_OUT= 5 V, R_ton= 300 k

25°C bench testing

ns

Minimum On-Time^b

Minimum Off-Time^b

t_ON

80

t_OFF

320

Soft Start

Soft Start Current^b

I_OUT= I_LIM/2, 25°C bench testing

2.75

500

0.5

µA

k

mV

I_SS

Analog Inputs/Outputs

V_OUTInput Resistance

Current Sense

R_O-IN

Zero-Crossing Detector Threshold Voltage

Power Good

V_Sense-th

LX-P_GND

- 3.5

+ 3.5

PG_V_{TH_UPPER}

PG_V_{TH_LOWER}

Power Good Threshold Voltage

V_FB> internal reference 750 mV

+ 20

%

Power Good Threshold Voltage

Start-Up Delay Time

Fault (noise-immunity) Delay Time^b

Power Good Leakage Current

Power Good On-Resistance

V_FB< internal reference 750 mV

C_ss= 10 nF

- 10

12

5

PG_T_d

PG_I_CC

ms

µs

µA



V_EN= 0 V, 25°C bench testing

V_EN= 0 V

PG_I_LK

1

PG_R_DS-ON

V_EN= 0 V

10

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Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

Vishay Siliconix

ELECTRICAL SPECIFICATIONS

Test Conditions Unless Specified

_IN= 12 V, V_DD= 5 V, T_A= + 25 °C for typ.,

- 40 °C to + 85 °C for min. and max.,

T_J= < 125 °C

V

Parameter

Symbol

Min.

Typ.

Max.

Unit

Fault Protection

I_LIMSource Current

I_LIM

8

6

µA

A

R_ILIM= 6 kV_DD= 5 V,

25°C bench testing

Valley Current Limit

4.5

7.2

V_FBwith respect to Internal 500 mV

reference, 8 consecutive clocks

Output Under-Voltage Fault

V_{OUV_Fault}

P_{SAVE_VTH}

- 25

+ 10

+ 20

%

Smart Power-Save Protection

Threshold Voltage^b

V_FBwith respect to internal 500 mV

reference, 25°C bench testing

V

_FBwith respect to internal 500 mV

reference

Over-Voltage Protection Threshold

Over-Voltage Fault Delay^b

Over Temperature Shutdown^b

Logic Inputs/Outputs

Logic Input High Voltage

Logic Input Low Voltage

EN/PSV Input Bias Current

ENL Input Bias Current

FBL, FB Input Bias Current

Linear Dropout Regulator

FBL Accuracy

25°C bench testing

5

µs

°C

t_OV-Delay

T_Shut

10 °C hysteresis, 25°C bench testing

150

V_IH

V_IL

1

EN, ENL, PSV

V

0.4

+ 10

18

I_EN

EN/PSV = V_DDor A_GND

V_IN= 28 V

- 10

- 1

I_ENL

11

µA

FBL_I_LK

FBL, FB = V_DDor A_GND

+ 1

FBL_ACC

V_LDOload = 10 mA

0.735 0.750 0.765

115

V

Start-up and foldback, V_IN= 12 V

Operating current limit, V_IN= 12 V

LDO Current Limit

LDO_I_LIM

mA

134

- 130

- 500

200

V_LDOto V_OUTSwitch-Over Threshold^c

V_LDOto V_OUTNon-Switch-Over Threshold^c

V_LDOto V_OUTSwitch-Over Resistance

+ 130

+ 500

V_LDO-BPS

V_LDO-NBPS

R_LDO

mV



V_OUT= 5 V

2

From V_INto V_VLDO, V_VLDO= + 5 V,

LDO Drop Out Voltage^d

1.2

V

I

_VLDO= 100 mA

Notes:

a. V_{IN UVLO}is programmable using a resistor divider from V_INto ENL to A_GND. The ENL voltage is compared to an internal reference.

b. Guaranteed by design.

c. The switch-over threshold is the maximum voltage diff erential between the V_LDOand V_OUTpins which ensures that V_LDOwill internally

switch-over to V_OUT. The non-switch-over threshold is the minimum voltage diff erential between the V_LDOand V_OUTpins which ensures that

V

_LDOwill not switch-over to V_OUT.

d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.

Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vishay.com

S12-0628-Rev. C, 19-Mar-12

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SiC403

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

90

80

70

60

50

40

30

90

80

70

60

50

40

30

20

10

0

V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz

10

0

0.01

0.1

1

10

0.01

0.1

1

10

I_OUT(A)

Efficiency vs. I_OUT

(in Continuous Conduction Mode)

(in Power-Save-Mode)

1.008

1.006

1.004

1.002

1

1.006

1.004

1.002

1

V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz

0.998

0.996

0.994

0.992

0.998

0.996

0.994

0.992

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

I

(A)

I_OUT(A)

OUT

V_OUTvs. I_OUT

(in Continuous Conduction Mode)

(in Power-Save-Mode)

1.05

1.04

1.03

1.02

1.01

1

1.012

1.010

1.008

1.006

1.004

1.002

1

0.99

0.98

0.97

0.96

0.95

V_OUT= 1 V, FSW = 500 kHz,

Continuous Conduction Mode

V_OUT= 1 V, FSW = 500 kHz,

Continuous Conduction Mode

0.998

5

7

9

11

13

15

17

19

21

23

5

7

9

11

13

V

15

_IN(V)

17

19

21 23

V_IN(V)

V

_OUTvs. V_INat I_OUT= 0 A

V

_OUTvs. V_INat I_OUT= 6 A

(in Continuous Conduction Mode, FSW = 500 kHz)

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Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC403

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

40

35

30

25

20

15

10

5

1.1

1.05

V_OUT= 1 V, I_OUT= 6 A, FSW = 500 kHz

1

V_OUT= 1 V, FSW = 500 kHz, Power Saving Mode

0.95

0.9

0

5

10

15

20

25

6

8

10 12 14 16 18 20 22 24

V_IN(V)

V_OUTvs. V_IN

V_OUTRipple vs. V_IN

(I_OUT= 0 A in Power-Save-Mode)

(I_OUT= 6 A in Continuous Conduction Mode)

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

V_OUT= 1 V, I_OUT= 0 A, FSW = 500 kHz

V_OUT=1 V, I_OUT= 0 A, FSW = 500 kHz

0

5

10

15

20

25

6

8

10

12

14

V_IN(V)

16

18

20

V_IN(V)

V_OUTRipple vs. V_IN

(I_OUT= 0 A in Continuous Conduction Mode)

V_OUTRipple vs. V_IN

(I_OUT= 0 A in Power-Save-Mode)

550

530

510

490

470

450

430

410

390

370

350

600

500

400

300

200

100

0

V_IN= 12 V, V_OUT= 1 V

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

I_OUT(A)

FSW vs. I_OUT

(in Continuous Conduction Mode)

FSW vs. I_OUT

(in Power-Save-Mode)

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

Ch2: Output ripple Voltage (20mV/div)

Ch1: LX Switching Node (5V/div)

Ch2: Output ripple Voltage (20mV/div)

Ch1: LX Switching Node (5V/div)

Time: 2 μs/div

Time: 20 μs/div

V_OUTRipple in Power Save Mode (No Load)

(V_IN= 12 V, V_OUT= 1 V)

V_OUTRipple in Continuous Conduction Mode (No Load)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

Ch3: Output Current (2A/div)

Ch2: Output Voltage (50mV/div)

Time: 5 μs/div

Transient Response in Continuous Conduction Mode

(0.2 A to 6 A)

Time: 5 μs/div

Transient Response in Continuous Conduction Mode

(6 A to 0.2 A)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

Ch3: Output Current (2A/div)

Ch2: Output Voltage (50mV/div)

Time: 10 μs/div

Transient Response in Power Save Mode

(6 A to 0.2 A)

Time: 10 μs/div

Transient Response in Power Save Mode

(0.2 A to 6 A)

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz at 6 A)

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SiC403

Vishay Siliconix

ELECTRICAL CHARACTERISTICS

Ch4: Vin (5V/div)

Ch4: Iout (10A/div)

Ch2: Vout (500mV/div)

Ch3: Power Good (5V/div)

Ch1: Switching Node (5V/div)

Ch2: Vout (1V/div)

Ch3: Power good (5V/div)

Ch1: Switching Node (10V/div)

Time: 10 ms/div

Start-up with V_INRamping up

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz)

Over-Current Protection

(V_IN= 12 V, V_OUT= 1 V, FSW = 500 kHz )

100

95

90

85

80

75

V_IN= 12 V, V_OUT= 5 V, FSW = 300 kHz

70

0

1

2

3

4

5

6

7

I_OUT(A)

Efficiency with 12 V_IN, 5 V_OUT, 300 kHz

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

Vishay Siliconix

APPLICATIONS INFORMATION

SiC403 Synchronous Buck Converter

t

ON

V

The SiC403 is a step down synchronous buck DC/DC

converter with integrated power FETs and programmable

LDO. The SiC403 is capable of 6 A operation at very high

efficiency in a tiny 5 mm x 5 mm - 32 pin package. The

programmable operating frequency range of 200 kHz to

1 MHz, enables the user to optimize the solution for minimum

board space and optimum efficiency.

The buck controller employs pseudo-fixed frequency

adaptive on-time control. This control scheme allows fast

transient response thereby lowering the size of the power

components used in the system.

IN

V

LX

C

IN

V

FB

Q1

Q2

FB threshold

V

LX

V

OUT

L

ESR

FB

+

C

OUT

Input Voltage Range

The SiC403 requires two input supplies for normal operation:

V_INand V_DD. V_INoperates over the wide range from 3 V to

28 V. V_DDrequires a supply voltage between 3 V to 5 V that

can be an external source or the internal LDO configured

from V_IN.

Figure 1 - Output Ripple and PWM Control Method

The adaptive on-time control has significant advantages over

traditional control methods used in the controllers today.

• Reduced component count by eliminating DCR sense or

current sense resistor as no need of a sensing inductor

current.

• Reduced saves external components used for

compensation by eliminating the no error amplifier and

other components.

• Ultra fast transient response because of fast loop,

absence of error amplifier speeds up the transient

response.

• Predictable frequency spread because of constant on-time

architecture.

Power Up Sequence

The SIC403 initiates a start up when V_IN, V_DD, and EN/PSV

pins are above the applicable thresholds. When using an

external bias supply for the V_DDvoltage, it is recommended

that the V_DDis applied to the device only after the V_INvoltage

is present because V_DDcannot exceed V_INat any time. A 10

resistor must be placed between the external V_DDsupply and

the V_DDpin to avoid damage to the device during power-up

and or shutdown situations where V_DDcould exceed V_IN

unexpectedly.

Shut-Down

• Fast transient response enables operation with minimum

output capacitance

Overall, superior performance compared to fixed frequency

architectures.

The SIC403 can be shut-down by pulling either V_DDor

EN/PSV pin below its threshold. When using an external

supply voltage for V_DD, the V_DDpin must be deactivated

while the V_INvoltage is still present. A 10 resistor must be

placed between the external V_DDsupply and the V_DDpin to

avoid damage to the device.

On-Time One-Shot Generator (t_ON

Frequency

) and Operating

When the V_DDpin is active and EN/PSV is at low logic level,

the output voltage discharges through an internal FET.

The SiC403 have an internal on-time one-shot generator

which is a comparator that has two inputs. The FB

Comparator output goes high when V_FBis less than the

internal 750 mV reference. This feeds into the gate drive and

turns on the high-side MOSFET, and also starts the one-shot

timer. The one-shot timer uses an internal comparator and a

capacitor. One comparator input is connected to V_OUT, the

other input is connected to the capacitor. When the on-time

begins, the internal capacitor charges from zero volts

through a current which is proportional to V_IN. When the

capacitor voltage reaches V_OUT, the on-time is completed

and the high-side MOSFET turns off. The figure 2 shows the

on-chip implementation of on-time generation.

Pseudo-Fixed Frequency Adaptive On-Time Control

The PWM control method used for the SiC403 is

pseudo-fixed frequency, adaptive on-time, as shown in

figure 1. The ripple voltage generated at the output capacitor

ESR is used as a PWM ramp signal. This ripple is used to

trigger the on-time of the controller.

The adaptive on-time is determined by an internal oneshot

timer. When the one-shot is triggered by the output ripple, the

device sends a single on-time pulse to the highside

MOSFET. The pulse period is determined by V_OUTand V_IN;

the period is proportional to output voltage and inversely

proportional to input voltage. With this adaptive on-time

arrangement, the device automatically anticipates the

on-time needed to regulate V_OUTfor the present V_IN

condition and at the selected frequency.

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SiC403

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Gate

drives

2

R₁

R₂

V_RIPPLE

2

1 + (R₁ωC_TOP)

FB comparator

-

V_OUT= 0.75 x 1 +

+

x

2

FB

750 mV

R₂x R₁

1 +

ωC_TOP

+

Q1

LX

R₂+ R₁

DH

DL

V

L

OUT

V

Enable and Power-Save Inputs

V

ESR

OUT

FB

The EN/PSV and ENL inputs are used to enable or dis-

One-shot

timer

Q2

V

IN

+

C

able the switching regulator and the LDO.

R

ton

On-time = K x R x (V

V )

OUT/ IN

When EN/PSV is low (grounded), the switching regulator is

off and in its lowest power state. When off, the output of the

switching regulator soft-discharges the output into a 15 

internal resistor via the V_OUTpin.

ton

Figure 2 - On-Time Generation

When EN/PSV is allowed to float, the pin voltage will float to

1.5 V. The switching regulator turns on with power-save

disabled and all switching is in forced continuous mode.

When EN/PSV is high (above 2 V), the switching regulator

turns on with ultra-sonic power-save enabled. The SiC403

ultra-sonic power-save operation maintains a minimum

switching frequency of 25 kHz, for applications with stringent

audio requirements.

This method automatically produces an on-time that is

proportional to V_OUTand inversely proportional to V_IN.

Under steady-state conditions, the switching frequency can

be determined from the on-time by the following equation.

V

ON

OUT

x V

IN

f

sw

=

t

The ENL input is used to control the internal LDO. This input

serves a second function by acting as a V_{IN UVLO}sensor for

the switching regulator.

The LDO is off when ENL is low (grounded). When ENL is a

logic high but below the V_{IN UVLO}threshold (2.6 V typical),

then the LDO is on and the switcher is off. When ENL is

above the V_{IN UVLO}threshold, the LDO is enabled and the

switcher is also enabled if the EN/PSV pin is not grounded.

The SiC403 uses an external resistor to set the ontime

which indirectly sets the frequency. The on-time can be pro-

grammed to provide operating frequency from 200 kHz to 1

MHz using a resistor between the t_ONpin and ground. The

resistor value is selected by the following equation.

(t - 10 ns) x V

ON

IN

R

=

ton

25 pF x V

OUT

Forced Continuous Mode Operation

The maximum R_tONvalue allowed is shown by the following

equation.

The SiC403 operates the switcher in Forced Continuous

Mode (FCM) by floating the EN/PSV pin (see figure 4). In this

mode one of the power MOSFETs is always on, with no

intentional dead time other than to avoid cross-conduction.

This feature results in uniform frequency across the full load

range with the trade-off being poor efficiency at light loads

due to the high-frequency switching of the MOSFETs.

V

IN_MIN

R

=

ton_MAX

15 µA

V_OUTVoltage Selection

The switcher output voltage is regulated by comparing V_OUT

as seen through a resistor divider at the FB pin to the internal

750 mV reference voltage, see figure 3.

FB ripple

FB threshold

(750 mV)

voltage (VFB

)

V_OUT

to FB pin

R₁

DC load current

Inductor

current

R₂

DH on-time is triggered when

reaches the FB threshold

On-time

(t

V

Figure 3 - Output Voltage Selection

FB

)

ON

As the control method regulates the valley of the output ripple

voltage, the DC output voltage V_OUTis off set by the output

ripple according to the following equation.

DH

DL

R₁

R₂

V_RIPPLE

2

V_OUT= 0.75 x 1 +

+

DL drives high when on-time is completed.

DL remains high until V falls to the FB threshold.

FB

When a large capacitor is placed in parallel with R1 (C_TOP

)

Figure 4 - Forced Continuous Mode Operation

V_OUTis shown by the following equation.

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SiC403

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Ultrasonic Power-Save Operation

The SiC403 provides ultra-sonic power-save operation at

light loads, with the minimum operating frequency fixed at

25 kHz. This is accomplished using an internal timer that

monitors the time between consecutive high-side gate

pulses.

If the time exceeds 40 µs, DL drives high to turn the low-side

MOSFET on. This draws current from V_OUTthrough the

inductor, forcing both V_OUTand V_FBto fall. When V_FBdrops

to the 750 mV threshold, the next DH on-time is triggered.

After the on-time is completed the high-side MOSFET is

turned off and the low-side MOSFET turns on, the low-side

MOSFET remains on until the inductor current ramps down

to zero, at which point the low-side MOSFET is turned off.

minimum f

25 kHz

SW

~

FB ripple

voltage (VFB

Figure 6 - Ultrasonic Power-Save Operation Mode

)

FB threshold

(750 mV)

Figure 6 shows the behavior under power-save and

continuous conduction mode at light loads.

Smart Power-Save Protection

(0A)

Inductor

current

Active loads may leak current from a higher voltage into the

switcher output. Under light load conditions with

power-save-power-save enabled, this can force V_OUTto

slowly rise and reach the over-voltage threshold, resulting in

a hard shutdown. Smart power-save prevents this condition.

When the FB voltage exceeds 10 % above nominal (exceeds

825 mV), the device immediately disables power-save, and

DL drives high to turn on the low-side MOSFET. This draws

current from V_OUTthrough the inductor and causes V_OUTto

fall. When V_FBdrops back to the 750 mV trip point, a normal

t_ONswitching cycle begins.

This method prevents a hard OVP shutdown and also cycles

energy from V_OUTback to V_IN. It also minimizes operating

power by avoiding forced conduction mode operation.

Figure 7 shows typical waveforms for the smart power-save

feature.

DH on-time is triggered when

reaches the FB threshold

On-time

(t

V

FB

)

ON

DH

DL

After the 40 µs time-out, DL drives high if V

has not reached the FB threshold.

FB

Figure 5 - Ultrasonic power-save Operation

Because the on-times are forced to occur at intervals no

greater than 40 µs, the frequency will not fall below ~ 25 kHz.

Figure 5 shows ultra-sonic power-save operation.

V

drifts up to due to leakage

OUT

current flowing into C

OUT

V

discharges via inductor

OUT

Smart power save

threshold (825 mV)

and low-side MOSFET

Benefits of Ultrasonic Power-Save

Having a fixed minimum frequency in power-save has some

significant advantages as below:

• The minimum frequency of 25 kHz is outside the audible

range of human ear. This makes the operation of the

SiC403 very quiet.

• The output voltage ripple seen in power-save mode is

significant lower than conventional power-save, which

improves efficiency at light loads.

Normal V ripple

OUT

FB

threshold

DH and DL off

High-side

drive (DH)

Single DH on-time pulse

after DL turn-off

Low-side

drive (DL)

• Lower ripple in power-save also makes the power

component selection easier.

DL turns on when smart

PSAVE threshold is reached

Normal DL pulse after DH

on-time pulse

DL turns off FB

threshold is reached

Figure 7 - Smart Power-Save

Current Limit Protection

The SiC403 features programmable current limit capability,

which is accomplished by using the R_DS(ON)of the lower

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SiC403

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MOSFET for current sensing. The current limit is set by R_ILIM

resistor. The R_ILIMresistor connects from the I_LIMpin to the

LX pin which is also the drain of the low-side MOSFET.

When the low-side MOSFET is on, an internal ~ 10 µA

current flows from the I_LIMpin and the R_ILIMresistor, creating

a voltage drop across the resistor. While the low-side

MOSFET is on, the inductor current flows through it and

creates a voltage across the R_DS(ON). The voltage across the

MOSFET is negative with respect to ground.

pulse when the voltage at the FB pin is less than 50 % of the

SS pin. As result, the output voltage follows the SS start volt-

age. The output voltage reaches and maintains regulation

when the soft start voltage is > 1.5 V. The time between the

first LX pulse and when V_OUTmeets regulation is the soft

start time (t_SS). The calculation for the soft-start time is

shown by the following equation:

1.5 V

t_SS= C_SS

x

2.75 μA

If this MOSFET voltage drop exceeds the voltage across

R

_ILIM, the voltage at the I_LIMpin will be negative and current

Power Good Output

limit will activate. The current limit then keeps the low-side

MOSFET on and will not allow another high-side on-time,

until the current in the low-side MOSFET reduces enough to

bring the I_LIMvoltage back up to zero. This method regulates

the inductor valley current at the level shown by I_LIMin

figure 8.

The power good (P_GOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage is

10 % below the nominal voltage, P_GOODis pulled low. It is

held low until the output voltage returns above - 8 % of nom-

inal. P_GOODis held low during start-up and will not be allowed

to transition high until soft-start is completed (when V_FB

reaches 750 mV) and typically 2 ms has passed.

I

PEAK

I

P_GOODwill transition low if the V_FBpin exceeds + 20 % of

nominal, which is also the over-voltage shutdown threshold

(900 mV). P_GOODalso pulls low if the EN/PSV pin is low

when V_DDis present.

LOAD

I

LIM

Time

Output Over-Voltage Protection

Figure 8 - Valley Current Limit

Over-voltage protection becomes active as soon as the

device is enabled. The threshold is set at 750 mV + 20 %

(900 mV). When V_FBexceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off , until the EN/PSV input is

toggled or V_DDis cycled. There is a 5 µs delay built into the

OVP detector to prevent false transitions. P_GOODis also low

after an OVP event.

Setting the valley current limit to 6 A results in a 6 A peak

inductor current plus peak ripple current. In this situation, the

average (load) current through the inductor is 6 A plus

one-half the peak-to-peak ripple current.

The internal 10 µA current source is temperature

compensated at 4100 ppm in order to provide tracking with

the R_DS(ON). The R_ILIMvalue is calculated by the following

equation.

Output Under-Voltage Protection

When V_FBfalls 25 % below its nominal voltage (falls to

562.5 mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tristate

the MOSFETs. The controller stays off until EN/PSV is

toggled or V_DDis cycled.

R_ILIM= 1176 x I_LIMx [0.088 x (5V - V_DD) + 1] ()

where I_LIMis in A.

When selecting a value for RILIM do not exceed the absolute

maximum voltage value for the ILIM pin.

V

_DDUVLO, and POR

Under-voltage lock-out (UVLO) circuitry inhibits switching

and tri-states the DH/DL drivers until V_DDrises above 3 V.

An internal Power-On Reset (POR) occurs when V_DD

exceeds 3 V, which resets the fault latch and soft-start

counter to prepare for soft-start. The SiC403 then begins a

soft-start cycle. The PWM will shut off if V_DDfalls below

2.4 V.

Note that because the low-side MOSFET with low R_DS(ON)is

used for current sensing, the PCB layout, solder

connections, and PCB connection to the LX node must be

done carefully to obtain good results. Refer to the layout

guidelines for information.

Soft-Start of PWM Regulator

LDO Regulator

SiC403 has a programmable soft-start time that is controlled

by an external capacitor at the SS pin. After the controller

meets both UVLO and EN/PSV thresholds, the controller has

an internal current source of 2.75 µA flowing through the

SS pin to charge the capacitor. During the start up process,

50 % of the voltage at the SS pin is used as the reference for

the FB comparator. The PWM comparator issues an on-time

SIC403 has an option to bias the switcher by using an

internal LDO from V_IN. The LDO output is connected to V_DD

internally. The output of the LDO is programmable by using

external resistors from the V_DDpin to A_GND. The feedback

pin (FBL) for the LDO is regulated to 750 mV (see figure 9).

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SiC403

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V_DD

to FBL pin

R_LDO1

R_LDO2

Figure 9 - LDO Voltage Divider

The LDO output voltage is set by the following equation.

R

LDO1

LDO2

V

= 750 mV x 1 +

LDO

(

)

Figure 10 - ENL Threshold

A minimum 0.1 µF capacitor referenced to A_GNDis equired

along with a minimum 1 µF capacitor referenced to P_GNDto

filter the gate drive pulses. Refer to the layout guidelines

section for component placement suggestions.

.

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

• ENL pin

• V_INinput voltage

LDO ENL Functions

The ENL input is used to control the internal LDO. When ENL

is low (grounded), the LDO is off. When ENL is above the V_IN

UVLO threshold, the LDO is enabled and the switcher is also

enabled if EN/PSV and V_DDmeet the thresholds.

The ENL pin also acts as the switcher UVLO (undervoltage

lockout) for the V_INsupply. The V_INUVLO voltage is

programmable via a resistor divider at the V_IN, ENL and

A_GNDpins.

If the ENL pin transitions from high to low within 2 switching

cycles and is less than 1 V, then the LDO will turn off but the

switcher remains on. If the ENL goes below the V_INUVLO

threshold and stays above 1 V, then the switcher will turn off

but the LDO remains on. The V_INUVLO function has a typical

threshold of 2.6 V on the V_INrising edge. The falling edge

threshold is 2.4 V.

When the ENL pin is high and V_INis above the UVLO point,

the LDO will begin start-up. During the initial phase, when the

V_DDvoltage (which is the LDO output voltage) is less than

0.75 V, the LDO initiates a current-limited start-up (typically

65 mA) to charge the output capacitors while protecting from

a short circuit event. When V_DDis greater than 0.75 V but still

less than 90 % of its final value (as sensed at the FBL pin),

the LDO current limit is increased to ~ 115mA. When V_DD

has reached 90 % of the final value (as sensed at the FBL

pin), the LDO current limit is increased to ~ 200 mA and the

LDO output is quickly driven to the nominal value by the

internal LDO regulator. It is recommended that during LDO

start-up to hold the PWM switching off until the LDO has

reached 90 % of the final value. This prevents overloading

the current-limited LDO output during the LDO start-up.

Due to the initial current limitations on the LDO during power

up (figure 11), any external load attached to the V_DDpin must

be limited to 20 mA before the LDO has reached 90 % of it

final regulation value.

Note that it is possible to operate the switcher with the LDO

disabled, but the ENL pin must be below the logic low

threshold (0.4 V max.). In this case, the UVLO function for

the input voltage cannot be used. The table below

summarizes the function of the ENL and EN pins, with

respect to the rising edge of ENL.

LDO

Status

Switcher

Status

EN

ENL

Low

High

Low

High

Low

High

Low, < 0.4 V

High, < 2.6 V

High, > 2.6 V

Off

On

Off

On

Off

On

Figure 11 - LDO Start-Up

LDO Switchover Function

The SiC403 includes a switch-over function for the LDO. The

switch-over function is designed to increase efficiency by

using the more efficient DC/DC converter to power the LDO

output, avoiding the less efficient LDO regulator when

possible. The switch-over function connects the V_LDOpin

directly to the V_OUTpin using an internal switch. When the

switch-over is complete the LDO is turned off, which results

Figure 10 shows the ENL voltage thresholds and their effect

on LDO and switcher operation.

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SiC403

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in a power savings and maximizes efficiency. If the LDO

output is used to bias the SiC403, then after switch-over the

device is self-powered from the switching regulator with the

LDO turned off.

It is not recommended to use the switch-over feature for an

output voltage less than 3 V since this does not provide

sufficient voltage for the gate-source drive to the internal

p-channel switch-over MOSFET.

The switch-over logic waits for 32 switching cycles before it

starts the switch-over. There are two methods that determine

Switch-Over MOSFET Parasitic Diodes

the switch-over of V_LDOto V_OUT

.

The switch-over MOSFET contains parasitic diodes that are

inherent to its construction, as shown in figure 12.

In the first method, the LDO is already in regulation and the

DC/DC converter is later enabled. As soon as the P_GOOD

output goes high, the 32 cycles are started. The voltages at

the V_LDOand V_OUTpins are then compared; if the two

voltages are within 300 mV of each other, the V_LDOpin

connects to the V_OUTpin using an internal switch, and the

LDO is turned off.

Switchover

control

Switchover

MOSFET

V

OUT

LDO

In the second method, the DC/DC converter is already

running and the LDO is enabled. In this case the 32 cycles

are started as soon as the LDO reaches 90 % of its final

value. At this time, the V_LDOand V_OUTpins are compared,

and if within 300 mV the switch-over occurs and the LDO

is turned off.

Parastic diode

V5V

Figure 12- Switch-over MOSFET Parasitic Diodes

Benefits of having a switchover circuit

There are some important design rules that must be followed

to prevent forward bias of these diodes. The following two

conditions need to be satisfied in order for the parasitic

diodes to stay off.

• V_DD V_LDO

• V_DD V_OUT

If either V_LDOor V_OUTis higher than V_DD, then the respective

diode will turn on and the SiC403 operating current will flow

through this diode. This has the potential of damaging the

device.

The switchover function is designed to get maximum

efficiency out of the DC/DC converter. The efficiency for an

LDO is very low especially for high input voltages. Using the

switchover function we tie any rails connected to V_LDO

through a switch directly to V_OUT. Once switchover is

complete LDO is turned off which saves power. This gives us

the maximum efficiency out of the SiC403.

If the LDO output is used to bias the SiC403, then after

switchover the V_OUTself biases the SiC403 and operates in

self-powered mode.

Steps to follow when using the on chip LDO to bias the

SiC403:

• Always tie the V_DDto V_LDObefore enabling the LDO

• Enable the LDO before enabling the switcher

• LDO has a current limit of 40 mA at start-up, so do not

connect any load between V_LDOand ground

ENL Pin and V_INUVLO

The ENL pin also acts as the switcher under-voltage lockout

for the V_INsupply. The V_INUVLO voltage is programmable

via a resistor divider at the V_IN, ENL and A_GNDpins.

ENL is the enable/disable signal for the LDO. In order to

implement the V_INUVLO there is also a timing requirement

that needs to be satisfied.

• The current limit for the LDO goes up to 200 mA once the

V

_LDOreaches 90 % of its final values and can easily supply

If the ENL pin transitions low within 2 switching cycles and is

< 0.4 V, then the LDO will turn off but the switcher remains

on. If ENL goes below the V_INUVLO threshold and stays

above 1 V, then the switcher will turn off but the LDO remains

on.

The V_INUVLO function has a typical threshold of 2.6 V on the

V_INrising edge. The falling edge threshold is 2.4 V.

Note that it is possible to operate the switcher with the LDO

disabled, but the ENL pin must be below the logic low

threshold (0.4 V maximum).

the required bias current to the IC.

Switch-over Limitations on V_OUTand V_LDO

Because the internal switch-over circuit always compares

the V_OUTand V_LDOpins at start-up, there are limitations on

permissible combinations of V_OUTand V_LDO. Consider the

case where V_OUTis programmed to 1.5 V and V_LDOis

programmed to 1.8 V. After start-up, the device would

connect V_OUTto V_LDOand disable the LDO, since the two

voltages are within the

300 mV switch-over window.

To avoid unwanted switch-over, the minimum difference

between the voltages for V_OUTand V_LDOshould be

500 mV.

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6 V, it is impossible to

determine if the LDO output is going to be used to power the

device or not. In self-powered operation where the LDO will

power the device, it is necessary during the LDO start-up to

hold the PWM switching off until the LDO has reached 90 %

of the final value. This is to prevent overloading the

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SiC403

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current-limited LDO output during the LDO start-up.

However, if the switcher was previously operating (with EN/

PSV high but ENL at ground, and V_DDsupplied externally),

then it is undesirable to shut down the switcher.

To prevent this, when the ENL input is taken above 2.6 V

(above the V_INUVLO threshold), the internal logic checks the

Frequency Selection

Selection of the switching frequency requires making a

trade-off between the size and cost of the external filter

components (inductor and output capacitor) and the power

conversion efficiency.

The desired switching frequency is 250 kHz which results

from using component selected for optimum size and cost.

A resistor (R_TON) is used to program the on-time (indirectly

setting the frequency) using the following equation.

P_GOODsignal. If P_GOODis high, then the switcher is already

running and the LDO will run through the start-up cycle

without affecting the switcher. If P_GOODis low, then the LDO

will not allow any PWM switching until the LDO output has

reached 90 % of it's final value.

(t - 10 ns) x V

ON

IN

R

=

ton

25 pF x V

OUT

On-Chip LDO Bias the SiC403

The following steps must be followed when using the onchip

LDO to bias the device.

To select R_TON, use the maximum value for V_IN, and for t_ON

use the value associated with maximum V_IN.

• Connect V_DDto V_LDObefore enabling the LDO.

• The LDO has an initial current limit of 40 mA at start-up,

therefore, do not connect any external load to V_LDOduring

start-up.

V

OUT

t

=

ON

V

x f

SW

INMAX.

t_ON= 318 ns at 13.2 V_IN, 1.05 V_OUT, 250 kHz

• When V_LDOreaches 90 % of its final value, the LDO

current limit increases to 200 mA. At this time the LDO may

be used to supply the required bias current to the device.

Attempting to operate in self-powered mode in any other

configuration can cause unpredictable results and may

damage the device.

Substituting for R_TONresults in the following solution

R_TON= 154.9 k, use R_TON= 154 k.

Inductor Selection

In order to determine the inductance, the ripple current must

first be defined. Low inductor values result in smaller size but

create higher ripple current which can reduce efficiency.

Higher inductor values will reduce the ripple current and

voltage and for a given DC resistance are more efficient.

However, larger inductance translates directly into larger

packages and higher cost. Cost, size, output ripple, and

efficiency are all used in the selection process.

The ripple current will also set the boundary for power-save

operation. The switching will typically enter power-save

mode when the load current decreases to 1/2 of the ripple

current. For example, if ripple current is 4 A then power-save

operation will typically start for loads less than 2 A. If ripple

current is set at 40 % of maximum load current, then

power-save will start for loads less than 20 % of maximum

current.

Design Procedure

When designing a switch mode power supply, the input

voltage range, load current, switching frequency, and

inductor ripple current must be specified.

The maximum input voltage (V_INMAX) is the highest specified

input voltage. The minimum input voltage (V_INMIN) is

determined by the lowest input voltage after evaluating the

voltage drops due to connectors, fuses, switches, and PCB

traces.

The following parameters define the design:

• Nominal output voltage (V_OUT

• Static or DC output tolerance

• Transient response

)

The inductor value is typically selected to provide a ripple

current that is between 25 % to 50 % of the maximum load

current. This provides an optimal trade-off between cost,

efficiency, and transient performance.

During the DH on-time, voltage across the inductor is

(V_IN- V_OUT). The equation for determining inductance is

shown next.

• Maximum load current (I_OUT

)

There are two values of load current to evaluate - continuous

load current and peak load current. Continuous load current

relates to thermal stresses which drive the selection of the

inductor and input capacitors. Peak load current determines

instantaneous

component

stresses

and

filtering

requirements such as inductor saturation, output capacitors,

and design of the current limit circuit.

The following values are used in this design:

• V_IN= 12 V 10 %

• V_OUT= 1.05 V 4 %

• f_SW= 250 kHz

(V - V

) x t

ON

IN

OUT

L =

I

RIPPLE

Example

In this example, the inductor ripple current is set equal to

50 % of the maximum load current. Thus ripple current will be

50 % x 6 A or 3 A. To find the minimum inductance needed,

use the V_INand T_ONvalues that correspond to V_INMAX.

• Load = 6 A maximum

(13.2 - 1.05) x 318 ns

L =

= 1.28 µH

3 A

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SiC403

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A slightly larger value of 1.3 µH is selected. This will

decrease the maximum I_RIPPLEto 2.9 A.

Note that the inductor must be rated for the maximum DC

load current plus 1/2 of the ripple current. The ripple current

under minimum V_INconditions is also checked using the

following equations.

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 750 mV reference, the DL

output is high and the low-side MOSFET is on. During this

time, the voltage across the inductor is approximately - V_OUT

.

This causes a down-slope or falling di/dt in the inductor. If the

load dI/dt is not much faster than the - dI/dt in the inductor,

then the inductor current will tend to track the falling load

current. This will reduce the excess inductive energy that

must be absorbed by the output capacitor, therefore a

smaller capacitance can be used.

25 pF x R

x V

OUT

TON

T

=

ON_VINMIN

V

INMIN

(V - V

IN

) x T

ON

OUT

I

=

RIPPLE

L

The following can be used to calculate the needed

capacitance for a given dI_LOAD/dt:

(10.8 - 1.05) x 384 ns

1.3 µH

I

=

= 2.88 A

RIPPLE_VIN

Peak inductor current is shown by the next equation.

I_LPK= I_MAX+ 1/2 x I_RIPPLEMAX

I_LPK= 6 + 1/2 x 2.9 = 7.45 A

Capacitor Selection

The output capacitors are chosen based on required ESR

and capacitance. The maximum ESR requirement is

controlled by the output ripple requirement and the DC

tolerance. The output voltage has a DC value that is equal to

the valley of the output ripple plus 1/2 of the peak-to-peak

ripple. Change in the output ripple voltage will lead to a

change in DC voltage at the output.

Rate of change of load current = dI_LOAD/dt

I_MAX= maximum load release = 6 A

I

V

I

MAX

LPK

L x

-

x dt

dl

LOAD

OUT

C

= I

x

LPK

OUT

2 (V - V

)

PK

OUT

The design goal is that the output voltage regulation be

4 % under static conditions. The internal 500 mV reference

tolerance is 1 %. Allowing 1 % tolerance from the FB resistor

divider, this allows 2 % tolerance due to V_OUTripple.

Since this 2 % error comes from 1/2 of the ripple voltage, the

allowable ripple is 4 %, or 42 mV for a 1.05 V output.

The maximum ripple current of 4.4 A creates a ripple voltage

across the ESR. The maximum ESR value allowed is shown

by the following equations.

Example

dl

2.5 A

LOAD

Load

=

dt

µs

This would cause the output current to move from 10 A to

zero in 4 µs as shown by the following equation.

7.45

1.05

6

2.5

1.3 µH x

-

x 1 µs

C

= 7.45 x

OUT

2 (1.15 - 1.05)

V

42 mV

RIPPLE

ESR

=

MAX

I

2.9 A

RIPPLEMAX

= 254 µF

OUT

ESR

= 9.5 mΩ

Note that C_OUTis much smaller in this example, 254 µF

compared to 328 µF based on a worst-case load release. To

meet the two design criteria of minimum 254 µF and

maximum 9 m ESR, select two capacitors rated at 150 µF

and 18 m ESR.

It is recommended that an additional small capacitor be

placed in parallel with C_OUTin order to filter high frequency

switching noise.

The output capacitance is usually chosen to meet transient

requirements. A worst-case load release, from maximum

load to no load at the exact moment when inductor current is

at the peak, determines the required capacitance. If the load

release is instantaneous (load changes from maximum to

zero in < 1 µs), the output capacitor must absorb all the

inductor's stored energy. This will cause a peak voltage on

the capacitor according to the following equation.

Stability Considerations

1

2

)

Unstable operation is possible with adaptive on-time

controllers, and usually takes the form of double-pulsing or

ESR loop instability.

L (I

+

x I

2

OUT

RIPPLEMAX

C

=

OUT_MIN

2

(V

) - (V

)

OUT

PEAK

Double-pulsing occurs due to switching noise seen at the FB

input or because the FB ripple voltage is too low. This causes

the FB comparator to trigger prematurely after the 250 ns

minimum off-time has expired. In extreme cases the noise

can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect operation.

Assuming a peak voltage V_PEAKof 1.150 (100 mV rise upon

load release), and a 10 A load release, the required

capacitance is shown by the next equation.

1

2

1.3 µH (6 + x 2.9)

C

=

OUT_MIN

2

(1.15) - (1.05)

= 328 µF

OUT_MIN

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

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This form of instability can usually be avoided by providing

the FB pin with a smooth, clean ripple signal that is at least

10 mV_p-p, which may dictate the need to increase the ESR of

the output capacitors. It is also imperative to provide a proper

PCB layout as discussed in the Layout Guidelines section.

For applications using ceramic output capacitors, the ESR is

normally too small to meet the above ESR criteria. In these

applications it is necessary to add a small virtual ESR

network composed of two capacitors and one resistor, as

shown in figure 14. This network creates a ramp voltage

across C_L, analogous to the ramp voltage generated across

the ESR of a standard capacitor. This ramp is then

capacitive-coupled into the FB pin via capacitor C_C.

C

TOP

L

To FB pin

V

OUT

R

1

High-

side

C

R

2

L

R

L

R1

R2

C

OUT

Low-

side

Figure 13 - Capacitor Coupling to FB Pin

Another way to eliminate doubling-pulsing is to add a small

(~ 10 pF) capacitor across the upper feedback resistor, as

shown in figure 13. This capacitor should be left unpopulated

until it can be confirmed that double-pulsing exists. Adding

the C_TOPcapacitor will couple more ripple into FB to help

eliminate the problem. An optional connection on the PCB

should be available for this capacitor.

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking

stability is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and ringing.

Ringing for more than one cycle after the initial step is an

indication that the ESR should be increased.

FB

Figure 14 - Virtual ESR Ramp Current

Dropout Performance

The output voltage adjusts range for continuous-conduction

operation is limited by the fixed 250 ns (typical) minimum

off-time of the one-shot. When working with low input

voltages, the duty-factor limit must be calculated using

worst-case values for on and off times. The duty-factor

limitation is shown by the next equation.

One simple way to solve this problem is to add trace

resistance in the high current output path. A side effect of

adding trace resistance is output decreased load regulation.

T

ON(MIN)

DUTY =

T

x T

OFF(MAX)

ON(MIN)

The inductor resistance and MOSFET on-state voltage drops

must be included when performing worst-case dropout

duty-factor calculations.

ESR Requirements

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide10 mV_p-p

at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insufficient

ESR. The on-time control regulates the valley of the output

ripple voltage. This ripple voltage is the sum of the two

voltages. One is the ripple generated by the ESR, the other

is the ripple due to capacitive charging and discharging

during the switching cycle. For most applications the

minimum ESR ripple voltage is dominated by the output

capacitors, typically SP or POSCAP devices. For stability the

ESR zero of the output capacitor should be lower than

approximately one-third the switching frequency. The

formula for minimum ESR is shown by the following

equation.

3

ESR

=

MIN

2 x π x C

x f

SW

OUT

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Document Number: 66550

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SiC403

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System DC Accuracy (V_OUTController)

Switching Frequency Variations

Three factors affect V_OUTaccuracy: the trip point of the FB

error comparator, the ripple voltage variation with line and

load, and the external resistor tolerance. The error

comparator off set is trimmed so that under static conditions

it trips when the feedback pin is 750 mV, 1 %.

The on-time pulse from the SiC403 in the design example is

calculated to give a pseudo-fixed frequency of 250 kHz.

Some frequency variation with line and load is expected.

This variation changes the output ripple voltage. Because

constant on-time converters regulate to the valley of the

output ripple, ½ of the output ripple appears as a DC

regulation error. For example, if the output ripple is 50 mV

with V_IN= 6 V, then the measured DC output will be 25 mV

above the comparator trip point. If the ripple increases to

80 mV with V_IN= 25 V, then the measured DC output will be

40 mV above the comparator trip. The best way to minimize

this effect is to minimize the output ripple.

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of trace

resistance between the inductor and output capacitor.

This trace resistance should be optimized so that at full load

the output droops to near the lower regulation limit. Passive

droop minimizes the required output capacitance because

the voltage excursions due to load steps are reduced as

seen at the load.

The switching frequency will vary depending on line and load

conditions. The line variations are a result of fixed

propagation delays in the on-time one-shot, as well as

unavoidable delays in the external MOSFET switching. As

V_INincreases, these factors make the actual DH on-time

slightly longer than the ideal on-time. The net effect is that

frequency tends to falls slightly with increasing input voltage.

The switching frequency also varies with load current as a

result of the power losses in the MOSFETs and the inductor.

For a conventional PWM constant-frequency converter, as

load increases the duty cycle also increases slightly to

compensate for IR and switching losses in the MOSFETs

and inductor.

A constant on-time converter must also compensate for the

same losses by increasing the effective duty cycle (more

time is spent drawing energy from V_INas losses increase).

The on-time is essentially constant for a given V_OUT/V_IN

combination, to off set the losses the off-time will tend to

reduce slightly as load increases. The net effect is that

switching frequency increases slightly with increasing load.

The use of 1 % feedback resistors contributes up to 1 %

error. If tighter DC accuracy is required, 0.1 % resistors

should be used.

The output inductor value may change with current. This will

change the output ripple and therefore will have a minor

effect on the DC output voltage. The output ESR also affects

the output ripple and thus has a minor effect on the DC

output voltage.

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

For technical support, please contact: analogswitchtechsupport@vi-

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SiC403

Vishay Siliconix

SIC403 EVALUATION BOARD SCHEMATIC

1

2

4

3

1

t

b s l x

T O N

B S T

V O U T

N C

A G N D

3 5

B S T 8

A G N D

3 0

A G N D

V o

2

4

P G N D

2 2

P G N D

1 2

1 4

2 1

P G N D

2 0

P G N D

1 9

P G N D

1 8

P G N D

E N / P S V

E N L

_ P S E V N 2 9

3 2

1 7

P G N D

1 6

P G N D

1

1 5

1

Figure 15. Evaluation Board Schematic

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Document Number: 66550

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SiC403

Vishay Siliconix

BILL OF MATERIALS

Item

Qty.

Reference

Value

Voltage

PCB Footprint

Part Number

Manufacturer

V_IN

1

B1

SOLDER-BANANA

575-4

Keystone

V_IN_GND

2

3

1

4

1

3

1

2

3

1

B2

SOLDER-BANANA

SM/C_1210

575-4

Keystone

Murata

B3

B4

Vo

575-4

V_O_GND

4

575-4

5

C1, C2, C3, C4

C5

22 µF

0.1 µF

220 µF

150 µF

0.01 µF

10 µF

16 V

50 V

25 V

35 V

50 V

16 V

10 V

GRM32ER71C226ME18L

EMK105BJ104KV-F

VJ0603Y104KXACW1BC

593D227X0010E2TE3

EEU-FM1V151

6

SM/C_0402

Taiyo Yuden

Murata

7

C6

SM/C_0603

8

C7, C11, C14

C10, C20, C22

C12

SM/C_0603

Vishay

9

595D-D

Vishay

10

11

12

13

14

15

16

D8X11.5-D0.6X3.5

SM/C_0402

Panasonic

Vishay

C13

VJ0402Y103KXACW1BC

C3216X7R1C106M

593D227X0010E2TE3

C15, C21

C16, C17, C18

C19

SM/C_1206

TDK

220 µF

1 µ

595D-D

Vishay

SM/C_0603

C24

10 n

68 pF

SM/C_0603

C25

50 V

10 V

SM/C_0402

0402YA680JAT2A

LMK212B7475KG-T

AVX

TAIYO

YUDEN

17

2

C26, C27

4.7 µF

SM/C_0805

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

1

4

1

2

1

C28

0.1 µF

22 nF

10 V

16 V

50 V

SM/C_0603

GRM155R61A105KE19D

Murata

Vishay

C29

C30

100 pF

SM/C_0402

VJ0402Y101KXACW1BC

C0402C102K3RA

VJ0402A103KXACW1BC

PK007-015

C36

1 nF

SM/C_0402

C37

10 nF

SM/C_0402

J5

Probe Test Pin

0.78 µH

M HOLE2

V_DD

LECROY PROBE PIN

IHLP4040

L1

IHLP4040DZERR78M11

8834

Vishay

Keystone

Vishay

M1, M2, M3, M4

STACKING SPACER

Probe Hook - d76

SO-8

P1

P2

1573-3

EN_PSV

Step_I_Sense

LDTRG

1573-3

P3

1573-3

P4

1573-3

V_CTL

P5

1573-3

P6

ENL

PGOOD

V_IN

1573-3

P7

1573-3

P8

1573-3

V_IN_GND

V_OUT

P9

1573-3

P10

P11

Q1

1573-3

V_O_GND

1573-3

Si4812BDY

300K

30 V

50 V

200 V

50 V

Si4812BDY

R1

SM/C_0603

CRCW060310K0FKEA

CRCW06030000FKEA

CRCW25121R00FKTA

CRCW0603100KFKEA

CRCW06030000Z0EA

Vishay

R2

300K

SM/C_0603

Vishay

R4

1R01

100K

C_2512

Vishay

R5, R6

R7

SM/C_0603

Vishay

0R

SM/C_0603

Vishay

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

For technical support, please contact: analogswitchtechsupport@vi-

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SiC403

Vishay Semiconductors

New Product

BILL OF MATERIALS

43

44

45

46

47

48

49

50

51

52

53

54

3

1

R8, R10, R29

10K



50 V

SM/C_0603

CRCW060310K0FKEA

Vishay

R9

SM/C_0603

SM/C_0402

SM/C_0603

SM/C_0402

SM/C_0805

SM/C_0603

MLPQ5x5-32L

R12

57.6K

10K

50 V

CRCW060357K6FKEA

CRCW040210K0FKED

CRCW06031K50FKEA

CRCW06037K15FKEA

CRCW0603154KFKEA

CRCW04020000Z0ED

CRCW08051R00FNEA

CRCW060331K6FKEA

Vishay

R13

R14

100

R15

1.5K

7k15

154K

0R

R23

R30

R39

R51

1R

R52

31K6

SiC401/2/3

50 V

U1

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Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

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PCB LAYOUT OF THE EVALUATION BOARD

Figure 14. Top Layer

Figure 15. Middle Layer 1

Figure 16. Middle Layer 2

Figure 17. Bottom Layer

Figure 15. Top Component

Figure 17. Bottom Component

Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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SiC403

Vishay Semiconductors

New Product

PACKAGE DIMENSIONS AND MARKING INFO

C

0.900 0.100

0.050

0.000

3.480 0.100

R Full

B

5.000 0.075

17

24

25

16

C

L

0.460

32

9

R0.200

Pin 1 I.D.

Bare

Copper

8

C

L

Pin # 1 (Laser Marked)

1.660 0.100

0.500

1.485 0.100

Top View

0.250 0.050

0.10

C A

0.460

Bottom View

B

0.200 ref.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?66550.

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Document Number: 66550

S12-0628-Rev. C, 19-Mar-12

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Package Information

Vishay Siliconix

PowerPAK^®MLP55-32L CASE OUTLINE

0.08 C

6

5

2x

A

Pin 1 dot

by marking

2x

A1

A2

D2 - 1

0.10 CA

A

D

D2 - 2

32

Pin #1 identification

R0.200

0.360

0.10 CB

25

1

24

32L T/SLP

(5 mm x 5 mm)

17

8

B

16

9

D2 - 3

D2 - 4

C

(Nd-1) Xe

Ref.

D4

0.36

Top View

Side View

Bottom View

MILLIMETERS

INCHES

DIM

MIN.

0.80

0.00

NOM.

0.85

MAX.

0.90

0.05

MIN.

0.031

0.000

NOM.

0.033

-

MAX.

0.035

0.002

A

A1⁽⁸⁾

-

A2

b⁽⁴⁾

0.20 REF.

0.25

0.008 REF.

0.098

0.20

0.30

0.078

0.011

D

5.00 BSC

0.50 BSC

5.00 BSC

0.40

0.196 BSC

0.019 BSC

0.196 BSC

0.015

e

E

L

0.35

0.45

0.013

0.017

N⁽³⁾

32

Nd⁽³⁾

Ne⁽³⁾

D2 - 1

D2 - 2

D2 - 3

D2 - 4

E2 - 1

E2 - 2

E2 - 3

8

3.43

1.00

1.92

3.43

1.61

1.43

3.48

3.53

1.10

2.02

3.53

1.71

1.53

0.135

0.039

0.075

0.135

0.063

0.056

0.137

0.139

0.043

0.079

0.139

0.067

0.060

1.05

0.041

1.05

0.041

1.97

0.077

3.48

0.137

1.66

0.065

1.48

0.058

ECN: T-08957-Rev. A, 29-Dec-08

DWG: 5983

Notes

1. Use millimeters as the primary measurement.

2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.

3. N is the number of terminals.

Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.

4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.

5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.

6. Exact shape and size of this feature is optional.

7. Package warpage max. 0.08 mm.

8. Applied only for terminals.

Document Number: 64714

Revision: 29-Dec-08

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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,

“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other

disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or

the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all

liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,

consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular

purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical

requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements

about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular

product with the properties described in the product specification is suitable for use in a particular application. Parameters

provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All

operating parameters, including typical parameters, must be validated for each customer application by the customer’s

technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,

including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining

applications or for any other application in which the failure of the Vishay product could result in personal injury or death.

Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please

contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by

any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the

definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council

of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment

(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that

all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free

requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference

to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21

conform to JEDEC JS709A standards.

Revision: 02-Oct-12

Document Number: 91000

1


型号：	CRCW060310K0JNEA
厂家：	VISHAY
描述：	Fixed Resistor, Metal Glaze/thick Film, 0.1W, 10000ohm, 75V, 5% +/-Tol, 200ppm/Cel, Surface Mount, 0603, CHIP, HALOGEN FREE AND ROHS COMPLIANT 稳压器
文件：	总26页 (文件大小：648K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CRCW060310K0JNEA [VISHAY]

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