DG408L
更新时间：2024-09-18 08:24:47
品牌：VISHAY
描述：Precision 8-Ch/Dual 4-Ch Low Voltage Analog Multiplexers
概述
数据手册DG408L 概述
Precision 8-Ch/Dual 4-Ch Low Voltage Analog Multiplexers 高精度8通道/双4通道低电压模拟多路复用器
DG408L 数据手册
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PDF下载DG408L/409L
Vishay Siliconix
Precision 8-Ch/Dual 4-Ch Low Voltage Analog Multiplexers
DESCRIPTION
FEATURES
The DG408L/409L are low voltage pin-for-pin compatible
companion devices to the industry standard DG408/409 with
improved performance.
•
Pin-For-Pin compatibility with DG408/409
Pb-free
•
2.7- to 12 V Single Supply or 3 to ꢀ V
Dual Supply Operation
Available
RoHS*
Using BiCMOS wafer fabrication technology allows the
DG408L/409L to operate on single and dual supplies. Single
supply voltage ranges from 3 to 12 V while dual supply
operation is recommended with 3 to ꢀ V.
•
•
•
•
•
•
•
•
Lower On-Resistance: rDS(on) - 17 Ω Typ.
Fast Switching: tON - 38 ns, tOFF - 18 ns
Break-Before-Make Guaranteed
Low Leakage: IS(off) - 0.2 nA Max.
Low Charge Injection: 1 pC
COMPLIANT
The DG408L is an 8 Channel single-ended analog
multiplexer designed to connect one of eight inputs to a
common output as determined by a 3 bit binary address (A0,
A1, A2). The DG409L is a dual 4 Channel differential analog
multiplexer designed to connect one of four differential
inputs to a common dual output as determined by its 2 bit
binary address (A0, A1). Break-before-make switching action
to protect against momentary crosstalk between adjacent
channels.
TTL, CMOS, LV Logic (3 V) Compatible
- 82 dB Off-Isolation at 1 MHz
2000 V ESD Protection (HBM)
BENEFITS
•
•
•
•
High Accuracy
Single and Dual Power Rail Capacity
Wide Operating Voltage Range
Simple Logic Interface
The DG408L/409L provides lower on-resistance, faster
switching time, lower leakage, less power consumption and
higher off-Isolation than the DG408/409.
APPLICATIONS
•
•
•
•
•
•
•
Data Acquisition Systems
Battery Operated Equipment
Portable Test Equipment
Sample and Hold Circuits
Communication Systems
SDSL, DSLAM
Audio and Video Signal Routing
FUNCTIONAL BLOCK DIAGRAMS AND PIN CONFIGURATIONS
DG408L
DG409L
Dual-In- Line, SOIC and TSSOP
Dual-In- Line, SOIC and TSSOP
A
A
A
A
1
0
1
0
1
2
3
4
5
ꢀ
7
8
1ꢀ
15
14
13
12
11
10
9
1
2
3
4
5
ꢀ
7
8
1ꢀ
15
14
13
12
11
10
9
EN
V-
A
2
EN
V-
GND
V+
Decoders/Drivers
Decoders/Drivers
GND
V+
S
1
S
S
1b
1a
2a
3a
S
2
S
5
S
S
S
S
2b
S
3
S
ꢀ
S
3b
S
4
S
7
S
4b
4a
D
S
8
D
D
b
a
Top View
Top View
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
www.vishay.com
1
DG408L/409L
Vishay Siliconix
TRUTH TABLE - DG408L
TRUTH TABLE - DG409L
A2
A1
A0
A1
A0
EN
1
On Switch
EN
On Switch
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
None
X
0
0
1
1
X
0
1
0
1
0
None
0
1
2
3
4
5
ꢀ
7
8
1
1
2
3
4
1
1
1
1
1
1
1
Logic "0" = VAL ≤ 0.8 V
Logic "1" = VAH ≥ 2.4 V
X = Do not Care
1
1
1
For low and high voltage levels for VAX and VEN consult “Digital Control” parameters for specific V+ operation.
ORDERING INFORMATION - DG408L ORDERING INFORMATION - DG409L
Temp Range
Package
Part Number
Temp Range
Package
Part Number
DG408LDY
DG408LDY-E3
DG408LDY-T1
DG408LDY-T1-E3
DG409LDY
DG409LDY-E3
DG409LDY-T1
DG409LDY-T1-E3
1ꢀ-Pin SOIC
1ꢀ-Pin SOIC
- 40 to 85 °C
- 40 to 85 °C
DG408LDQ
DG408LDQ-E3
DG408LDQ-T1
DG408LDQ-T1-E3
DG409LDQ
DG409LDQ-E3
DG409LDQ-T1
DG409LDQ-T1-E3
1ꢀ-Pin TSSOP
1ꢀ-Pin TSSOP
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
14
Unit
Voltage Referenced V+ to V-
GND
7
V
Digital Inputsa, VS, VD
(V-) - 0.3 to (V) + 0.3
Current (Any Terminal)
30
100
mA
°C
Peak Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle Max)
(A Suffix)
- ꢀ5 to 150
- ꢀ5 to 125
ꢀ50
Storage Temperature
(D Suffix)
1ꢀ-Pin Plastic TSSOPc
1ꢀ-Pin Narrow SOICc
1ꢀ-Pin CerDIPd
LCC-20e
ꢀ00
Power Dissipation (Package)b
mW
900
750
Notes:
a. Signals on SX, DX, AX, or EN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 7.ꢀ mW/°C above 75 °C.
d. Derate 12 mW/°C above 75 °C.
e. Derate 10 mW/°C above 75 °C.
www.vishay.com
2
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
DG408L/409L
Vishay Siliconix
SPECIFICATIONS (SINGLE SUPPLY 12 V)
Test Conditions
A Suffix
D Suffix
Unless Otherwise Specified
- 55 to 125 °C - 40 to 85 °C
V+ = 12 V, 10 %, V- = 0 V
Tempb Typd Minc Maxc Minc Maxc Unit
V
EN = 0.8 V or 2.4 Vf
Parameter
Symbol
Analog Switch
Analog Signal Rangee
VANALOG
rDS(on)
Full
0
12
0
12
V
VD = 10.8 V, VD = 2 V or 9 V, IS = 10 mA
Sequence Each Switch On
Room
Full
17
29
38
29
35
Drain-Source On-Resistance
r
DS(on) Matching
Ω
ΔrDS
Room
1
3
3
3
VD = 10.8 V, VD = 2 V or 9 V
IS = 10 mA
Between Channelsg
On-Resistance Flatnessi
rFLAT(on)
IS(off)
ID(off)
ID(on)
Room
7
7
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
VEN = 0 V, VD = 11 V or 1 V
Switch Off Leakage Current
Channel On Leakage Current
V
S = 1 V or 11 V
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
nA
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
VS = VD = 1 V or 11 V
Digital Control
VINH
VINL
IIN
Logic High Input Voltage
Logic Low Input Voltage
Input Current
Full
Full
Full
2.4
2.4
- 1
V
0.8
1.5
0.8
1
VAX = VEN = 2.4 V or 0.8 V
- 1.5
µA
Dynamic Characteristics
VS1 = 8 V, VS8 = 0 V, (DG408L)
VS1b = 8 V, VS4b = 0 V, (DG409L)
See Figure 2
Room
Full
30
ꢀ0
ꢀ8
ꢀ0
ꢀ5
tTRANS
Transition Time
VS(all) = VDA = 5 V
Room
Full
11
38
18
1
1
tOPEN
tON(EN)
tOFF(EN)
Break-Before-Make Time
Enable Turn-On Time
Enable Turn-Off Time
ns
See Figure 4
Room
Full
55
ꢀ0
55
ꢀ0
VAX = 0 V, VS1 = 5 V (DG408L)
VAX = 0 V, VS1b = 5 V (DG409L)
See Figure 3
Room
Full
25
35
25
30
Charge Injectione
Off Isolatione, h
Crosstalke
Source Off Capacitancee
Drain Off Capacitancee
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω
f = 100 kHz, RL = 1 kΩ
Q
Room
Room
Room
Room
Room
1
- 70
- 82
7
5
5
pC
dB
OIRR
XTALK
CS(off)
CD(off)
f = 1 MHz, VS = 0 V, VEN = 0 V
f = 1 MHz, VD = 2.4 V, VEN = 0 V
20
pF
f = 1 MHz, VD = 0 V, VEN = 2.4 V
(DG409L only)
Drain On Capacitancee
CD(on)
Room
31
Power Supplies
Power Supply Range
Power Supply Current
V+
I+
3
12
3
12
V
VEN = VA = 0 V or 5 V
Room
0.2
0.7
0.7
mA
Notes:
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. ΔrDS(on) = rDS(on) Max - rDS(on) Min.
h. Worst case isolation occurs on Channel 4 do to proximity to the drain pin.
i. rDS(on) flatness is measured as the difference between the minimum and maximum measured values across a defined Analog signal.
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
www.vishay.com
3
DG408L/409L
Vishay Siliconix
SPECIFICATIONS (DUAL SUPPLY V+ = 5 V, V = 5 V)
Test Conditions
A Suffix
D Suffix
Unless Otherwise Specified
- 55 to 125 °C - 40 to 85 °C
V+ = 5 V, 10 %, V- = - 5 V, V- = 0 V
Tempb Typd Minc Maxc Minc Maxc Unit
V
EN = 0.ꢀ V or 2.4 Vf
Parameter
Symbol
Analog Switch
Analog Signal Rangee
VANALOG
rDS(on)
Full
- 5
5
- 5
5
V
VD
=
3.5 V, IS = 10 mA
Room
Full
20
40
50
40
50
Drain-Source On-Resistance
Ω
Sequence Each Switch On
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
IS(off)
ID(off)
ID(on)
V+ = 5.5 , V- = 5.5 V
Switch Off Leakage Currenta
V
EN = 0 V, VD
=
4.5 V, VS
=
4.5 V
4.5 V
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
nA
Channel On Leakage
Currenta
V+ = 5.5 V, V- = - 5.5 V
EN = 2.4 V, VD 4.5 V, VS =
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
V
=
Digital Control
VINH
VINL
IIN
Logic High Input Voltage
Full
Full
Full
2.4
2.4
- 1
V
Logic Low Input Voltage
0.ꢀ
1.5
0.ꢀ
1
Input Currenta
VAX = VEN = 2.4 V or 0.ꢀ V
- 1.5
µA
Dynamic Characteristics
VS1 = 3.5 V, VS8 = - 3.5 V, (DG408L)
Room
Full
30
ꢀ0
78
ꢀ0
ꢀ5
Transition Timee
tTRANS
VS1b = 3.5 V, VS4b = - 3.5 V, (DG409L)
See Figure 2
VS(all) = VDA = 3.5 V
See Figure 4
Room
Full
8
1
1
Break-Before-Make Timee
Enable Turn-On Timee
Enable Turn-Off Timee
tOPEN
tON(EN)
tOFF(EN)
ns
Room
Full
25
20
55
ꢀ8
55
ꢀ0
VAX = 0 V, VS1 = 3.5 V (DG408L)
V
AX = 0 V, VS1b = 3.5 V (DG409L)
Room
Full
40
50
40
45
See Figure 3
Source Off Capacitancee
Drain Off Capacitancee
Drain On Capacitancee
CS(off)
CD(off)
CD(on)
f = 1 MHz, VS = 0 V, VEN = 0 V
f = 1 MHz, VD = 0 V, VEN = 0 V
f = 1 MHz, VD = 0 V, VEN = 2.4 V
Room
Room
Room
ꢀ
15
29
pF
Notes:
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. ΔrDS(on) = rDS(on) Max - rDS(on) Min.
h. Worst case isolation occurs on Channel 4 do to proximity to the drain pin.
i. rDS(on) flatness is measured as the difference between the minimum and maximum measured values across a defined Analog signal.
www.vishay.com
4
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
DG408L/409L
Vishay Siliconix
SPECIFICATIONS (SINGLE SUPPLY 5 V)
Test Conditions
A Suffix
D Suffix
Unless Otherwise Specified
- 55 to 125 °C - 40 to 85 °C
V+ = 5 V, 10 %, V- = 0 V
Tempb Typd Minc Maxc Minc Maxc Unit
V
EN = 0.ꢀ V or 2.4 Vf
Parameter
Symbol
Analog Switch
Analog Signal Rangee
VANALOG
rDS(on)
Full
0
5
0
5
V
V+ = 4.5 V, VD or VS = 1 V or 3.5 V,
ID = 5 mA
Room
Full
35
49
ꢀ2
40
ꢀ2
Drain-Source On-Resistance
rDS(on) Matching Between
Channelsg
On-Resistance Flatnessi
Ω
ΔrDS
Room
Room
1.5
3
4
3
4
V+ = 4.5 V, VD = 1 V or 3.5 V,
IS = 5 mA
rFLAT(on)
IS(off)
ID(off)
ID(on)
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
V+ = 5.5 V, VS = 1 V or 4 V
Switch Off Leakage Currenta
V
D = 4 V or 1 V
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
nA
Channel On Leakage
Currenta
V+ = 5.5 V, VD = VS = 1 V or 4 V
Sequence Each Switch On
Room
Full
- 1
- 15
1
15
- 1
- 10
1
10
Digital Control
VINH
VINL
IIN
Logic High Input Voltage
Full
Full
Full
2.4
2.4
- 1
V+ = 5 V
V
Logic Low Input Voltage
0.ꢀ
1.5
0.ꢀ
1
Input Currenta
VAX = VEN = 2.4 V or 0.ꢀ V
- 1.5
µA
Dynamic Characteristics
VS1 = 3.5 V, VS8 = 0 V, (DG408L)
VS1b = 3.5 V, VS4b = 0 V, (DG409L)
See Figure 2
Room
Full
44
125
138
125
135
Transition Timee
tTRANS
VS(all) = VDA = 3.5 V,
Room
Full
17
43
2ꢀ
1
1
Break-Before-Make Timee
Enable Turn-On Timee
Enable Turn-Off Timee
tOPEN
tON(EN)
tOFF(EN)
ns
See Figure 4
Room
Full
ꢀ0
70
ꢀ0
ꢀ5
VAX = 0 V, VS1 = 3.5 V (DG408L)
VAX = 0 V, VS1b = 3.5 V (DG409L)
See Figure 3
Room
Full
45
ꢀ0
45
50
Charge Injectione
Off Isolatione, h
Crosstalke
Source Off Capacitancee
Drain Off Capacitancee
CL = 1 nF, RGEN = 0 Ω, VGEN = 0 Ω
f = 100 kHz, RL = 1 kΩ
Q
Room
Room
Room
Room
Room
1
- 70
- 80
8
5
5
pC
dB
OIRR
XTALK
CS(off)
CD(off)
f = 1 MHz, VS = 0 V, VEN = 0 V
f = 1 MHz, VD = 0 V, VEN = 0 V
21
pF
f = 1 MHz, VD = 0 V, VEN = 2.4 V
(DG409L only)
Drain On Capacitancee
CD(on)
Room
32
Notes:
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. ΔrDS(on) = rDS(on) Max - rDS(on) Min.
h. Worst case isolation occurs on Channel 4 do to proximity to the drain pin.
i. rDS(on) flatness is measured as the difference between the minimum and maximum measured values across a defined Analog signal.
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
www.vishay.com
5
DG408L/409L
Vishay Siliconix
SPECIFICATIONS (SINGLE SUPPLY 3 V)
Test Conditions
A Suffix
- 55 to 125 °C - 40 to 85 °C
D Suffix
Unless Otherwise Specified
V+ = 3 V, 10 %, V- = 0 V
Tempb Typd Minc Maxc Minc Maxc Unit
V
EN = 0.4 V or 2.0 Vf
Parameter
Symbol
Analog Switch
Analog Signal Rangee
VANALOG
rDS(on)
Full
0
3
0
3
V
V+ = 2.7 V, VD = 0.5 or 2.2 V,
S = 5 mA
ꢀ0
80
105
80
100
Room
Full
Drain-Source On-Resistance
Ω
I
- 1
- 15
1
15
- 1
- 10
1
10
Room
Full
IS(off)
ID(off)
ID(on)
Switch Off Leakage Currenta
V+ = 3.3 V, VS = 2 or 1 V, VD = 1 or 2 V
- 1
- 15
1
15
- 1
- 10
1
10
Room
Full
nA
Channel On Leakage
Currenta
V+ = 3.3 V, VD = VS = 1 or 2 V
Sequence Each Switch On
- 1
- 15
1
15
- 1
- 10
1
10
Room
Full
Digital Control
VINH
VINL
IIN
Logic High Input Voltage
Logic Low Input Voltage
Full
Full
Full
2
2
V
0.4
1.5
0.4
1
Input Currenta
VAX = VEN = 2.4 V or 0.4 V
- 1.5
- 1
µA
Dynamic Characteristics
VS1 = 1.5 V, VS8 = 0 V, (DG408L)
75
150
175
150
175
Room
Full
tTRANS
Transition Time
VS1b = 1.5 V, VS4b = 0 V, (DG409L)
See Figure 2
VS(all) = VDA = 1.5 V,
See Figure 4
32
70
55
1
1
Room
Full
tOPEN
tON(EN)
tOFF(EN)
Break-Before-Make Time
Enable Turn-On Time
Enable Turn-Off Time
ns
95
115
95
105
Room
Full
VAX = 0 V, VS1 = 1.5 V (DG408L)
AX = 0 V, VS1b = 1.5 V (DG409L)
V
100
115
100
105
Room
Full
See Figure 3
Charge Injectione
Off Isolatione, h
Crosstalke
Source Off Capacitancee
Drain Off Capacitancee
CL = 1 nF, RGEN = 0 Ω, VGEN = 0 V
RL = 1 kΩ, f = 100 kHz
Q
Room
Room
Room
Room
Room
0.4
- 70
- 79
8
5
5
pC
dB
OIRR
XTALK
CS(off)
CD(off)
f = 1 MHz, VS = 0 V, VEN = 0 V
f = 1 MHz, VD = 0 V, VEN = 0 V
19
pF
f = 1 MHz, VD = 0 V, VEN = 2 V
(DG409L only)
Drain On Capacitancee
CD(on)
Room
33
Notes:
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. ΔrDS(on) = rDS(on) Max - rDS(on) Min.
h. Worst case isolation occurs on Channel 4 do to proximity to the drain pin.
i. rDS(on) flatness is measured as the difference between the minimum and maximum measured values across a defined Analog signal.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
ꢀ
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
DG408L/409L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
80
25
20
15
10
5
70
ꢀ0
V+ = 5 V
V- = - 5 V
V+ = 2.7 V
50
40
30
20
10
0
V+ = 4.5 V
V+ = 12 V
0
0
2
4
ꢀ
8
10
12
- 5
- 3
- 1
1
3
5
V
D
– Drain Voltage (V)
V
D
– Drain Voltage (V)
rDS(on) vs. VD and Power Supply
rDS(on) vs. VD and Power Supply
1.8
1.ꢀ
1.4
1.2
1.0
0.8
0.ꢀ
0.4
0.2
0.0
50
40
30
20
10
0
85 °C
Upper Threshold Limit
125 °C
Low Threshold Limit
25 °C
- 55 °C
0
2
4
ꢀ
8
10
12
14
0
1
2
3
4
5
ꢀ
V+ – Positive Supply Voltage (V)
V
D
– Drain Voltage (V)
rDS(on) vs. VD and Temperature
Input Threshold vs. V+ Supply Voltage
35
30
25
20
15
10
5
70
ꢀ0
50
40
30
20
10
0
85 °C
125 °C
25 °C
t
TRANS
t
ON
- 55 °C
t
OFF
0
- ꢀ
- 4
- 2
0
2
4
ꢀ
0
2
4
ꢀ
8
10
V+ – Positive Supply Voltage (V)
Switching Time vs. Positive Supply Voltage
12
14
Drain V
V
D
–
oltage (V)
rDS(on) vs. VD and Temperature
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
www.vishay.com
7
DG408L/409L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
35
30
25
20
15
10
5
10
0
- 10
- 20
- 30
- 40
I
S(off)
t
ON
I
t
D(off)
TRANS
I
D(on)
t
OFF
0
3
4
5
ꢀ
- 5
- 3
- 1
1
3
5
V , V – Analog Voltage (V)
– Dual Power Supply Voltage (V)
D
S
Leakage Current vs. Analog Voltage
Switching Time vs. Dual Power Supply Voltage
1.0
0.8
0.ꢀ
0.4
0.2
0.0
10
C
= 1000 pF
L
- 10
V+ = 3 V
V- = 0 V
V+ = 12 V
V- = 0 V
Insertion Loss
- 3 dB = 280 MHz
R
L
= 50 Ω
- 30
- 50
- 70
Off Isolation
V+ = 5 V
V- = - 5 V
Crosstalk
V+ = 5 V
V- = 0 V
- 90
- 110
- 5
0
5
10
0.1
1
10
Frequency (MHz)
100
1000
V
– Source Voltage (V)
S
Charge Injection vs. Analog Voltage
Insertion Loss, Off Isolation and Crosstalk
vs. Frequency (Single Supply)
35
30
25
20
15
10
5
35
30
25
20
15
10
5
C
C
D(on)
D(on)
V+ = 5 V
V- = - 5 V
V+ = 12 V
V– = 0 V
C
C
C
D(off)
D(off)
C
S(off)
S(off)
0
0
0
2
4
ꢀ
8
10
12
- 5 - 4 - 3 - 2 - 1
0
1
2
3
4
5
Drain/Source Capacitance vs. Analog Voltage
Drain/Source Capacitance vs. Analog Voltage
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8
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
DG408L/409L
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
GND
D
A
0
V+
V-
Level
Shift
Decode/
Drive
A
X
S
S
1
V+
EN
V-
n
Figure 1.
TEST CIRCUITS
V+
V+
A
A
A
2
S
V
V
1
S1
1
0
S
2
- S
7
50 Ω
S
8
DG408L
t < 20 ns
r
f
S8
t < 20 ns
3 V
0 V
V
O
EN
D
Logic
Input
3 V
50 %
GND
V-
35 pF
V
AX
300 Ω
V-
V
S1
90 %
Switch
Output
V+
V
O
50 %
A
A
1
V
S
S1
1b
90 %
V
0
S8
S
- S , D
4a
1a
a
V+
50 Ω
t
t
TRANS
TRANS
S
4b
V
SB4
DG409L
S ON
1
S
ON (DG408L)
or
ON (DG409L)
V
O
D
8
3 V
EN
b
GND
V-
S
4
35 pF
300 Ω
V-
Figure 2. Transition Time
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
www.vishay.com
9
DG408L/409L
Vishay Siliconix
TEST CIRCUITS
V+
V+
V
S1
S
1
EN
S
- S
2
8
A
A
A
0
DG408L
1
2
t < 20 ns
r
f
3 V
Logic
Input
t < 20 ns
V
O
D
50 %
GND
V-
0 V
t
50 Ω
35 pF
300 Ω
t
ON(EN)
OFF(EN)
V-
0 V
10 %
V+
V+
Switch
Output
V
O
90 %
V
S1
S
1b
V
O
EN
S
1a
- S , D
4a
a
A
0
S
- S
2b
4b
DG409L
A
1
D
V
O
b
GND
V-
50 Ω
35 pF
300 Ω
V-
Figure 3. Enable Switching Time
bbm.5
4/9
t < 20 ns
r
f
V+
t < 20 ns
3 V
0 V
Logic
Input
3 V
EN
50 %
All S and D
V
S1
a
A
A
A
0
DG408L
DG409L
1
D , D
2
b
V
O
V
S
80 %
GND
V-
Switch
Output
50 Ω
35 pF
300 Ω
V-
V
O
t
OPEN
0 V
Figure 4. Break-Before-Make Interval
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10
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
DG408L/409L
Vishay Siliconix
TEST CIRCUITS
V+
V+
R
g
3 V
0 V
S
Logic
Input
X
OFF
ON
OFF
EN
V
g
A
A
A
0
D
V
O
Channel
Select
1
ΔV
O
C
L
Switch
Output
2
1 nF
GND
V-
V-
ΔV is the measured voltage due to charge transfer
O
error Q, when the channel turns off.
Q = C x ΔV
L
O
Figure 5. Charge Injection
V+
V+
V+
V+
V
IN
V
IN
S
S
1
S
X
V
S
X
V
S
R
g
= 50 Ω
S
8
A
0
A
1
A
2
S
A
A
A
8
0
1
2
D
V
O
D
V
O
R
g
= 50 Ω
R
1 kΩ
L
R
L
GND
EN
V-
V-
1 kΩ
GND
EN
V-
V-
V
OUT
V
OUT
Off Isolation = 20 log
V
Crosstalk = 20 log
IN
V
IN
Figure 6. Off Isolation
Figure 7. Crosstalk
V+
V+
V+
V
S
S
1
V+
R
g
= 50 Ω
S
S
1
Meter
A
2
1
0
A
0
A
1
A
2
D
V
O
HP4192A
Impedance
Analyzer
Channel
Select
8
A
A
R
1 kΩ
L
or Equivalent
GND
EN
V-
V-
D
f = 1 MHz
EN
GND
V-
V-
V
OUT
Insertion Loss = 20 log
V
IN
Figure 9. Source Drain Capacitance
Figure 8. Insertion Loss
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?71342.
Document Number: 71342
S-71241–Rev. E, 25-Jun-07
www.vishay.com
11
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
www.vishay.com
1
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