DG9262_11 [VISHAY]
Low-Voltage Dual SPST Analog Switch; 低电压双通道SPST模拟开关
| 型号： | DG9262_11 |
| 厂家： | 
VISHAY |
| 描述： | Low-Voltage Dual SPST Analog Switch |
| 文件： | 总12页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG9262, DG9263
Vishay Siliconix
Low-Voltage Dual SPST Analog Switch
FEATURES
DESCRIPTION
The DG9262, DG9263 is
monolithic CMOS analog device designed for high
performance switching of analog signals. Combining low
power, high speed (tON: 35 ns, tOFF
on-resistance (RDS(on): 40 ) and small physical size, the
DG9262, DG9263 is ideal for portable and battery powered
applications requiring high performance and efficient use of
board space.
The DG9262, DG9263 is built on Vishay Siliconix’s low
voltage BCD-15 process. Minimum ESD protection, per
Method 3015.7 is 2000 V. An epitaxial layer prevents
latchup. Break-before make is guaranteed for DG9262,
DG9263.
•
Halogen-free According to IEC 61249-2-21
Definition
a
single-pole/single-throw
•
•
•
•
•
•
•
•
•
•
Low Voltage Operation (- 2.7 V to 5 V)
Low On-Resistance - RDS(on): 40
Fast Switching - tON: 35 ns, tOFF: 20 ns
Low Leakage - ICOM(on): 200-pA max.
Low Charge Injection - QINJ: 1 pC
Low Power Consumption
: 20 ns), low
TTL/CMOS Compatible
ESD Protection > 2000 V (Method 3015.7)
Available in MSOP-8 and SOIC-8
Compliant to RoHS Directive 2002/95/EC
Each switch conducts equally well in both directions when
on, and blocks up to the power supply level when off.
APPLICATIONS
•
•
•
•
•
•
•
Battery Operated Systems
Portable Test Equipment
Sample and Hold Circuits
Cellular Phones
Communication Systems
Military Radio
BENEFITS
•
•
•
•
Reduced Power Consumption
Simple Logic Interface
High Accuracy
Reduce Board Space
PBX, PABX Guidance and Control Systems
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
NO
COM
IN
V+
IN
NC
COM
IN
V+
IN
1
1
2
1
1
2
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
1
COM
COM
2
2
GND
NO
2
GND
NC
2
Top View
Top View
TRUTH TABLE - DG9263
TRUTH TABLE - DG9262
Logic
Switch
Off
Logic
Switch
On
0
1
0
1
On
Off
Logic “0” 0.8 V
Logic “1” 2.4 V
Logic “0” 0.8 V
Logic “1” 2.4 V
ORDERING INFORMATION
Temp Range
Package
Part Number
DG9262DY-E3
DG9262DY-T1
DG9262DY-T1-E3
SOIC-8
DG9263DY-E3
DG9263DY-T1
- 40 °C to 85 °C
DG9263DY-T1-E3
DG9262DQ-T1-E3
DG9263DQ-T1-E3
MSOP-8
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9262, DG9263
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Unit
- 0.3 to + 13
Reference V+ to GND
IN, COM, NC, NOa
V
- 0.3 to (V+ + 0.3)
20
40
Continuous Current (Any Terminal)
Peak Current (Pulsed at 1 ms, 10 % duty cycle)
ESD (Method 3015.7)
mA
> 2000
- 65 to 125
400
V
Storage Temperature (D Suffix)
Power Dissipation (Packages)b
°C
8-Pin Narrow Body SOICc
mW
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6.5 mW/°C above 75 °C.
SPECIFICATIONS (V+ = 3 V)
D Suffix
Test Conditions
- 40 °C to 85 °C
Unless Otherwise Specified
V+ = 3 V, 10 %, VIN = 0.8 V or 2.4 Ve
Parameter
Symbol
Temp.a Min.b
Typ.c
Max.b Unit
Analog Switch
Analog Signal Ranged
VANALOG
RDS(on)
Full
0
3
V
VNO or VNC = 1.5 V, V+ = 2.7 V
ICOM = 5 mA
Room
Full
50
80
140
Drain-Source On-Resistance
RDS(on)Matchd
RDS(on)
VNO or VNC = 1.5 V
Room
Room
0.4
4
2
8
RDS(on)
Flatness
DS(on) Flatnessd
VNO or VNC = 1 and 2 V
R
NO or NC Off Leakage
Currentg
Room
Full
- 100
- 5000
5
100
5000
INO/NC(off)
VNO or VNC = 1 V/2 V, VCOM = 2 V/1 V
Room
Full
- 100
5
100
COM Off Leakage Currentg
pA
ICOM(off)
ICOM(on)
VCOM = 1 V/2 V, VNO or VNC = 2 V/1 V
VCOM = VNO or VNC = 1 V/2 V
- 5000
5000
Room
Full
- 200
- 10 000
10
200
10 000
Channel-On Leakage Currentg
Digital Control
IINL or IINH
Input Current
Full
1
µA
ns
Dynamic Characteristics
Room
Full
50
20
120
200
tON
Turn-On Time
Turn-Off Time
VNO or VNC = 1.5 V
Room
Full
50
120
tOFF
QINJ
Charge Injectiond
Off-Isolation
Crosstalk
CL = 1 nF, VGEN = 0 V, RGEN = 0
RL = 50 , CL = 5 pF, f = 1 MHz
Room
Room
Room
Room
Room
Room
1
- 74
- 90
7
5
pC
dB
OIRR
XTALK
C(off)
NC and NO Capacitance
Channel-On Capacitance
CCOM(on)
CCOM(off)
f = 1 MHz
20
pF
COM-Off Capacitance
Power Supply
13
Power Supply Range
Power Supply Current
V+
I+
2.7
12
1
V
V+ = 3.3 V, VIN = 0 V or 3.3 V
µA
Notes:
a. Room = 25 °C, full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Difference of min and max values.
g. Guraranteed by 5 V leakage testing, not production tested.
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Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9262, DG9263
Vishay Siliconix
SPECIFICATIONS (V+ = 5 V)
D Suffix
Test Conditions
- 40 °C to 85 °C
Unless Otherwise Specified
V+ = 5 V, 10 %, VIN = 0.8 V or 2.4 Ve
Parameter
Symbol
Temp.a
Min.b
Typ.c
Max.b
Unit
Analog Switch
Analog Signal Ranged
VANALOG
RDS(on)
Full
0
5
V
VNO or VNC = 3.5 V, V+ = 4.5 V
ICOM = 5 mA
Room
Full
30
60
75
Drain-Source On-Resistance
RDS(on)Matchd
RDS(on)
VNO or VNC = 3.5 V
Room
Room
0.4
2
6
RDS(on)
Flatness
DS(on) Flatnessf
VNO or VNC = 1, 2 and 3 V
2
R
Room
Full
- 100
10
100
INO/NC(off)
ICOM(off)
ICOM(on)
VNO or VNC = 1 V/4 V, VCOM = 4 V/1 V
VCOM = 1 V/4 V, VNO or VNC = 4 V/1 V
VCOM = VNO or VNC = 1 V/4 V
NO or NC Off Leakage Current
COM Off Leakage Current
Channel-On Leakage Current
- 5000
5000
Room
Full
- 100
- 5000
10
100
5000
pA
Room
Full
- 200
- 10 000
200
10 000
Digital Control
IINL or IINH
Input Current
Full
1
µA
ns
Dynamic Characteristics
Room
Full
35
20
75
tON
Turn-On Time
Turn-Off Time
150
VNO or VNC = 3 V
Room
Full
50
100
tOFF
QINJ
Charge Injectiond
Off-Isolation
Crosstalk
CL = 1 nF, VGEN = 0 V, RGEN = 0
RL = 50 , CL = 5 pF, f = 1 MHz
Room
Room
Room
Room
Room
Room
2
- 74
- 90
7
5
pC
dB
OIRR
XTALK
C(off)
CD(on)
NC and NO Capacitance
Channel-On Capacitance
f = 1 MHz
20
pF
CCOM(off)
COM-Off Capacitance
Power Supply
13
Power Supply Range
Power Supply Current
V+
I+
2.7
12
1
V
V+ = 5.5 V, VIN = 0 V or 5.5 V
µA
Notes:
a. Room = 25 °C, full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Difference of min and max values.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9262, DG9263
Vishay Siliconix
TYPICAL CHARACTERISTICS (25°C, unless otherwise noted)
2.0
1.5
3000
2500
2000
1500
1000
500
V+ = 3 V
1.0
0.5
0.0
V+ = 5 V
- 0.5
- 1.0
- 1.5
- 2.0
0
V+ = 3 V
- 500
0.0
0.5
1.0
1.5
2.0
2.5
3.0
125
5
0
1
2
3
4
5
V
V
IN
COM
Charge Injection
Supply Current vs. VIN
10 nA
1 nA
- 40
- 60
100 pA
- 80
I
COM(off)
10 pA
1 pA
I
COM(on)
- 100
- 120
- 140
0.1 pA
25
45
65
85
105
0.001 M
0.01 M
0.1 M
1 M
10 M
Temperature (°C)
Frequency (Hz)
Leakage Current vs. Temperature
Off-Isolation vs. Frequency
80
60
40
20
2.5
2.0
V+ = 5 V
1.5
V+ = 3 V
1.0
I
COM
0.5
0.0
V+ = 5 V
- 0.5
- 1.0
- 1.5
- 2.0
- 2.5
I
NO/NC
0
0
0
1
2
3
4
1
2
3
4
5
V
V
COM
COM
Off-Leakage vs. Voltage at 25 °C
RDS vs. VCOM
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Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9262, DG9263
Vishay Siliconix
TYPICAL CHARACTERISTICS (25°C, unless otherwise noted)
80
60
40
20
0
70
V+ = 3 V
60
50
40
30
20
10
0
t
ON
85 °C
25 °C
40 °C
t
OFF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
- 60
- 30
0
30
60
90
120
V
COM
Temperature (°C)
RDS vs. VCOM
Switching Time vs. Temperature
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
120
100
80
60
40
20
0
t
ON
t
OFF
2
3
4
5
6
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V+
V+
tON/tOFF vs. Power Supply Voltage
Input Switching Point vs. Power Supply Voltage
Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9262, DG9263
Vishay Siliconix
TEST CIRCUITS
V+
V+
+ 3 V
0 V
Logic
Input
t < 20 ns
f
50 %
r
t < 20 ns
Switch Output
NO or NC
COM
Switch
Input
V
OUT
0.9 x V
OUT
IN
Switch
Output
R
L
C
L
300
35 pF
0 V
GND
Logic
Input
t
t
OFF
ON
0 V
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
C
L
(includes fixture and stray capacitance)
R
L
+ R
V
= V
COM
OUT
R
L
ON
Figure 1. Switching Time
V+
Logic
Input
3 V
0 V
t < 5 ns
r
t < 5 ns
f
V+
COM
COM
NO or NC
NO or NC
1
V
V
1
2
2
V
= V
NO
NC
R
300
C
L
35 pF
L
V
90 %
O
GND
Switch
Output
0 V
t
D
t
D
C
L
(includes fixture and stray capacitance)
Figure 2. Break-Before-Make Interval
V+
V+
V
OUT
R
gen
V
OUT
NC or NO
IN
COM
V
OUT
+
IN
V
gen
C
L
On
On
Off
Q = V
3 V
GND
x C
OUT
L
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 3. Charge Injection
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Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9262, DG9263
Vishay Siliconix
TEST CIRCUITS
V+
V+
10 nF
COM
0 V, 2.4 V
IN
COM
NC or NO
V
NC/NO
Off Isolation = 20 log
R
L
V
COM
GND
Analyzer
Figure 4. Off-Isolation
V+
10 nF
V+
COM
Meter
IN
HP4192A
Impedance
Analyzer
0 V, 2.4 V
or Equivalent
NC or NO
GND
f = 1 MHz
Figure 5. Channel Off/On Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70862.
Document Number: 70862
S11-1229–Rev. D, 20-Jun-11
www.vishay.com
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
2
5
4
E
H
1
3
S
h x 45
D
C
0.25 mm (Gage Plane)
A
All Leads
0.101 mm
q
e
B
A
1
L
0.004"
MILLIMETERS
Max
INCHES
DIM
A
Min
Min
Max
1.35
0.10
0.35
0.19
4.80
3.80
1.75
0.20
0.51
0.25
5.00
4.00
0.053
0.004
0.014
0.0075
0.189
0.150
0.069
0.008
0.020
0.010
0.196
0.157
A1
B
C
D
E
e
1.27 BSC
0.050 BSC
H
h
5.80
0.25
0.50
0°
6.20
0.50
0.93
8°
0.228
0.010
0.020
0°
0.244
0.020
0.037
8°
L
q
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
Package Information
Vishay Siliconix
MSOP: 8−LEADS
JEDEC Part Number: MO-187, (Variation AA and BA)
(N/2) Tips)
2X
5
A
B C 0.20
N N-1
0.48 Max
Detail “B”
(Scale: 30/1)
Dambar Protrusion
E
1
2
N/2
0.50
0.60
M
S
S
A
0.08
C
B
7
b
Top View
e1
b
1
With Plating
e
A
See Detail “B”
c
c
1
0.10
C
6
Section “C-C”
Scale: 100/1
(See Note 8)
-H-
A
1
Seating Plane
Base Metal
D
-A-
3
See Detail “A”
Side View
0.25
BSC
C
C
Parting Line
0.07 R. Min
2 Places
ς
S
A
2
0.05
Seating Plane
E
1
-B-
L
4
-C-
T
3
0.95
End View
Detail “A”
(Scale: 30/1)
NOTES:
N = 8L
1. Die thickness allowable is 0.203"0.0127.
MILLIMETERS
2. Dimensioning and tolerances per ANSI.Y14.5M-1994.
Dim
Min
Nom
Max
Note
3. Dimensions “D” and “E ” do not include mold flash or protrusions, and are
1
-
-
0.10
1.10
0.15
0.95
0.38
0.33
0.23
0.18
A
A1
A2
b
b1
c
c1
D
E
E1
e
e1
L
measured at Datum plane -H- , mold flash or protrusions shall not exceed
0.15 mm per side.
0.05
0.75
0.25
0.25
0.13
0.13
0.85
4. Dimension is the length of terminal for soldering to a substrate.
5. Terminal positions are shown for reference only.
-
8
8
0.30
-
6. Formed leads shall be planar with respect to one another within 0.10 mm at
seating plane.
0.15
7. The lead width dimension does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the lead width
dimension at maximum material condition. Dambar cannot be located on the
lower radius or the lead foot. Minimum space between protrusions and an
adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”.
3.00 BSC
4.90 BSC
3.00
3
3
2.90
3.10
0.65 BSC
1.95 BSC
0.55
8. Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip.
9. Controlling dimension: millimeters.
0.40
0.70
4
5
8
N
T
10. This part is compliant with JEDEC registration MO-187, variation AA and BA.
11. Datums -A- and -B- to be determined Datum plane -H- .
12. Exposed pad area in bottom side is the same as teh leadframe pad size.
0_
4_
6_
ECN: T-02080—Rev. C, 15-Jul-02
DWG: 5867
Document Number: 71244
12-Jul-02
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050
1.27
0.088
2.25
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
0.288
7.3
0.050
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
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1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
0.022
0.050
(0.559)
(1.270)
Recommended Minimum Pads
Dimensions in Inches/(mm)
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Document Number: 72606
Revision: 21-Jan-08
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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