IHLP3232DZER2R2_技术文档

SiC401, SiC402, SiC403

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Vishay Siliconix

Reference Board User’s Manual for SiC403 (6 A), SiC402 (10 A),

and SiC401 (15 A) Synchronous Buck Regulators

FEATURES

PRODUCT SUMMARY SiC401A, SIC401BCD

• SiC401A/B: 3 V to 17 V input range.

Input Voltage Range

Output Voltage Range

Operating Frequency

Continuous Output Current

Package

3 V to 17 V

0.6 V to V_INx 0.75

200 kHz to 1 MHz

15 A

SiC402A/B, SiC403A/B: 3 V to 28 V input range.

• Adjustable output voltage down to 0.6 V

• 6 A (SiC403), 10 A (SiC402), and 15 A (SiC401) continuous

output current

MLP55-32L

• Selectable frequency from 200 kHz to 1 MHz with an

external resistor

PRODUCT SUMMARY SiC402A, SIC402BCD

• 95 % peak efficiency

Input Voltage Range

Output Voltage Range

Operating Frequency

Continuous Output Current

Package

3 V to 28 V

0.6 V to V_INx 0.75

200 kHz to 1 MHz

10 A

• Stable with any capacitor; no external ESR network

required

• Ultrafast transient response

• Power saving scheme for increased light load efficiency

MLP55-32L

•

1 % accuracy of V_OUTsetting

• Cycle-by-cycle current limit

PRODUCT SUMMARY SiC403A, SIC403BCD

• Fully protected with OTP, SCP, UVP, OVP

• P_GOODIndicator

Input Voltage Range

Output Voltage Range

Operating Frequency

Continuous Output Current

Package

3 V to 28 V

0.6 V to V_INx 0.75

200 kHz to 1 MHz

6 A

• -40 °C to +125 °C operating junction temperature

• Output voltage tracking

MLP55-32L

APPLICATIONS

Note

External divider network needed

• Point of load regulation for low-power processors,

network processors, DSPs, FPGAs, and ASICs

•

• Low voltage, distributed power architectures with 5 V or

12 V, or 24 V rails

DESCRIPTION

The SiC401, SiC402, and SiC403 are high frequency

voltage-mode constant-on-time (CM-COT) synchronous

buck regulators with integrated high-side and low-side

power MOSFETs. The SiC403 is capable of 6 A continuous

current, the SiC402 is capable of 10 A and the SiC401 15 A.

These regulators produce an adjustable output voltage

which in standard setup can output 5 V down to 0.6 V

and with the V_OUTdivider network 75 % of V_INdown to

0.6 V to accommodate a variety of applications, including

computing, consumer electronics, telecom, and industrial.

• Computing, broadband, networking, LAN / WAN, optical,

test, and measurement

• A / V, high density cards, storage, DSL, STB, DVR, DTV,

industrial PC

ORDERING INFORMATION

BOARD PART NUMBER

MAX. OUTPUT CURRENT

SiC403DB-LC

6 A

SiC402DB-HC

10 A

15 A

The CM-COT architecture delivers ultra-fast transient

response with minimum output capacitance and tight ripple

regulation at very light load. The parts are stable with any

capacitor type and no ESR network is required for loop

stability. The regulator integrates a full protection feature

set, it also has UVLO for the input rail and an internal

soft-start.

SiC401DB-HC

Notes

•

LC - low current inductor, HC - high current inductor

The only difference between HC and LC board is the O / P

inductor size

The SiC40X family is available in lead (Pb)-free power

enhanced 5 mm x 5 mm MLP55-32L package.

Revision: 17-Nov-14

Document Number: 62923

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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SPECIFICATIONS

Vishay Siliconix

Output Voltage Sense

V_{OUT_SENSE}, GND_{OUT_SENSE}(P4): This allows the user to

measure the voltage at the output of the regulator and

remove any losses generated due to the connections, from

the measurement. This can also be used by an active load

with sense capability.

This reference board allows the end user to evaluate the

SiC401, SiC402, or the SiC403 chip for its features and all

functionalities.

It can also be a reference design for a user’s application.

PGD (P9): Is an open drain output and is pulled up with a

10 kΩ resistor to V_IN. When FB or V_OUTare within -10 % to

+20 % percent of the set voltage this pin will go HI to

indicate the output is okay. The pin will also follow EN/PSV

condition switching LO if the IC is disabled.

CONNECTION AND SIGNAL / TEST POINTS

Power Sockets

V_IN, GND (P1): Input voltage source with V_INto be positive.

Connect to a voltage source:

- SiC401A/BCD - 3 V to 17 V

- SiC402A/BCD - 3 V to 28 V

- SiC403A/BCD - 3 V to 28 V

POWER UP PROCEDURE

To turn-on the reference board, apply 12 V to V_INwith the

P6 jumper is in Position 1. If the P7 jumper is in place the

board will come up in power save mode, if not in place then

constant P_WMwill be observed.

V_OUT, GND (P3): Output voltage with V_OUTto be positive.

Connect to a load that draws no more than:

• SiC401A/BCD - 15 A

When applying higher than 12 V to the input it is reasonable

to install a RC snubber from LX to GND. There are place

holders on the reference board R9 and C11 for the snubber.

Values of 10 Ω and 1 nF are a reasonable starting point.

• SiC402A/BCD - 10 A

• SiC403A/BCD - 6 A

5 V, GND (P5): External 5 V voltage source with 5 V to be

positive. Connect to a 5 V source when this option is

selected.

ADJUSTMENTS TO THE REFERENCE BOARD

OUTPUT VOLTAGE ADJUSTMENT

SELECTION JUMPERS

If a different output voltage is needed, simply change the

value of V_OUTand solve for R12 based on the following

formula:

Mode Select

P7: This is a 2 way header which allows the user to select

either power save mode or constant P_WMmode.

V_OUT- V_FB

-----------------------------

R₁₂= R₁₃x

OPEN - forced P_WM, the pin is floating

V_FB

SHORT - power save mode, the pin is at 5 V

Where V_FBis 0.6 V for the SiC40X.

A third option is available whereby pin 2 is shorted to 0 V to

disable the part.

CHANGING SWITCHING FREQUENCY

UVLO Option

The following equation illustrates the relationship between

ON-time, V_IN, V_OUT, and R_ONvalue:

P8: This is a 2 way header that will enable the UVLO function

when selected. The divider resistors R1 and R2 can be

changed depending on the required turn on voltage level,

the pin requires a voltage greater than 3 V to enable.

k

--------------------------------

R_tON

=

25 pF x F_SW

OPEN - UVLO disabled

SHORT - UVLO enabled

Where k equals 1 when V_DDis greater than 3.6 V. When k is

less than 3.6 V and V_INis greater than ((V_DD- 1.75 V) x 10),

k is shown by the following equation:

V_DDSelect

P6: This is a 3 way header that will enable the user to select

between internal LDO and an external 5 V supply.

(V_DD- 1.75 V) x 10

----------------------------------------------------

k =

V_IN

Position 1 - SHORT PIN 1-2 - internal LDO

Position 2 - SHORT PIN 2-3 - external 5 V

The maximum R_tonvalue allowed is shown:

V_{IN min.}

SIGNALS AND TEST LEADS

------------------

=

R_{tON MAX.}

15 μA

Input Voltage Sense

V_{IN_SENSE}, GND_{IN_SENSE}(P2): This allows the user to

measure the voltage at the input of the regulator and remove

any losses generated due to the, connections from the

measurement. This can also be used by a power source with

sense capability.

Revision: 17-Nov-14

Document Number: 62923

2

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC401, SiC402, SiC403

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Vishay Siliconix

Other than the inductance the DCR and saturation current

parameters are key values. The DCR causes an I²R loss

which will decrease the system efficiency and generate

heat. The saturation current has to be higher than the

maximum output current plus 1/2 the ripple current. In over

current condition the inductor current may be very high. All

this needs to be considered when selecting the inductor.

OUTPUT RIPPLE VOLTAGE

Output ripple voltage is measured with a tip and barrel

measurement across C_OUT. Typically output ripple voltage

is set to 3 % to 5 % of the output voltage, but an all ceramic

output solution can bring output ripple voltage to a much

lower level since the ESR of ceramics is very small.

If ceramics or a combination of ceramics and bulk

capacitors are used it may be necessary to add a voltage

injection network.

On this board Vishay IHLP series inductors are used to meet

cost requirement and high efficiency, a part that utilizes a

material that has incredible saturation levels compared to

competing products.

VOLTAGE INJECTION NETWORK

This is the network seen placed across the output inductor

in the schematic consisting of R8, C9, and C10. A quick

method to add or remove injection is to reduce or increase

R4.

OUTPUT CAPACITOR SELECTION

Voltage rating, ESR, transient response, overall PCB area

and cost are requirements for selecting output capacitors.

The types of capacitors and there general advantages and

disadvantages are covered next.

The time constant of the inductor (τ_IND) and voltage injection

network are as follows:

Electrolytic have high ESR, dry out over time so ripple

current rating must be examined and have slower transient

response, but are fairly inexpensive for the amount of overall

capacitance.

L

DCR

------------

τ_IND

=

and

τ_RIN= R_Lx C_L

Tantalums can come in low ESR varieties and high

capacitance value for its overall size, but they fail short when

damaged and also have slower transient response.

In (1) the recommended value of C9 = 10 nF.

The injection voltage can be checked for magnitude next

using the following equation,

Ceramics have very low ESR, fast transient response and

overall small size, but come in low capacitance values

compared to the others above. A combination of technology

is sensible.











1

----------

V_INJ= (V_{IN MIN.}- V_OUT) x 1 -



t

---------





e^τ

RIN

LDO SETTING

In order that the LDO is programmed to 5 V the divider

resistors from the V_DDpin to the FBL pin need to be set in

order that 0.75 V is present on FBL. They can be set as

Where t is the ON period. This required magnitude is

> 20 mV_ppfor stable operation, when the ripple injection

voltage is smaller than 20 mV_ppthen double pulsing may be

observed as the thresholds are not correctly triggered within

the SiC40X.

follows:

V_DDx R₈

------------------------

=

V_LDO

R₂+ R₈

The injection voltage will be DC decoupled from the FB pin

via a capacitor, the calculation for this part is as follows:

ENABLE PIN VOLTAGE

1

3

--------- -------------------------------

C₁₀

=

x

The ENL pin will need to be set to enable the LDO. This pin

accepts an input voltage up to V_INhowever it can also be set

as an under voltage trigger. The operation for this pin can be

seen in Table 1.

R₁₂2 x π x F_SW

--------

R₁₃

INDUCTOR SELECTION

The choice of inductor is specific to each application and

quickly determined with the following equations:

TABLE 1

EN/PSV

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

ENL

LDO

Off

On

SWITCHER

V_OUT

Low, < 0.4 V

Off

On

Off

On

-------------------------------------

=

t_ON

V_{IN MAX.}x f_SW

Low, < 0.4 V

1 V < High < 2.6 V

High > 2.6 V

(V_IN- V_OUT) x t_ON

--------------------------------------------------

I_{OUT MAX.}x k₂

L =

Where k₂is a percentage of maximum output current ripple

required. The designer can quickly make a choice if the

ripple percentage is decided, usually no more than 30 %

however higher or lower percentages of I_OUTcan be

acceptable depending on application.

High > 2.6 V

Revision: 17-Nov-14

Document Number: 62923

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For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC401, SiC402, SiC403

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Vishay Siliconix

The UVLO will be activated if the voltage present at this pin

is below 2.6 V. This can be set using the following equation.

If under voltage is not a consideration then this can be

connected to V_IN. The divider values for this pin can be set

using the following equation:

Where I_LPKis the peak inductor current, I_MAX.is the

maximum output current, dI_LOADis the current step in μF

and V_PKis the peak voltage, the output voltage summed

with the specified over and under shoot.

V_INx R₉

INPUT CAPACITANCE

----------------------

=

V_ENL

R₁+ R₉

In order to keep the design compact and minimize parasitic

elements, ceramic capacitors will be chosen. The initial

requirement for the input capacitance is decided by the

maximum input voltage, 16 V in this case however a 35 V

rated capacitor will be chosen of the X7R variety. The

footprint will be a compact 1206.

SOFT START SETTING

Soft start is a useful function helping to limit the current draw

from the source at switch on. This is simply set with a

ceramic capacitor using the following equation:

t_SS

In order to determine the minimum capacitance the input

voltage ripple needs to be specified; V_CINPP≤ 150 mV is a

suitable starting point. This magnitude is determined by the

final application specification. The input current needs to be

determined for the lowest operating input voltage:

I_OUT

---------------------

=

C_SS

500 000

A 2. 2 nF capacitor will provide ~ 1 ms soft start time.

BOOTSTRAP CIRCUIT

-----------

I_CIN(RMS)

=

x

V_OUTx (V_IN- V_OUT)

A bootstrap capacitor of 100 nF will be sufficient for this

circuit with switching frequencies from 200 kHz to 500 kHz.

A series resistor has been added in order to slow down the

low side switch in and minimize overshoot without adding a

snubber. This is user adjustable.

V_IN

The minimum input capacitance can then be found,

DC - (1 - DC)

--------------------------------------

x

C_{IN MIN.}= I_OUT

V_CINPPx F_SW

V_DDDECOUPLING

HIGH OUTPUT VOLTAGE OPERATION

The V_DDpin will need to be decoupled in order to provide a

stable voltage internally and externally. The value for this

capacitor is recommended as ≥ 1 μF.

For the SiC40X family the recommended maximum output

voltage of no more than 75 % of V_IN.

For applications where an output voltage greater than 5 V is

required a resistive network should be used to step down

the output voltage in order to provide the V_OUTpin with

4.5 V.

CURRENT LIMIT RESISTOR

The current limit is set by placing a resistor between pins

LXS and ILIM. The values can be found using the following

equations.

R₂x (V_OUT- V_{OUT PIN}

)

-------------------------------------------------------------

R₁=

V_{OUT PIN}

SiC401:

For example, if an output voltage of V_OUT= 8.5 V is

required, setting R₂= 10 kΩ and V_{OUT PIN}= 4.5 V results in

R₁= 8870 Ω.

R_ILIM= 792 x I_LIMx [0.101 x (5 V - V_DD) + 1]

SiC402:

The switching frequency will also need recalculating using a

R_ILIM= 446 x I_LIMx [0.099 x (5 V - V_DD) + 1]

V

_{OUT PIN}magnitude of 4.5 V.

V_{OUT PIN}

------------------------

t_ONx V_IN

SiC403:

F_SW

=

R_ILIM= 1176 x I_LIMx [0.112 x (5 V - V_DD) + 1]

OUTPUT CAPACITANCE

LX

V_OUT

The output capacitance will be determined by the ripple

voltage requirement. Voltage mode COT topology can work

with very small values of capacitor ESR however a ripple

injection network will also be required for stable operation.

R₁

R₂

SiC40X

C_OUT

V_{OUT PIN}

The overall capacitance needs to be calculated next. The

following equations are used to calculate the size needed to

meet a transient load response:

I_LPK= I_MAX.+ 0.5 x I_{RIPPLE MAX,}

Fig. 1 - Resistor Divider Network Allows 4.5 V at the V_{OUT PIN}

I_LPK

------------- -----------------

x dt

I_MAX.

L x

-

V_OUTdI_LOAD

--------------------------------------------------------------

x

C_{OUT MIN.}= I_LPK

2 x (V_PK- V_OUT

)

Revision: 17-Nov-14

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7. If a voltage injection network is needed then place it near

to the inductor LX node.

LAYOUT CONSIDERATIONS

The SiC40x family of footprint compatible 15 A, 10 A, and

6 A products offers the designer a scalable buck regulator

solution. If the below layout recommendations are followed,

the same layout can be used to cover a wide range of output

currents and voltages without any changes to the board

design and only minor changes to the component values in

the schematic.

8. P_GNDcan be used on internal layers if the resistance of

the PCB is to be small; this will also help remove heat.

Use extra vias if needed but be mindful to allow a path

between the vias.

9. A quiet plane should be employed for the A_GND, this is

placed under the small signal passives. This can be

placed on multiple layers if needed for heat removal. This

should be connected to the P_GNDplane near to the input

GND at one connection only of at least 1mm width.

The reference design has a majority of the components

placed on the top layer. This allows for easy assembly and

straightforward layout.

10. The LX copper can also be used on multiple layers, use

a number of vias.

Figure 2 outlines the pointers for the layout considerations

and the explanations follow.

11. The copper area beneath the inductor has been removed

(on all layers) in this design to reduce the inductive

coupling that occurs between the inductor and the GND

trace. No other voltage planes should be placed under

this area.

Fig. 2 - Resistor Divider Network Allows 4.5 V at the V_{OUT PIN}

1. Place input ceramic capacitors close to the voltage input

pins with a small 10 nF / 100 nF placed as close as the

design rules will allow. This will help reduce the size of

the input high frequency current loop and consequently

reduce the high frequency ripple noise seen at the input

and the LX node.

2. Place the setup and control passive devices logically

around the IC with the intention of placing a quiet ground

plane beneath them on a secondary layer.

3. It is advisable to use ceramic capacitors at the output to

reduce impedance. Place these as close to the IC P_GND

and output voltage node as design will allow. Place a

small 10 nF / 100 nF ceramic capacitor closest to the IC

and inductor loop.

4. The loop between LX, V_OUTand the IC GND should be as

compact as possible. This will lower series resistance

and also make the current loop smaller enabling the high

frequency response of the output capacitors to take

effect.

5. The output impedance should be small when high

current is required; use high current traces, multiple

layers can be used with many vias.

6. Use many vias when multiple layers are involved. This

will have the effect of lowering the resistance between

layers and reducing the via inductance of the PCB nets.

Revision: 17-Nov-14

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PCB LAYOUT

Fig. 3 - Top Layer

Fig. 5 - Inner Layer 2

Fig. 4 - Inner Layer 1

Fig. 6 - Bottom Layer

Revision: 17-Nov-14

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SCHEMATIC - COMMON TO ALL BOARDS

Revision: 17-Nov-14

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BILL OF MATERIAL FOR SIC401 (V_IN= 12 V, V_OUT= 1.5 V, F_SW= 500 kHz)

ITEM

QTY

REFERENCE

PCB FOOTPRINT

VALUE VOLTAGE

PART NUMBER

MANUFACTURER

TDK

1

2

3

4

5

6

2

3

1

2

1

C1, C2

1206

0402

Omit

22 μF

10 nF

2.2 μF

2.2 nF

100 nF

35 V

50 V

10 V

50 V

35 V

C3216X5R1V226M160AC

GRM155R71H103KA88D

C0402C225M8PACTU

C3, C4

TDK

C5, C9, C12

C6

Murata

Kemet

C7, C10

C8

GRM155R71H222KA01D

CGA2B3X7R1V104K050BB

Murata

Vishay

C13, C14, C15, C16,

C17

7

5

1206

47 μF

35 V

GRM31CR61A476ME15L

Murata

8

3

2

4

5

1

C18, C19, C20

1206

7343

Omit

-

35 V

GRM31CR61A476ME15L

-

Murata

-

9

C21, C22

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

P1, P3, P9, P10

Banana Jack

Header-2

Header-3

IHLP5050

0402

575-4K-ND

Keystone

AMP (TE)

Samtec

Vishay

-

P2, P4, P5, P7, P8

-

826926-2

P6

L1

-

HTSW-103-08-T-S

IHLP5050FDER1R0

CRCW0402249KFKED

CRCW0402100KFKED

CRCW0402169KFKED

CRCW040230K0FKED

CRCW04025K11FKED

CRCW040276K8FKED

CRCW040210R0FKEA

CRCW040210K0FKED

-

1 μH

249K

100K

169K

30K

5K11

76K8

10R

10K

Omit

0R

R1

R2

0402

R3

0402

R4

0402

R5

0402

R6

0402

R7

0402

R8

0402

R9

0805

R10

R11

R12

R13

R14

R15

U1

0402

CRCW04020000Z0ED

-

0402

Omit

1K54

1K

0402

CRCW04021K54FKED

CRCW0402249KFKED

CRCW040210R0FKEA

CRCW040210K0FKED

-

0402

10R

10K

SIC401

0402

MLP55-33

KEY

Only needed for reference board

Revision: 17-Nov-14

Document Number: 62923

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For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC401, SiC402, SiC403

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Vishay Siliconix

BILL OF MATERIAL FOR SIC402 (V_IN= 12 V, V_OUT= 1.5 V, F_SW= 500 kHz)

ITEM

QTY

REFERENCE

PCB FOOTPRINT

VALUE VOLTAGE

PART NUMBER

MANUFACTURER

TDK

1

2

3

4

5

6

7

2

3

1

2

1

3

C1, C2

1206

0402

1206

Omit

22 μF

10 nF

2.2 μF

2.2 nF

100 nF

47 μF

35 V

50 V

10 V

50 V

35 V

C3216X5R1V226M160AC

GRM155R71H103KA88D

C0402C225M8PACTU

C3, C4

TDK

C5, C9, C12

C6

Murata

Kemet

C7, C10

C8

GRM155R71H222KA01D

CGA2B3X7R1V104K050BB

GRM31CR61A476ME15L

Murata

Vishay

C13, C14, C15

Murata

C16, C17, C18, C19,

C20

8

5

1206

Omit

35 V

GRM31CR61A476ME15L

Murata

9

2

4

5

1

C21, C22

7343

Banana Jack

Header-2

Header-3

IHLP4040

0402

Omit

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

P1, P3, P9, P10

575-4K-ND

Keystone

AMP (TE)

Samtec

Vishay

-

P2, P4, P5, P7, P8

-

826926-2

P6

L1

-

HTSW-103-08-T-S

IHLP4040DZER1R0

CRCW0402249KFKED

CRCW0402100KFKED

CRCW0402169KFKED

CRCW040230K0FKED

CRCW04025K11FKED

CRCW040276K8FKED

CRCW040210R0FKEA

CRCW040210K0FKED

-

1 μH

249K

100K

169K

30K

5K11

76K8

10R

10K

Omit

0R

R1

R2

0402

R3

0402

R4

0402

R5

0402

R6

0402

R7

0402

R8

0402

R9

0805

R10

R11

R12

R13

R14

R15

U1

0402

CRCW04020000Z0ED

-

0402

Omit

1K54

1K

0402

CRCW04021K54FKED

CRCW0402249KFKED

CRCW040210R0FKEA

CRCW040210K0FKED

-

0402

10R

10K

SIC402

0402

MLP55-33

KEY

Only needed for reference board

Revision: 17-Nov-14

Document Number: 62923

9

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC401, SiC402, SiC403

www.vishay.com

Vishay Siliconix

BILL OF MATERIAL FOR SIC403 LC (V_IN= 12 V, V_OUT= 1.5 V, F_SW= 500 kHz)

ITEM

QTY

REFERENCE

C1, C2, C3

C4

PCB FOOTPRINT

VALUE VOLTAGE

PART NUMBER

MANUFACTURER

TDK

1

2

3

4

5

6

7

3

1

3

1

2

1

2

1206

0402

1206

Omit

22 μF

10 nF

2.2 μF

1 nF

35 V

50 V

10 V

50 V

35 V

C3216X5R1V226M160AC

GRM155R71H103KA88D

C0402C225M8PACTU

TDK

C5, C9, C12

C6

Murata

Kemet

C7, C10

C8

GRM155R71H102KA01D

CGA2B3X7R1V104K050BB

GRM31CR61A476ME15L

Murata

100 nF

47 μF

Vishay

C13, C14

Murata

C15, C16, C17

C18, C19, C20

8

6

1206

Omit

35 V

GRM31CR61A476ME15L

Murate

9

2

4

5

1

C21, C22

7343

Banana Jack

Header-2

Header-3

IHLP3232

0402

Omit

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

P1, P3, P9, P10

575-4K-ND

Keystone

AMP (TE)

Samtec

Vishay

-

P2, P4, P5, P7, P8

-

826926-2

P6

L1

-

HTSW-103-08-T-S

IHLP3232DZER2R2

CRCW0402249KFKED

CRCW0402100KFKED

CRCW0402169KFKED

CRCW040230K0FKED

CRCW04025K11FKED

CRCW040276K8FKED

CRCW040210R0FKEA

CRCW040210K0FKED

-

2.2 μH

249K

100K

169K

30K

5K11

76K8

10R

10K

Omit

0R

R1

R2

0402

R3

0402

R4

0402

R5

0402

R6

0402

R7

0402

R8

0402

R9

0805

R10

R11

R12

R13

R14

R15

U1

0402

CRCW04020000Z0ED

-

0402

Omit

1K54

1K

0402

CRCW04021K54FKED

CRCW0402249KFKED

CRCW040210R0FKEA

CRCW040210K0FKED

-

0402

10R

10K

SIC403

0402

MLP55-33

KEY

Only needed for reference board

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?62923.

Revision: 17-Nov-14

Document Number: 62923

10

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000


型号：	IHLP3232DZER2R2
厂家：	VISHAY
描述：	Selectable frequency from 200 kHz to 1 MHz with an external resistor
文件：	总10页 (文件大小：632K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IHLP3232DZER2R2 [VISHAY]

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