SI3900DV_09 [VISHAY]
Dual N-Channel 20-V (D-S) MOSFET; 双N通道20 -V （D -S ）的MOSFET
| 型号： | SI3900DV_09 |
| 厂家： | 
VISHAY |
| 描述： | Dual N-Channel 20-V (D-S) MOSFET |
| 文件： | 总9页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3900DV
Vishay Siliconix
Dual N-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
ID (A)
2.4
Definition
0.125 at VGS = 4.5 V
0.200 at VGS = 2.5 V
•
•
TrenchFET® Power MOSFET
Compliant to RoHS Directive 2002/95/EC
20
1.8
TSOP-6
Top View
G1
S2
G2
D1
S1
D2
1
2
3
6
5
D
1
D
2
3 mm
4
G
G
2
1
2.85 mm
S
S
2
1
Ordering Information: Si3900DV-T1-E3 (Lead (Pb)-free)
Si3900DV-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
5 s
Steady State
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
20
8
V
VGS
12
TA = 25 °C
A = 85 °C
2.4
1.7
2.0
1.4
Continuous Drain Current (TJ = 150 °C)a
ID
T
A
IDM
IS
Pulsed Drain Current (10 µs Pulse Width)
Continuous Source Current (Diode Conduction)a
1.05
1.15
0.59
0.75
0.83
0.53
TA = 25 °C
TA = 85 °C
Maximum Power Dissipationa
PD
W
TJ, Tstg
Operating Junction and Storage Temperature Range
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
93
Maximum
110
Unit
t ≤ 5 s
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
RthJA
Steady State
Steady State
130
75
150
°C/W
RthJF
90
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
Document Number: 71178
S09-2275-Rev. D, 02-Nov-09
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1
Si3900DV
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
IGSS
VDS = VGS, ID = 250 µA
Gate Threshold Voltage
0.6
1.5
100
1
V
VDS = 0 V, VGS
=
12 V
Gate-Body Leakage
nA
VDS = 20 V, VGS = 0 V
DS = 20 V, VGS = 0 V, TJ = 85 °C
VDS ≥ 5 V, VGS = 4.5 V
IDSS
ID(on)
Zero Gate Voltage Drain Current
µA
A
V
10
On-State Drain Currenta
5
VGS = 4.5 V, ID = 2.4 A
0.100
0.160
5
0.125
0.200
Drain-Source On-State Resistancea
RDS(on)
Ω
V
GS = 2.5 V, ID = 1.0 A
Forward Transconductancea
Diode Forward Voltagea
Dynamicb
gfs
VDS = 5 V, ID = 2.4 A
IS = 1.05 A, VGS = 0 V
S
V
VSD
0.79
1.10
4.0
Qg
Qgs
Qgd
td(on)
tr
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
2.1
0.3
0.4
10
30
14
6
VDS = 10 V, VGS = 4.5 V, ID = 2.4 A
nC
ns
17
50
25
12
50
V
DD = 10 V, RL = 10 Ω
ID ≅ 1 A, VGEN = 4.5 V, Rg = 6 Ω
td(off)
tf
Turn-Off Delay Time
Fall Time
trr
IF = 3.0 A, dI/dt = 100 A/µs
Source-Drain Reverse Recovery Time
30
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
8
10
T
= - 55 °C
V
GS
= 4.5 V thru 3.5 V
3 V
C
8
25 °C
125 °C
6
6
2.5 V
2 V
4
4
2
2
1.5 V
3
0
0.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
1
2
4
5
V
GS
- Gate-to-Source Voltage (V)
V
DS
- Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
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Document Number: 71178
S09-2275-Rev. D, 02-Nov-09
Si3900DV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.5
300
250
200
150
100
50
0.4
0.3
C
iss
V
GS
= 2.5 V
0.2
0.1
0.0
V
GS
= 4.5 V
C
oss
C
rss
0
0
1
2
I
3
4
5
6
7
0
4
8
12
16
20
- Drain Current (A)
V
- Drain-to-Source Voltage (V)
D
DS
On-Resistance vs. Drain Current
Capacitance
1.8
1.6
1.4
1.2
1.0
0.8
0.6
4.5
3.6
2.7
1.8
0.9
0.0
V
D
= 10 V
DS
= 2.4 A
V
D
= 4.5 V
GS
= 2.4 A
I
I
- 50 - 25
0
25
50
75
100 125 150
0.0
0.5
1.0
1.5
2.0
2.5
T - Junction Temperature (°C)
J
Q
- Total Gate Charge (nC)
g
Gate Charge
On-Resistance vs. Junction Temperature
10
0.40
0.32
0.24
0.16
0.08
0.00
I
D
= 2.4 A
I
D
= 1 A
T
= 150 °C
J
1
T
= 25 °C
J
0.1
0
1
2
3
4
5
0
0.3
0.6
0.9
1.2
1.5
V
GS
- Gate-to-Source Voltage (V)
V
SD
- Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Document Number: 71178
S09-2275-Rev. D, 02-Nov-09
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3
Si3900DV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.4
8
6
I
D
= 250 µA
0.2
0.0
4
2
0
- 0.2
- 0.4
- 0.6
- 50 - 25
0
25
50
75
100 125 150
0.01
0.1
1
10
30
T
- Temperature (°C)
Time (s)
J
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
2
1
Duty Cycle = 0.5
0.2
Notes:
P
DM
0.1
0.1
t
1
0.05
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 130 °C/W
thJA
(t)
3. TJM - T = P
Z
A
DM thJA
4. Surface Mounted
Single Pulse
0.01
-
-
-
-
1
4
3
2
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71178.
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Document Number: 71178
S09-2275-Rev. D, 02-Nov-09
Package Information
Vishay Siliconix
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
e1
e1
5
5
4
3
6
1
4
E
1
E
E
1
E
1
2
2
3
-B-
-B-
e
e
b
b
M
M
C
0.15
C
B
A
0.15
B A
5-LEAD TSOP
6-LEAD TSOP
4x
1
-A-
D
0.17 Ref
c
R
R
A
2
A
L
2
Gauge Plane
Seating Plane
Seating Plane
L
0.08
C
A
1
-C-
(L )
1
4x
1
MILLIMETERS
INCHES
Dim
A
A1
A2
b
c
D
E
E1
e
Min
Nom
-
Max
Min
0.036
0.0004
0.035
0.012
0.004
0.116
0.106
0.061
Nom
-
Max
0.91
0.01
0.90
0.30
0.10
2.95
2.70
1.55
1.10
0.10
1.00
0.45
0.20
3.10
2.98
1.70
0.043
0.004
0.039
0.018
0.008
0.122
0.117
0.067
-
-
-
0.32
0.15
3.05
2.85
1.65
0.95 BSC
1.90
-
0.038
0.013
0.006
0.120
0.112
0.065
0.0374 BSC
0.075
-
1.80
2.00
0.50
0.071
0.012
0.079
0.020
e1
L
0.32
0.60 Ref
0.25 BSC
-
0.024 Ref
0.010 BSC
-
L1
L2
R
0.10
0
-
0.004
0
-
4
8
4
8
7
Nom
7 Nom
1
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
Document Number: 71200
18-Dec-06
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1
AN823
Vishay Siliconix
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
Ramp-Up Rate
+6_C/Second Maximum
120 Seconds Maximum
70 − 180 Seconds
240 +5/−0_C
0.074
1.875
Temperature @ 155 " 15_C
Temperature Above 180_C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
0.014
0.35
0.122
3.1
0.026
0.65
20 − 40 Seconds
+6_C/Second Maximum
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 2. Solder Reflow Temperature Profile
FIGURE 1. Recommended Copper Spreading Footprint
Document Number: 71743
27-Feb-04
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1
AN823
Vishay Siliconix
10 s (max)
255 − 260_C
1X4_C/s (max)
3-6_C/s (max)
217_C
140 − 170_C
60 s (max)
3_C/s (max)
60-120 s (min)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
THERMAL PERFORMANCE
On-Resistance vs. Junction Temperature
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
1.6
1.4
1.2
1.0
0.8
0.6
V
= 4.5 V
GS
I
D
= 6.1 A
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rq
30_C/W
jf
−50 −25
0
25
50
75
100 125 150
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
T
− Junction Temperature (_C)
J
FIGURE 4. Si3434DV
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
Document Number: 71743
27-Feb-04
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2
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.099
(2.510)
0.039
0.020
0.019
(1.001)
(0.508)
(0.493)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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26
Document Number: 72610
Revision: 21-Jan-08
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Document Number: 91000
Revision: 11-Mar-11
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