SI4004DY-T1-GE3 [VISHAY]
N-Channel 20 V (D-S) MOSFET; N沟道20 V （D -S ）的MOSFET
| 型号： | SI4004DY-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 20 V (D-S) MOSFET |
| 文件： | 总10页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
New Product
Si4004DY
Vishay Siliconix
N-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
ID (A)a, e Qg (Typ.)
Definition
TrenchFET® Power MOSFET
100 % Rg and UIS Tested
0.0138 at VGS = 10 V
0.0192 at VGS = 4.5 V
12
•
•
•
20
10.6 nC
12
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
DC/DC Converters
SO-8
•
D
S
S
S
G
D
D
D
D
1
2
3
4
8
7
6
5
G
Top View
S
Ordering Information: Si4004DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
Limit
20
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
V
VGS
20
12e
12e
11b, c
8.8b, c
70
T
C = 25 °C
C = 70 °C
T
Continuous Drain Current (TJ = 150 °C)
ID
TA = 25 °C
TA = 70 °C
A
IDM
IS
Pulsed Drain Current
T
C = 25 °C
A = 25 °C
4.2
2.1b, c
Continuous Source-Drain Diode Current
T
IAS
Single Pulse Avalanche Current
Avalanche Energy
25
L = 0.1 mH
EAS
mJ
W
31
TC = 25 °C
5.0
TC = 70 °C
3.2
Maximum Power Dissipation
PD
2.5b, c
1.6b, c
- 55 to 150
TA = 25 °C
TA = 70 °C
TJ, Tstg
Operating Junction and Storage Temperature Range
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, d
Symbol
Typical
43
Maximum
Unit
t ≤ 10 s
Steady State
RthJA
RthJF
50
25
°C/W
Maximum Junction-to-Foot (Drain)
19
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under steady state conditions is 92 °C/W.
e. Package limited.
Document Number: 70338
S10-1288-Rev. A, 31-May-10
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1
New Product
Si4004DY
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
VGS = 0 V, ID = 250 µA
ID = 250 µA
Drain-Source Breakdown Voltage
20
V
V
DS Temperature Coefficient
22
mV/°C
VGS(th) Temperature Coefficient
- 5.5
VDS = VGS , ID = 250 µA
Gate-Source Threshold Voltage
Gate-Source Leakage
1.2
30
2.5
100
1
V
IGSS
VDS = 0 V, VGS
=
20 V
nA
VDS = 20 V, VGS = 0 V
VDS = 20 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 10 V
IDSS
ID(on)
RDS(on)
gfs
Zero Gate Voltage Drain Current
On-State Drain Currenta
µA
A
10
VGS = 10 V, ID = 11 A
0.0115 0.0138
0.0160 0.0192
25
Drain-Source On-State Resistancea
Forward Transconductancea
Ω
S
VGS = 4.5 V, ID = 9.3 A
VDS = 10 V, ID = 11 A
Dynamicb
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
1280
440
V
DS = 10 V, VGS = 0 V, f = 1 MHz
pF
195
V
DS = 10 V, VGS = 10 V, ID = 11 A
21.6
10.6
4.2
3.1
3.6
15
12
17
9
33
16
Qg
Total Gate Charge
nC
Qgs
Qgd
Rg
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
VDS = 10 V, VGS = 4.5 V, ID = 11 A
f = 1 MHz
0.7
7.2
25
20
26
18
14
20
35
18
Ω
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
V
DD = 10 V, RL = 1.1 Ω
ID ≅ 8.8 A, VGEN = 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
ns
Turn-On Delay Time
Rise Time
7
10
23
9
V
DD = 10 V, RL = 1.1 Ω
ID ≅ 8.8 A, VGEN = 10 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
ISM
VSD
trr
TC = 25 °C
IS = 8.8 A
4.2
70
A
Pulse Diode Forward Currenta
Body Diode Voltage
0.84
26
1.2
39
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Qrr
ta
15
23
IF = 8.8 A, dI/dt = 100 A/µs, TJ = 25 °C
13
ns
tb
13
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70338
S10-1288-Rev. A, 31-May-10
New Product
Si4004DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
70
10
8
VGS = 10 V thru 5 V
56
VGS = 4 V
42
28
14
0
6
TC = 25 °C
4
TC = 125 °C
TC = - 55 °C
2
VGS = 3 V
0
0
0.5
1.0
1.5
2.0
0
0.7
1.4
2.1
2.8
3.5
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.027
0.022
0.017
0.012
0.007
1600
1200
800
400
0
Ciss
VGS = 4.5 V
Coss
VGS = 10 V
Crss
0
14
28
42
56
70
0
8
16
ID - Drain Current (A)
On-Resistance vs. Drain Current
VDS - Drain-to-Source Voltage (V)
Capacitance
1.5
1.3
1.1
0.9
0.7
10
8
ID = 11 A
ID = 9.3 A
VGS = 4.5 V
ID = 11 A
VGS = 10 V
VDS = 5 V
6
VDS = 10 V
4
VDS = 16 V
2
0
- 50 - 25
0
25
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
50
75
100 125 150
0
5
10
15
20
25
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 70338
S10-1288-Rev. A, 31-May-10
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New Product
Si4004DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
0.04
0.03
0.02
0.01
0
ID = 11 A
10
TJ = 150 °C
TJ = 125 °C
TJ = 25 °C
1
TJ = 25 °C
0.1
0
0.3
0.6
0.9
1.2
1.5
2
4
6
8
10
VSD - Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.3
2.0
1.7
1.4
1.1
30
24
18
12
6
ID = 250 μA
0
- 50 - 25
0
25
50
75
100 125 150
0.01
0.1
1
10
100
1000
TJ - Junction Temperature (°C)
Time (s)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
Limited by RDS(on)
*
100 μs
10
1 ms
10 ms
1
100 ms
1 s
10 s
0.1
DC
TA = 25 °C
Single Pulse
BVDSS Limited
10
0.01
0.1
1
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 70338
S10-1288-Rev. A, 31-May-10
New Product
Si4004DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
18.0
13.5
Package Limited
9.0
4.5
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Current Derating*
2.0
1.6
1.2
0.8
0.4
0
6.0
4.5
3.0
1.5
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Ambient
TC - Case Temperature (°C)
Power Derating, Junction-to-Foot
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 70338
S10-1288-Rev. A, 31-May-10
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New Product
Si4004DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
Notes:
PDM
0.1
0.1
t1
0.05
t2
t1
t2
1. Duty Cycle, D =
0.02
2. Per Unit Base = RthJA = 92 °C/W
(t)
3. TJM - TA = PDMZthJA
Single Pulse
10-2
4. Surface Mounted
0.01
10-4
10-3
10-1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70338.
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Document Number: 70338
S10-1288-Rev. A, 31-May-10
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
2
5
4
E
H
1
3
S
h x 45
D
C
0.25 mm (Gage Plane)
A
All Leads
0.101 mm
q
e
B
A
1
L
0.004"
MILLIMETERS
Max
INCHES
DIM
A
Min
Min
Max
1.35
0.10
0.35
0.19
4.80
3.80
1.75
0.20
0.51
0.25
5.00
4.00
0.053
0.004
0.014
0.0075
0.189
0.150
0.069
0.008
0.020
0.010
0.196
0.157
A1
B
C
D
E
e
1.27 BSC
0.050 BSC
H
h
5.80
0.25
0.50
0°
6.20
0.50
0.93
8°
0.228
0.010
0.020
0°
0.244
0.020
0.037
8°
L
q
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050
1.27
0.088
2.25
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
0.288
7.3
0.050
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
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1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
0.022
0.050
(0.559)
(1.270)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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Document Number: 91000
Revision: 11-Mar-11
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