SI4048DY

更新时间:2024-09-18 10:19:35
品牌:VISHAY
描述:N-Channel 30 V (D-S) MOSFET

SI4048DY 概述

N-Channel 30 V (D-S) MOSFET N沟道30 V (D -S )的MOSFET

SI4048DY 数据手册

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Si4048DY  
Vishay Siliconix  
N-Channel 30 V (D-S) MOSFET  
FEATURES  
PRODUCT SUMMARY  
Halogen-free According to IEC 61249-2-21  
VDS (V)  
RDS(on) (Ω)  
Qg (Typ.)  
I
D (A)a  
19.3  
Definition  
TrenchFET® Power MOSFET  
100 % Rg Tested  
100 % UIS Tested  
0.0085 at VGS = 10 V  
0.0105 at VGS = 4.5 V  
30  
15 nC  
17.3  
Compliant to RoHS Directive 2002/95/EC  
APPLICATIONS  
Notebook DC/DC  
- High Side  
SO-8  
D
S
S
S
G
D
D
D
D
1
2
3
4
8
7
6
5
G
Top View  
S
N-Channel MOSFET  
Ordering Information: Si4048DY-T1-GE3 (Lead (Pb)-free and Halogen-free)  
ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)  
A
Parameter  
Symbol  
Limit  
Unit  
Drain-Source Voltage  
Gate-Source Voltage  
VDS  
VGS  
30  
20  
V
TC = 25 °C  
TC = 70 °C  
TA = 25 °C  
TA = 70 °C  
19.3  
15.3  
12.7b, c  
10.2b, c  
70  
20  
20  
5.1  
2.2b, c  
5.7  
3.6  
2.5b, c  
1.6b, c  
- 55 to 150  
Continuous Drain Current (TJ = 150 °C)  
ID  
A
Pulsed Drain Current (300 µs)  
Avalanche Current  
Avalanche Energy  
IDM  
IAS  
EAS  
L = 0.1 mH  
mJ  
A
T
C = 25 °C  
Continuous Source-Drain Diode Current  
Maximum Power Dissipation  
IS  
TA = 25 °C  
TC = 25 °C  
T
C = 70 °C  
PD  
W
TA = 25 °C  
TA = 70 °C  
TJ, Tstg  
°C  
Operating Junction and Storage Temperature Range  
THERMAL RESISTANCE RATINGS  
Parameter  
Maximum Junction-to-Ambientb, d  
Maximum Junction-to-Foot (Drain)  
Symbol  
RthJA  
RthJF  
Typical  
39  
Maximum  
Unit  
t 10 s  
Steady State  
50  
22  
°C/W  
18  
Notes:  
a. Based on TC = 25 °C.  
b. Surface mounted on 1" x 1" FR4 board.  
c. t = 10 s.  
d. Maximum under steady state conditions is 85 °C/W.  
Document Number: 66816  
S10-2009-Rev. A, 06-Sep-10  
www.vishay.com  
1
Si4048DY  
Vishay Siliconix  
SPECIFICATIONS (T = 25 °C, unless otherwise noted)  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Static  
VDS  
ΔVDS/TJ  
ΔVGS(th)/TJ  
VGS(th)  
VGS = 0 V, ID = 250 µA  
ID = 250 µA  
Drain-Source Breakdown Voltage  
30  
V
V
DS Temperature Coefficient  
33  
mV/°C  
VGS(th) Temperature Coefficient  
- 6.3  
VDS = VGS , ID = 250 µA  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
1
3
V
IGSS  
VDS = 0 V, VGS  
=
20 V  
100  
1
nA  
VDS = 30 V, VGS = 0 V  
DS = 30 V, VGS = 0 V, TJ = 55 °C  
VDS 5 V, VGS = 10 V  
VGS = 10 V, ID = 15 A  
IDSS  
ID(on)  
RDS(on)  
gfs  
Zero Gate Voltage Drain Current  
On-State Drain Currenta  
µA  
A
V
5
30  
0.0070  
0.0085  
78  
0.0085  
0.0105  
Drain-Source On-State Resistancea  
Ω
S
VGS = 4.5 V, ID = 10 A  
Forward Transconductancea  
VDS = 15 V, ID = 15 A  
Dynamicb  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
2060  
335  
132  
34  
V
DS = 15 V, VGS = 0 V, f = 1 MHz  
pF  
V
DS = 15 V, VGS = 10 V, ID = 10 A  
51  
23  
Qg  
Total Gate Charge  
15  
nC  
Qgs  
Qgd  
Rg  
Gate-Source Charge  
6.5  
4.0  
0.65  
19  
VDS = 15 V, VGS = 4.5 V, ID = 10 A  
Gate-Drain Charge  
Gate Resistance  
f = 1 MHz  
0.15  
1.3  
35  
22  
35  
16  
20  
18  
40  
16  
Ω
td(on)  
tr  
td(off)  
tf  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
11  
V
DD = 15 V, RL = 15 Ω  
ID 10 A, VGEN = 4.5 V, Rg = 1 Ω  
Turn-Off Delay Time  
18  
Fall Time  
8
ns  
Turn-On Delay Time  
10  
Rise Time  
9
V
DD = 15 V, RL = 15 Ω  
ID 10 A, VGEN = 10 V, Rg = 1 Ω  
Turn-Off Delay Time  
21  
Fall Time  
8
Drain-Source Body Diode Characteristics  
Continuous Source-Drain Diode Current  
Pulse Diode Forward Current  
Body Diode Voltage  
IS  
ISM  
VSD  
trr  
TC = 25 °C  
5.1  
70  
A
IS = 4.0 A, VGS = 0 V  
0.76  
23  
1.1  
45  
25  
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Reverse Recovery Fall Time  
Reverse Recovery Rise Time  
ns  
nC  
Qrr  
ta  
13  
IF = 5.0 A, dI/dt = 100 A/µs, TJ = 25 °C  
12  
ns  
tb  
11  
Notes:  
a. Pulse test; pulse width 300 µs, duty cycle 2 %.  
b. Guaranteed by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
www.vishay.com  
2
Document Number: 66816  
S10-2009-Rev. A, 06-Sep-10  
Si4048DY  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
70  
56  
42  
28  
14  
0
1.2  
V
= 10 V thru 4 V  
GS  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
T
= 125 °C  
C
T
= 25 °C  
C
T
= - 55 °C  
2
V
= 3 V  
C
GS  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0
1
3
4
5
VDS - Drain-to-Source Voltage (V)  
V
- Gate-to-Source Voltage (V)  
GS  
Output Characteristics  
Transfer Characteristics  
0.011  
0.010  
0.009  
0.008  
0.007  
0.006  
2600  
2080  
1560  
1040  
520  
C
iss  
V
= 4.5 V  
GS  
C
oss  
V
= 10 V  
GS  
C
rss  
0
0
16  
32  
48  
64  
80  
0
5
10  
15  
20  
25  
30  
I
- Drain Current (A)  
V
- Drain-to-Source Voltage (V)  
DS  
D
On-Resistance vs. Drain Current and Gate Voltage  
Capacitance  
2.0  
1.7  
1.4  
1.1  
0.8  
0.5  
10  
I
= 15 A  
D
I
=10 A  
D
8
V
= 10 V  
GS  
V
= 15 V  
DS  
6
V
= 4.5 V  
GS  
V
= 10 V  
DS  
4
V
= 20 V  
DS  
2
0
- 50 - 25  
0
25  
50  
75  
100 125 150  
0
7
14  
21  
28  
35  
T
- Junction Temperature (°C)  
J
Q
- Total Gate Charge (nC)  
g
On-Resistance vs. Junction Temperature  
Gate Charge  
Document Number: 66816  
S10-2009-Rev. A, 06-Sep-10  
www.vishay.com  
3
Si4048DY  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
0.04  
100  
10  
1
I
= 15 A  
D
T
= 150 °C  
J
0.03  
0.02  
0.01  
0.00  
T
= 25 °C  
J
0.1  
0.01  
T
= 125 °C  
J
T
= 25 °C  
8
J
0.001  
0.0  
0.2  
V
0.4  
0.6  
0.8  
1.0  
1.2  
0
1
2
3
4
5
6
7
9
10  
- Source-to-Drain Voltage (V)  
V
- Gate-to-Source Voltage (V)  
SD  
GS  
Source-Drain Diode Forward Voltage  
On-Resistance vs. Gate-to-Source Voltage  
140  
112  
84  
56  
28  
0
0.5  
0.2  
- 0.1  
- 0.4  
- 0.7  
- 1.0  
I
= 5 mA  
D
I
= 250 μA  
D
- 50 -- 25  
0
25  
50  
75  
100 125 150  
0.001  
0.01  
0.1  
1
10  
Time (s)  
T
- Temperature (°C)  
J
Single Pulse Power (Junction-to-Ambient)  
Threshold Voltage  
100  
Limited by R  
*
DS(on)  
10  
1
1 ms  
10 ms  
100 ms  
1 s  
10 s  
0.1  
DC  
T
= 25 °C  
BVDSS  
10  
A
Single Pulse  
0.01  
0.01  
0.1  
1
100  
V
- Drain-to-Source Voltage (V)  
DS  
* V  
> minimum V at which R  
is specified  
GS  
GS  
DS(on)  
Safe Operating Area, Junction-to-Ambient  
www.vishay.com  
4
Document Number: 66816  
S10-2009-Rev. A, 06-Sep-10  
Si4048DY  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
25  
20  
15  
10  
5
0
0
25  
50  
75  
100  
125  
150  
T
- Case Temperature (°C)  
C
Current Derating*  
1.80  
7.0  
5.6  
4.2  
2.8  
1.4  
0.0  
1.44  
1.08  
0.72  
0.36  
0.00  
0
25  
50  
75  
100  
125  
150  
0
25  
50  
T - Ambient Temperature (°C)  
A
75  
100  
125  
150  
T
- Case Temperature (°C)  
C
Power, Junction-to-Foot  
Power, Junction-to-Ambient  
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper  
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package  
limit.  
Document Number: 66816  
S10-2009-Rev. A, 06-Sep-10  
www.vishay.com  
5
Si4048DY  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
1
Duty Cycle = 0.5  
0.2  
Notes:  
0.1  
0.1  
P
DM  
0.05  
t
1
t
2
t
1
1. Duty Cycle, D =  
t
0.02  
2
2. Per Unit Base = R  
= 85 °C/W  
thJA  
(t)  
3. T -- T = P  
Z
JM  
A
DM thJA  
Single Pulse  
0.01  
4. Surface Mounted  
-4  
-3  
-2  
-1  
10  
10  
10  
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
10  
100  
1000  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
-4  
Single Pulse  
0.01  
-3  
-2  
-1  
10  
10  
10  
10  
1
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Foot  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see www.vishay.com/ppg?66816.  
www.vishay.com  
6
Document Number: 66816  
S10-2009-Rev. A, 06-Sep-10  
Package Information  
Vishay Siliconix  
SOIC (NARROW): 8-LEAD  
JEDEC Part Number: MS-012  
8
6
7
2
5
4
E
H
1
3
S
h x 45  
D
C
0.25 mm (Gage Plane)  
A
All Leads  
0.101 mm  
q
e
B
A
1
L
0.004"  
MILLIMETERS  
Max  
INCHES  
DIM  
A
Min  
Min  
Max  
1.35  
0.10  
0.35  
0.19  
4.80  
3.80  
1.75  
0.20  
0.51  
0.25  
5.00  
4.00  
0.053  
0.004  
0.014  
0.0075  
0.189  
0.150  
0.069  
0.008  
0.020  
0.010  
0.196  
0.157  
A1  
B
C
D
E
e
1.27 BSC  
0.050 BSC  
H
h
5.80  
0.25  
0.50  
0°  
6.20  
0.50  
0.93  
8°  
0.228  
0.010  
0.020  
0°  
0.244  
0.020  
0.037  
8°  
L
q
S
0.44  
0.64  
0.018  
0.026  
ECN: C-06527-Rev. I, 11-Sep-06  
DWG: 5498  
Document Number: 71192  
11-Sep-06  
www.vishay.com  
1
VISHAY SILICONIX  
TrenchFET® Power MOSFETs  
Application Note 808  
Mounting LITTLE FOOT®, SO-8 Power MOSFETs  
Wharton McDaniel  
0.288  
7.3  
Surface-mounted LITTLE FOOT power MOSFETs use  
integrated circuit and small-signal packages which have  
0.050  
1.27  
0.088  
2.25  
been been modified to provide the heat transfer capabilities  
required by power devices. Leadframe materials and  
design, molding compounds, and die attach materials have  
been changed, while the footprint of the packages remains  
the same.  
0.088  
2.25  
0.027  
0.69  
0.078  
1.98  
0.2  
5.07  
See Application Note 826, Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Siliconix  
MOSFETs, (http://www.vishay.com/ppg?72286), for the  
basis of the pad design for a LITTLE FOOT SO-8 power  
MOSFET. In converting this recommended minimum pad  
to the pad set for a power MOSFET, designers must make  
two connections: an electrical connection and a thermal  
connection, to draw heat away from the package.  
Figure 2. Dual MOSFET SO-8 Pad Pattern  
With Copper Spreading  
The minimum recommended pad patterns for the  
single-MOSFET SO-8 with copper spreading (Figure 1) and  
dual-MOSFET SO-8 with copper spreading (Figure 2) show  
the starting point for utilizing the board area available for the  
heat-spreading copper. To create this pattern, a plane of  
copper overlies the drain pins. The copper plane connects  
the drain pins electrically, but more importantly provides  
planar copper to draw heat from the drain leads and start the  
process of spreading the heat so it can be dissipated into the  
ambient air. These patterns use all the available area  
underneath the body for this purpose.  
In the case of the SO-8 package, the thermal connections  
are very simple. Pins 5, 6, 7, and 8 are the drain of the  
MOSFET for a single MOSFET package and are connected  
together. In a dual package, pins 5 and 6 are one drain, and  
pins 7 and 8 are the other drain. For a small-signal device or  
integrated circuit, typical connections would be made with  
traces that are 0.020 inches wide. Since the drain pins serve  
the additional function of providing the thermal connection  
to the package, this level of connection is inadequate. The  
total cross section of the copper may be adequate to carry  
the current required for the application, but it presents a  
large thermal impedance. Also, heat spreads in a circular  
fashion from the heat source. In this case the drain pins are  
the heat sources when looking at heat spread on the PC  
board.  
Since surface-mounted packages are small, and reflow  
soldering is the most common way in which these are  
affixed to the PC board, “thermal” connections from the  
planar copper to the pads have not been used. Even if  
additional planar copper area is used, there should be no  
problems in the soldering process. The actual solder  
connections are defined by the solder mask openings. By  
combining the basic footprint with the copper plane on the  
drain pins, the solder mask generation occurs automatically.  
0.288  
7.3  
0.050  
1.27  
0.196  
5.0  
A final item to keep in mind is the width of the power traces.  
The absolute minimum power trace width must be  
determined by the amount of current it has to carry. For  
thermal reasons, this minimum width should be at least  
0.020 inches. The use of wide traces connected to the drain  
plane provides a low impedance path for heat to move away  
from the device.  
0.027  
0.69  
0.078  
1.98  
0.2  
5.07  
Figure 1. Single MOSFET SO-8 Pad  
Pattern With Copper Spreading  
Document Number: 70740  
Revision: 18-Jun-07  
www.vishay.com  
1
Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM PADS FOR SO-8  
0.172  
(4.369)  
0.028  
(0.711)  
0.022  
0.050  
(0.559)  
(1.270)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
www.vishay.com  
22  
Document Number: 72606  
Revision: 21-Jan-08  
Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical  
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular  
product with the properties described in the product specification is suitable for use in a particular application. Parameters  
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All  
operating parameters, including typical parameters, must be validated for each customer application by the customer’s  
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,  
including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree  
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and  
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay  
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to  
obtain written terms and conditions regarding products designed for such applications.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by  
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.  
Document Number: 91000  
Revision: 11-Mar-11  
www.vishay.com  
1

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