SI4738CY-E3 [VISHAY]
Analog Circuit, PDSO16;
| 型号： | SI4738CY-E3 |
| 厂家： | 
VISHAY |
| 描述： | Analog Circuit, PDSO16 光电二极管 |
| 文件： | 总9页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4738CY
New Product
Vishay Siliconix
N-Channel Synchronous MOSFETs With Break-Before-Make
FEATURES
D 0- to 20-V Operation
D Driver Impedance—3
D 20-V MOSFETs
ꢀ
D Under-Voltage Lockout
D Shoot Through Resistant
D Fast Switching Times
D SO-16 Package
D High Side: 0.010
D Low Side: 0.006
ꢀ
ꢁ VDD = 4.5 V
ꢁ VDD = 4.5 V
ꢀ
D Switching Frequency: 250 kHz to 1 MHz
DESCRIPTION
The Si4738CY n-channel synchronous MOSFET with
break-before-make (BBM) is a high speed driver designed to
operate in high frequency dc-dc switch-mode power supplies.
It’s purpose is to simplify the use of n-channel MOSFETs in
high frequency buck regulators. This device is designed to be
used with any single output PWM IC or ASIC to produce a
highly efficient, low cost, synchronous rectifier converter.
The LITTLE FOOT Plust Drivers Si4738DY is packaged in
Vishay-Siliconix’s high-performance SO-16 package.
FUNCTIONAL BLOCK DIAGRAM
BOOT
V
DD
D
1
Q
1
Level Shift
S
1
Undervoltage
Lockout
D
2
V
DD
CLK
Q
2
SYNC EN
S
2
+
-
V
REF
GND
Order Number:
Si4738CY (without tape and reel)
Si4738CY-T1 (with tape and reel)
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
1
Si4738CY
New Product
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (T = 25_C UNLESS OTHERWISE NOTED)
A
Parameter
Symbol
Steady State
Unit
Logic Supply
Logic Inputs
V
7
DD
V
-0.7 to V + 0.3
DD
IN
V
Drain Voltage
Bootstrap Voltage
V
20
D1
V
V
+ 7
S1
BOOT
T
= 25rC
= 70rC
= 25rC
= 70rC
8.9
7.1
A
I
D1
D2
T
A
a
Continuous Drain Current (T = 150C)
A
J
T
A
14.29
11.43
I
T
A
a
Maximum Power Dissipation
P
1.2
W
D
Driver
-65 to 125
-65 to 150
Operating Junction and Storage Temperature Range
T, T
_C
j
stg
MOSFETs
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Steady State
Unit
Drain Voltage
V
0 to 20
D1
Logic Supply
V
4.5 to 5.5
DD
V
Input Logic High Voltage
Input Logic Low Voltage
Bootstrap Capacitor
Ambient Temperature
V
0.6 x V to V
DD
IH
DD
V
-0.3 to 0.3 x V
IL
DD
C
BOOT
100 n to 1 ꢂ
F
T
A
-40 to 85
_C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
a
High-Side Junction-to-Ambient
R
thJA1
R
thJA2
R
thJF1
R
thJF2
85
68
24
16
105
85
a
Low-Side Junction-to-Ambient
Steady State
C/W
b
High-Side Junction-to-Foot (Drain)
30
b
Low-Side Junction-to-Foot (Drain)
20
Notes
a. Surface mounted on 1” x1” FR4 board, 0.062” thick, 2-oz copper double sided.
b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with
the thermal impedance of the PC board pads to ambient (R
= R
+ R ). It can also be used to estimate chip temperature if power dissipation and
thJA
thJF
thPCB-A
the lead temperature of a heat carrying (drain) lead is known.
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
2
Si4738CY
New Product
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
Limits
T
= 25_
A
Min
Typa
Max
Unit
4.5 V < V <5.5 V, 4.5 V < V <20 V
Parameter
Power Supplies
Logic Voltage
Symbol
DD
D1
V
4.5
5.5
500
500
V
DD
I
V
= 4.5 V, V
= 4.5 V
280
220
20
DD(EN)
DD
CLK, SYNC
Logic Current (Static)
ꢂ
A
I
V
= 4.5 V, V
,
= 0 V
DD(DIS)
DD
CLK SYNC
I
I
V
= 5 V, f = 250 kHz
DD clk
DD1(DYN)
DD2(DYN)
Logic Current (Dynamic)
mA
V
= 5 V, f = 1 MHz
70
DD
clk
Logic Input
Logic Input Voltage—High
V
2.7
2.3
HIGH
(V
)
CLK, SYNC
V
= 4.5 V
V
DD
Logic Input Voltage—Low
(V
V
-0.3
2.25
0.8
LOW
)
CLK, SYNC
Protection
Break-Before-Make Reference
Under-Voltage Lockout
V
V
V
= 5.5 V
= 4.5 V
2.4
4
BBM
DD
DD
V
3.75
20
4.25
V
UVLO
Under-Voltage Lockout Hysteresis
V
0.4
H
MOSFETs
Drain-Source Voltage
V
I
D
= 250 ꢂA
V
DS
r
Q1
Q2
Q1
Q2
7
10
6
DS(on)1
DS(on)2
V
= 4.5 V, I = 10 A
D
DD
a
Drain-Source On-State Resistance
mꢀ
T
A
= 25_C
r
3.5
0.7
0.7
V
V
1.1
1.1
SD1
SD2
a
Diode Forward Voltage
I
= 2 A, V = 0 V
V
S
GS
Dynamicb
Driver CLK to S1/D2 Off Delay
Driver CLK to S1/D2 Fall Time
Driver CLK to S1/D2 On Delay
Driver CLK to S1/D2 Rise Time
Source-Drain Reverse Recovery
t
43.6
5.8
60
10
d(off)
t
f
f
IN
= 1 MHz, I = 10 A
D
s
V
= 12 V, V
= 1.6 V
OUT
t
81.5
17.5
150
40
d(on)
ns
t
r
t
rr
I
2.7 A, di/dt = 100 A/ꢂs
50
80
F
Time—Q
2
Notes
a. Pulse test: pulse width v300 ms, duty cycle v2%.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
3
Si4738CY
New Product
Vishay Siliconix
TIMING DIAGRAMS
CLK
50%
50%
CLK
t
f
t
r
S /D
1
2
90%
90%
50%
50%
10%
10%
S /D
1
2
t
t
d(on)
d(off)
SWITCHING TEST SET−UP
20 V
C
V
C
BOOT
DD
5 V
D
1
1
C
C
G
G
BOOT
1
L
S
S /D
1
MOSFET Drive
Circuitry with
Break-Before-Make
SYNC
EN
2
v
out
+
D
2
2
CLK
C
L
R
L
Signal Input
2
GND
S
GND
GND
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
4
Si4738CY
New Product
Vishay Siliconix
PIN CONFIGURATION
TRUTH TABLE
Q
2
Sync EN
CLK
Q1
H
H
ON
OFF
ON
SO-16
H
L
L
L
H
L
OFF
ON
D1
D1
S
S
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
1
OFF
OFF
OFF
GND
CLK
C
BOOT
V
DD
SYNC EN
S2
D2
PIN DESCRIPTION
D2
D2
D2
Pin
Symbol
Description
S2
1, 2
D
1
High-Side MOSFET Drain
Signal Ground
S2
3
GND
CLK
4
5
Input Logic Signal
Top View
SYNC EN Synchronous Enable
6, 7, 8
9, 10, 11, 12
S
Low-Side MOSFET Source
Low-Side MOSFET Drain
2
D
2
Logic Supply; Decoupling to GND (with a Dap is strongly
recommended)
13
V
DD
14
C
Bootstrap Capacitor for Upper MOSFET
High-Side MOSFET Source
BOOT
15, 16
S
1
APPLICATION CIRCUIT
0 V to 30 V
C
BOOT
V
DD
5 V
D
1
Power Up Sequence:
C
Q
1
3
4
Ensure V is within spec before allowing.
DD
BOOT
L
SYNC EN
CLK to be set high.
S
D
1
MOSFET Drive
Circuitry with
Break-Before-Make
V
OUT
Power Down Sequence:
DC-DC
2
Controller
1
2
Ensure CLK is low before turning.
Turn V off.
CLK
+
C
L
DD
Q
2
GND
S
2
GND
GND
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
5
Si4738CY
New Product
Vishay Siliconix
DEVICE OPERATION
The Vishay Siliconix MOSFET plus driver product is optimized
for dc-dc conversion in all aspects—driver design through
MOSFET optimization. The integrated packaged allows the
PCB designer to ignore the MOSFET driving current loops and
focus on one board layout aspect—output current loop. It also
allows for simplicity when adding additional phases to a
system.
The MOSFETs are designed to meet a specific set of
conditions to provide the best performance possible. These
requirements are as follows.
1. The size of the MOSFET is selected to provide a good
compromise between power dissipation and size.
2. The high-side MOSFET is designed to minimize the
rDS(on)-Qg figure-of-merit and to have a low Rg for short
switching times.
3. The low-side MOSFET is designed to have the optimum
rDS(on), low Rg for short switching times, and low Qgd/Qgs
ratio to eliminate shoot-through conditions.
The MOSFET driver is designed to eliminate any
shoot-through currents in the output MOSFET stage by
integrating a break-before-make circuit topology. When the
low-side MOSFET is to be turned on, there is an internal
reference voltage, VBBM, that the S1 node needs to be below
before the low-side MOSFET is turned on. When the high-side
MOSFET is to be turned on, there is an optimized delay time
(based on the MOSFET pair used) that will ensure that the
low-side is turned off, and minimize the body diode conduction.
In addition, the low impedance MOSFET drivers are optimized
with the MOSFET gate impedance to help ensure an “off” state
gate voltage during any shoot-through conditions when the
high-side MOSFET is turned on.
Switch Timing
The Si4738CY has a built-in delay time that is optimized for the
MOSFET pair. When the CLK signal goes low, the high-side
driver will turn off, and the output will start to ramp down, tf.
After a total delay, td(off) , the low-side driver turns on to provide
the synchronous rectification.
When the CLK goes high, the low-side driver turns off; as the
body diode starts to conduct, the high-side MOSFET turns on
after a total delay, td(on). The output then ramps up, tr.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Representative Safe Operating Curve
Typical Performance
The following guidelines are meant to allow the designer the
quickest and simplest method to working with the
Vishay Siliconix MOSFET plus driver products.
2. The following chart shows experimental results based on
a specific set of operating conditions.
1. The Si4738CY has a limited maximum output current
capability, depending on the frequency, duty cycle and
ambient temperature. The following graph shows the
limitation
Power Dissipation vs. Frequency
I
vs. Operating Frequency
OUT
7
16
12
8
V
V
V
= 12 V
IN
OUT
= 1.6 V
= 5 V
6
5
4
3
2
1
0
T
A
= 25_C
DD
I
= 12 A
OUT
T
= 80_C
A
I
= 8 A
OUT
4
V
V
= 12 V
OUT
IN
= 1.6 V
0
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
Operating Frequency (kHz)
Operating Frequency (kHz)
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
6
Si4738CY
New Product
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Power Dissipation vs. I
When all of these factors are put together, a set of efficiency
curves are developed as shown. This experimental result is
based on a spreading copper area on the board of one and a
half square inches.
OUT
8
6
4
2
0
V
V
V
= 12 V
= 1.6 V
= 5 V
IN
OUT
DD
Efficiency Comparison
95
V
= 12 V
IN
Inductor of 1.0 ꢂH, 5050EZ
91
87
83
79
75
700 kHz
300 kHz
300 kHz
500 kHz
0
4
8
12
16
20
700 kHz
I
(A)
OUT
1000 kHz
3. The dissipation of the heat generated by the MOSFET plus
driver product is highly dependent on the board thermal
impedance and the RthJF of the SO-16 package.
4
8
12
16
20
I
O
(A)
BOARD DESIGN GUIDELINES
The performance characteristics shown above was done
using a board that follows a suggested layout of the device and
surrounding components. The basic design rules are as
follows.
2. Place the output inductor close to the S1 and D2 pads.
Using a large copper area around these pads help
improve the thermal performance. Adding thermal vias
to help dissipate the heat also improves performance.
3. Use a large copper area for the D1 and S2 pads. Again,
using thermal vias in this area will help the thermal
performance.
1. Minimize the distance of the VDD capacitor to the VDD
pins and ground.
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
7
Si4738CY
New Product
Vishay Siliconix
BOARD LAYOUT
Top Layer Overlay
Top Layer
Internal Plane 1
Internal Plane 2
Bottom Layer
Bottom Layer Overlay
Document Number: 71927
S-03778—Rev. D, 21-Apr-03
www.vishay.com
8
Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000
Revision: 08-Apr-05
www.vishay.com
1
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