SI4778DY-T1-GE3 [VISHAY]
N-Channel 25-V (D-S) MOSFET; N通道25 -V （D -S ）的MOSFET
| 型号： | SI4778DY-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 25-V (D-S) MOSFET |
| 文件： | 总10页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4778DY
Vishay Siliconix
N-Channel 25-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
Qg (Typ.)
I
D (A)
Available
8a
8a
•
•
TrenchFET® Power MOSFET
100 % Rg and UIS Tested
0.023 at VGS = 10 V
0.028 at VGS = 4.5 V
25
5.5 nC
APPLICATIONS
•
•
DC/DC Converter
Gaming
• Notebook System Power
SO-8
D
1
2
3
4
8
7
6
5
S
S
D
D
D
D
S
G
G
Top View
S
N-Channel MOSFET
Ordering Information:
Si4778DY-T1-E3 (Lead (Pb)-free)
Si4778DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Drain-Source Voltage
Gate-Source Voltage
Symbol
VDS
VGS
Limit
25
16
8a
8a
8a, b, c
6.4b, c
30
4.2
2b, c
5
1.25
5
3.2
2.4b, c
1.5b, c
Unit
V
T
T
C = 25 °C
C = 70 °C
Continuous Drain Current (TJ = 150 °C)
ID
TA = 25 °C
TA = 70 °C
A
IDM
IS
Pulsed Drain Current
TC = 25 °C
TA = 25 °C
Continuous Source-Drain Diode Current
IAS
EAS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L = 0.1 mH
mJ
W
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
PD
Maximum Power Dissipation
TJ, Tstg
°C
Operating Junction and Storage Temperature Range
- 55 to 150
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambientb, d
Maximum Junction-to-Foot (Drain)
t ≤ 10 s
Steady State
RthJA
RthJF
42
53
°C/W
19
25
Notes:
a. Package Limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under Steady State conditions is 85 °C/W.
Document Number: 69817
S09-0394-Rev. B, 09-Mar-09
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1
Si4778DY
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
VGS = 0 V, ID = 250 µA
ID = 250 µA
Drain-Source Breakdown Voltage
25
V
V
DS Temperature Coefficient
25
mV/°C
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
- 4.7
VDS = VGS , ID = 250 µA
1.0
20
2.2
100
1
V
IGSS
VDS = 0 V, VGS
=
16 V
nA
VDS = 25 V, VGS = 0 V
VDS = 25 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 10 V
IDSS
ID(on)
RDS(on)
gfs
Zero Gate Voltage Drain Current
µA
A
10
On-State Drain Currenta
VGS = 10 V, ID = 7 A
0.019
0.023
23
0.023
0.028
Drain-Source On-State Resistancea
Forward Transconductancea
Ω
S
VGS = 4.5 V, ID = 6.3 A
VDS = 10 V, ID = 7 A
Dynamicb
Ciss
Coss
Crss
Input Capacitance
680
120
55
12
5.5
2
V
DS = 13 V, VGS = 0 V, f = 1 MHz
Output Capacitance
pF
Reverse Transfer Capacitance
VDS = 13 V, VGS = 10 V, ID = 7 A
VDS = 13 V, VGS = 4.5 V, ID = 7 A
f = 1 MHz
18
Qg
Total Gate Charge
8.5
nC
Qgs
Qgd
Rg
Gate-Source Charge
Gate-Drain Charge
1.5
2.5
15
50
20
10
10
12
15
10
Gate Resistance
3.8
25
75
30
15
15
20
25
15
Ω
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
VDD = 13 V, RL = 2.3 Ω
ID ≅ 5.6 A, VGEN = 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
ns
Turn-On Delay Time
Rise Time
VDD = 13 V, RL = 2.3 Ω
ID ≅ 5.6 A, VGEN = 10 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
IS
ISM
VSD
trr
TC = 25 °C
2.3
30
A
IS = 5.6 A, VGS = 0 V
0.8
15
8
1.2
30
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Qrr
ta
16
IF = 5.6 A, dI/dt = 100 A/µs, TJ = 25 °C
8.5
6.5
ns
tb
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 69817
S09-0394-Rev. B, 09-Mar-09
Si4778DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
30
10
8
V
GS
= 10 thru 4 V
24
18
12
6
T
= - 55 °C
C
6
V
= 3 V
GS
4
T
= 25 °C
C
2
T
= 125 °C
1.5
C
0
0
0.0
0.4
0.8
1.2
1.6
2.0
0.0
0.5
1.0
2.0
2.5
3.0
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.035
0.030
0.025
0.020
0.015
900
750
600
450
300
150
0
C
iss
V
GS
= 10 V
V
GS
= 4.5 V
C
oss
C
rss
0
6
12
18
24
30
0
5
10
15
20
25
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
Capacitance
On-Resistance vs. Drain Current
10
8
1.6
1.4
1.2
1.0
0.8
0.6
I
D
= 7 A
I
D
= 7 A
V
GS
= 10 V, 4.5 V
V
DS
= 13 V
6
V
DS
= 24 V
4
2
0
0
3
6
9
12
- 50 - 25
0
25
50
75
100 125 150
Q
- Total Gate Charge (nC)
T
- Junction Temperature (°C)
g
J
On-Resistance vs. Junction Temperature
Gate Charge
Document Number: 69817
S09-0394-Rev. B, 09-Mar-09
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Si4778DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.08
0.06
0.04
0.02
0.00
100
I
D
= 7 A
T
= 150 °C
J
10
T
= 25 °C
T
= 125 °C
J
A
T
= 25 °C
A
1
0.0
0
2
4
6
8
10
0.2
0.4
0.6
0.8
1.0
1.2
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.0
1.8
1.6
1.4
1.2
1.0
30
25
20
15
10
5
I
D
= 250 µA
0
- 50 - 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
100
1000
T
- Temperature (°C)
Time (s)
J
Single Pulse Power
Threshold Voltage
100
Limited by R
*
DS(on)
10
1
100 µs
1 ms
10 ms
100 ms
1 s
10 s
0.1
DC
BVDSS
Limited
T
= 25 °C
A
Single Pulse
0.01
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V > minimum V at which R is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Ambient
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Document Number: 69817
S09-0394-Rev. B, 09-Mar-09
Si4778DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
15
5
4
3
2
1
0
12
9
6
3
0
Package Limited
0
25
50
75
100
125
150
25
50
75
100
125
150
T
C
- Case Temperature (°C)
T
C
- Case Temperature (°C)
Power Derating
Current Derating*
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 69817
S09-0394-Rev. B, 09-Mar-09
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Si4778DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
P
DM
t
0.05
0.02
1
t
2
t
t
1
2
1. Duty Cycle, D =
2. Per Unit Base = R
= 70 °C/W
thJA
(t)
3. T - T = P
Z
JM
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
100
1000
10
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?69817.
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6
Document Number: 69817
S09-0394-Rev. B, 09-Mar-09
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
2
5
4
E
H
1
3
S
h x 45
D
C
0.25 mm (Gage Plane)
A
All Leads
0.101 mm
q
e
B
A
1
L
0.004"
MILLIMETERS
Max
INCHES
DIM
A
Min
Min
Max
1.35
0.10
0.35
0.19
4.80
3.80
1.75
0.20
0.51
0.25
5.00
4.00
0.053
0.004
0.014
0.0075
0.189
0.150
0.069
0.008
0.020
0.010
0.196
0.157
A1
B
C
D
E
e
1.27 BSC
0.050 BSC
H
h
5.80
0.25
0.50
0°
6.20
0.50
0.93
8°
0.228
0.010
0.020
0°
0.244
0.020
0.037
8°
L
q
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050
1.27
0.088
2.25
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
0.288
7.3
0.050
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
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1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
0.022
0.050
(0.559)
(1.270)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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Disclaimer
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Document Number: 91000
Revision: 11-Mar-11
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