SI5401DC-T1-GE3 [VISHAY]
Small Signal Field-Effect Transistor, 5.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, 1206-8, CHIPFET-8;
| 型号： | SI5401DC-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Small Signal Field-Effect Transistor, 5.2A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, 1206-8, CHIPFET-8 开关 光电二极管 晶体管 |
| 文件： | 总10页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5401DC
Vishay Siliconix
P-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
ID (A)
- 7.1
- 6.4
- 5.5
Qg (Typ.)
Available
0.032 at VGS = - 4.5 V
0.040 at VGS = - 2.5 V
0.053 at VGS = - 1.8 V
•
•
•
•
TrenchFET® Power MOSFET
Ultra-Low On-Resistance
Thermally Enhanced ChipFET® Package
40 % Smaller Footprint than TSOP-6
- 20
16.5
APPLICATIONS
1206-8 ChipFET®
•
Load Switch, PA Switch, and Battery Switch for Portable
Devices
1
D
S
D
D
D
D
Marking Code
D
G
G
BO XXX
S
Lot Traceability
and Date Code
Part # Code
Bottom View
Ordering Information:
D
Si5401DC-T1-E3 (Lead (Pb)-free)
Si5401DC-T1-GE3 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
5 s
Steady State
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
- 20
8
V
VGS
TA = 25 °C
TA = 85 °C
- 7.1
- 5.1
- 5.2
- 3.7
Continuous Drain Current (TJ = 150 °C)a
ID
A
IDM
IS
Pulsed Drain Current
- 20
Continuous Source Currenta
- 2.1
2.5
- 1.1
1.3
TA = 25 °C
TA = 85 °C
Maximum Power Dissipationa
PD
W
1.3
0.7
TJ, Tstg
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)b, c
- 55 to 150
260
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
40
Maximum
Unit
t ≤ 5 s
50
95
20
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
RthJA
Steady State
Steady State
80
°C/W
RthJF
15
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 73225
S-83054-Rev. B, 29-Dec-08
www.vishay.com
1
Si5401DC
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
IGSS
VDS = VGS, ID = - 250 µA
Gate Threshold Voltage
- 0.40
- 1.0
100
- 1
V
VDS = 0 V, VGS
=
8 V
Gate-Body Leakage
nA
VDS = - 20 V, VGS = 0 V
VDS = - 20 V, VGS = 0 V, TJ = 85 °C
VDS ≤ - 5 V, VGS = - 4.5 V
IDSS
Zero Gate Voltage Drain Current
µA
A
- 5
On-State Drain Currenta
ID(on)
- 20
VGS = - 4.5 V, ID = - 5.2 A
0.026
0.033
0.044
20
0.032
0.040
0.053
Drain-Source On-State Resistancea
RDS(on)
V
V
GS = - 2.5 V, ID = - 4.6 A
GS = - 1.8 V, ID = - 1.9 A
Ω
Forward Transconductancea
Diode Forward Voltagea
gfs
VDS = - 10 V, ID = - 5.2 A
IS = - 1.1 A, VGS = 0 V
S
V
VSD
- 0.8
- 1.2
25
Dynamicb
Qg
Qgs
Qgd
Rg
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
16.5
1.7
3.5
9
V
DS = - 10 V, VGS = - 4.5 V, ID = - 5.2 A
f = 1 MHz
nC
Ω
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
10
15
40
25
V
DD = - 10 V, RL = 10 Ω
ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω
Turn-Off Delay Time
Fall Time
115
70
175
105
60
ns
trr
Source-Drain Reverse Recovery Time
Reverse Recovery Charge
30
IF = - 1.1 A, dI/dt = 100 A/µs
Qrr
140
nC
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
16
12
8
20
16
12
8
T
= - 55 °C
25 °C
C
V
GS
= 5 thru 2 V
125 °C
1.5 V
4
4
1 V
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Transfer Characteristics
Output Characteristics
www.vishay.com
2
Document Number: 73225
S-83054-Rev. B, 29-Dec-08
Si5401DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2000
1800
1600
1400
1200
1000
800
0.10
0.08
0.06
C
iss
V
GS
= 1.8 V
V
= 2.5 V
GS
0.04
0.02
0.00
600
C
oss
400
V
= 4.5 V
GS
200
C
rss
0
0
4
8
12
16
20
0
4
8
12
16
20
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
5
4
3
2
1
0
1.6
1.4
1.2
1.0
0.8
0.6
V
D
= 10 V
V
D
= 4.5 V, 2.5 V, 1.8 V
DS
= 5.2 A
GS
I = 5.2 A
I
0
4
8
12
16
20
- 50 - 25
0
25
50
75
100 125 150
Q
-Total Gate Charge (nC)
T - Junction Temperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
0.12
0.10
0.08
0.06
0.04
0.02
0.00
20
10
I
= 5.2 A
D
T
= 150 °C
J
T
= 125 °C
J
T
= 125 °C
J
T
= 25 °C
J
T
= 25 °C
4
J
1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
1
2
3
5
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Document Number: 73225
S-83054-Rev. B, 29-Dec-08
www.vishay.com
3
Si5401DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.4
50
40
30
20
10
0
0.3
I
D
= 250 µA
0.2
0.1
0.0
- 0.1
- 0.2
-3
-2
-1
- 50 - 25
0
25
50
75
100 125 150
10
10
10
1
10
100
600
T
- Temperature (°C)
Time (s)
J
Threshold Voltage
Single Pulse Power
100
I
Limited
DM
Limited by R
*
DS(on)
10
P(t) = 0.001
I
D(on)
Limited
1
P(t) = 0.01
P(t) = 0.1
P(t) = 1
T
= 25 °C
P(t) = 10
C
0.1
Single Pulse
DC
BVDSS Limited
0.01
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V > minimum V
GS
at which R
is specified
DS(on)
GS
Safe Operating Area
2
1
Duty Cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
0.05
t
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 80 °C/W
thJA
(t)
3. T
- T = P Z
A DM thJA
JM
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
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4
Document Number: 73225
S-83054-Rev. B, 29-Dec-08
Si5401DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73225.
Document Number: 73225
S-83054-Rev. B, 29-Dec-08
www.vishay.com
5
Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
4
E
1
E
x
S
e
b
c
Backside View
2X 0.10/0.13 R
A
DETAIL X
NOTES:
1. All dimensions are in millimeaters.
2. Mold gate burrs shall not exceed 0.13 mm per side.
3. Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4. Dimensions exclusive of mold gate burrs.
5. No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
INCHES
Min Nom Max
Dim
A
b
c
c1
D
E
E1
e
Min
1.00
0.25
0.1
Nom
−
Max
1.10
0.039
0.010
0.004
0
−
0.012
0.006
−
0.043
0.014
0.008
0.0015
0.122
0.078
0.067
0.30
0.35
0.15
0.20
0
−
0.038
3.10
2.95
1.825
1.55
3.05
0.116
0.072
0.061
0.120
0.075
0.065
0.0256 BSC
−
1.90
1.975
1.70
1.65
0.65 BSC
−
0.28
0.42
0.011
0.017
L
0.55 BSC
5_Nom
0.022 BSC
5_Nom
S
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
www.vishay.com
1
AN811
Vishay Siliconix
Single-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
80 mil
68 mil
This technical note discusses the single-channel ChipFET
1206-8 pin-out, package outline, pad patterns, evaluation
board layout, and thermal performance.
28 mil
26 mil
PIN-OUT
FIGURE 2. Footprint With Copper Spreading
Figure 1 shows the pin-out description and Pin 1 identification
for the single-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thermal performance.
The legs of the device are very short, again helping to reduce
the thermal path to the external heatsink/pcb and allowing a
larger die to be fitted in the device if necessary.
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins
1,2,3,6.7,8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0054 sq. in. or
3.51 sq. mm). This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the single device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the
Vishay Siliconix Evaluation Board described in the next
section (Figure 3).
Single 1206-8 ChipFET
1
D
D
D
D
D
D
G
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE SINGLE 1206-8
S
Bottom View
The ChipFET 1206-08 evaluation board measures 0.6 in by
0.5 in. Its copper pad pattern consists of an increased pad area
around the six drain leads on the top-side—approximately
0.0482 sq. in. 31.1 sq. mm—and vias added through to the
underside of the board, again with a maximized copper pad
area of approximately the board-size dimensions. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71126
12-Dec-03
www.vishay.com
1
AN811
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 45_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 33_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
pcb.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 15_C/W typical, 20_C/W
maximum for the single device. The “foot” is the drain lead of
the device as it connects with the body. This is identical to the
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
160
120
Single EVB
Min. Footprint
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
80
40
The typical RQja for the single-channel 1206-8 ChipFET is
80_C/W steady state, compared with 68_C/W for the SO-8.
Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W
for the SO-8.
1” Square PCB
Testing
0
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
thermal performance on two different board sizes and three
different pad patterns. The results display the thermal
performance out to steady state and produce a graphic
account of how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the single 1206-8
ChipFET are :
-5
-4
-3
-2
-1
10
10
10
10
10
Time (Secs)
1
10
100
1000
FIGURE 4. Single 1206−8 ChipFET
SUMMARY
The thermal results for the single-channel 1206-8 ChipFET
package display similar power dissipation performance to the
SO-8 with a footprint reduction of 80%. Careful design of the
package has allowed for this performance to be achieved. The
short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
1) Minimum recommended pad pattern (see 156_C/W
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
2) The evaluation board with the pad pattern 111_C/W
ASSOCIATED DOCUMENT
described on Figure 3.
3) Industry standard 1” square pcb with
maximum copper both sides.
78_C/W
1206-8 ChipFET Dual Thermal performance, AN812
(http://www.vishay.com/doc?71127).
Document Number: 71126
12-Dec-03
www.vishay.com
2
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
(2.357)
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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2
Document Number: 72593
Revision: 21-Jan-08
Legal Disclaimer Notice
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
Document Number: 91000
1
相关型号：
SI5402DC-E3
TRANSISTOR 4900 mA, 30 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, 1206-8, CHIPFET-8, FET General Purpose Small Signal
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SI5402DC-T1-GE3
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