SI5511DC-T1-GE3 [VISHAY]
Small Signal Field-Effect Transistor, 3.9A I(D), 30V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, 1206-8, CHIPFET-8;
| 型号： | SI5511DC-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Small Signal Field-Effect Transistor, 3.9A I(D), 30V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, 1206-8, CHIPFET-8 开关 光电二极管 晶体管 |
| 文件： | 总16页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5511DC
Vishay Siliconix
N- and P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
ID (A) Qg (Typ.)
Definition
4a,g
4a,g
0.055 at VGS = 4.5 V
0.090 at VGS = 2.5 V
0.150 at VGS = - 4.5 V
0.256 at VGS = - 2.5 V
•
•
TrenchFET® Power MOSFETs
Compliant to RoHS Directive 2002/95/EC
N-Channel
P-Channel
30
4.2 nC
- 3.6a
- 2.7a
- 30
2.85 nC
APPLICATIONS
•
Buck-Boost
1206-8 ChipFET®
- DSC
- Portable Devices
1
D
1
S
2
S
1
D
1
G
1
Marking Code
D
1
S
2
G
2
EE
XXX
G
1
D
2
G
2
Lot Traceability
and Date Code
D
2
Part # Code
S
1
D
2
Bottom View
Ordering Information: Si5511DC-T1-E3 (Lead (Pb)-free)
N-Channel MOSFET
P-Channel MOSFET
Si5511DC-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
N-Channel
P-Channel
Unit
VDS
30
- 30
Drain-Source Voltage
Gate-Source Voltage
V
VGS
12
4a, g
4a, g
4a, g
3.9a
15
- 3.6a
- 2.8a
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
ID
Continuous Drain Current (TJ = 150 °C)
- 2.3b, c
- 1.8b, c
- 10
A
IDM
IS
Pulsed Drain Current
TC = 25 °C
2.6
1.7b, c
3.1
- 2.6
- 1.7b, c
2.6
Source Drain Current Diode Current
TA = 25 °C
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
2.0
1.7
PD
Maximum Power Dissipation
W
2.1b, c
1.33b, c
1.3b, c
0.84b, c
TJ, Tstg
- 55 to 150
260
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
°C
THERMAL RESISTANCE RATINGS
N-Channel
Typ. Max.
P-Channel
Typ. Max.
Parameter
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Foot (Drain)
Symbol
RthJA
Unit
t ≤ 5 s
50
30
60
40
77
33
95
40
°C/W
RthJF
Steady State
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequade bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 110 °C/W for N-Channel and 130 °C/W for P-Channel.
g. Package limited.
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
1
Si5511DC
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Static
Symbol
Test Conditions
Min.
Typ.a Max.
Unit
VGS = 0 V, ID = 250 µA
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
30
VDS
Drain-Source Breakdown Voltage
V
VGS = 0 V, ID = - 250 µA
- 30
ID = 250 µA
24.2
- 23.1
3.6
V
DS Temperature Coefficient
ΔVDS/TJ
ΔVGS(th)/TJ
ID = - 250 µA
mV/°C
ID = 250 µA
VGS(th) Temperature Coefficient
I
D = - 250 µA
VDS = VGS, ID = 250 µA
DS = VGS, ID = - 250 µA
2.3
0.7
2
VGS(th)
Gate Threshold Voltage
Gate-Body Leakage
V
V
P-Ch
N-Ch
P-Ch
N-Ch
- 0.7
- 2
100
- 100
1
IGSS
VDS = 0 V, VGS
=
12 V
nA
VDS = 30 V, VGS = 0 V
V
DS = - 30 V, VGS = 0 V
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
- 1
10
IDSS
ID(on)
RDS(on)
gfs
Zero Gate Voltage Drain Current
On-State Drain Currentb
µA
A
V
DS = 30 V, VGS = 0 V, TJ = 55 °C
V
DS = - 30 V, VGS = 0 V, TJ = 55 °C
VDS ≤ 5 V, VGS = 4.5 V
- 10
15
VDS ≤ - 5 V, VGS = - 4.5 V
VGS = 4.5 V, ID = 4.8 A
- 10
0.045 0.055
0.125 0.150
0.075 0.090
0.213 0.256
10.8
V
GS = - 4.5 V, ID = - 2.3 A
GS = 2.5 V, ID = 3.8 A
GS = - 2.5 V, ID = 1.8 A
VDS = 15 V, ID = 4.8 A
Drain-Source On-State Resistanceb
Ω
S
V
V
Forward Transconductanceb
V
DS = - 15 V, ID = - 2.3 A
6.56
Dynamica
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
435
260
65
Ciss
Coss
Crss
Input Capacitance
N-Channel
DS = 15 V, VGS = 0 V, f = 1 MHz
V
Output Capacitance
pF
55
P-Channel
DS = - 15 V, VGS = 0 V, f = 1 MHz
30
V
Reverse Transfer Capacitance
42
VDS = 15 V, VGS = 5 V, ID = 4.8 A
DS = - 15 V, VGS = - 5 V, ID = - 3.2 A
4.7
7.1
V
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
4.1
4.2
3.8
1.1
0.6
0.9
1.85
2.7
7.7
6.2
6.3
4.6
Qg
Total Gate Charge
N-Channel
DS = 15 V, VGS = 4.5 V, ID = 4.8 A
nC
V
Qgs
Qgd
Rg
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
P-Channel
V
DS = - 15 V, VGS = - 4.5 V, ID = - 3.2 A
f = 1 MHz
Ω
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Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
Si5511DC
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Dynamica
Symbol
Test Conditions
Min.
Typ.a Max.
Unit
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
9
12
23
68
117
72
50
42
98
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
N-Channel
DD = 15 V, RL = 3.95 Ω
ID ≅ 3.8 A, VGEN = 4.5 V, Rg = 1 Ω
15
45
78
48
33
28
65
V
ns
P-Channel
DD = - 15 V, RL = 18.1 Ω
ID ≅ - 1.86 A, VGEN = - 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
V
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
2.6
- 2.6
15
IS
TC = 25 °C
A
V
Pulse Diode Forward Currenta
Body Diode Voltage
ISM
- 10
1.2
IS = 2.4 A, VGS = 0 V
0.8
VSD
I
S = - 1.5 A, VGS = 0 V
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
- 0.8
11.6
19.8
6.1
- 1.2
18
trr
Qrr
ta
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
ns
30
N-Channel
IF = 2.4 A, dI/dt = 100 A/µs, TJ = 25 °C
9.2
27
nC
17.5
8.4
P-Channel
IF = - 1.5 A, dI/dt = - 100 A/µs, TJ = 25 °C
17.2
3.2
ns
tb
Reverse Recovery Rise Time
2.6
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
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3
Si5511DC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
15
12
9
5
4
3
2
1
0
V
GS
= 5 V thru 3 V
V
= 2.5 V
GS
6
T
= 125 °C
C
V
V
= 2 V
GS
3
T
= 25 °C
1.0
C
= 1.5 V
GS
T
= - 55 °C
C
0
0.0
0.6
1.2
1.8
2.4
3.0
0.0
0.5
1.5
2.0
2.5
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.20
0.16
0.12
0.08
0.04
0.00
600
500
400
300
200
100
0
C
iss
V
GS
= 2.5 V
V
GS
= 4.5 V
C
oss
C
rss
0
3
6
9
12
15
0
5
10
15
20
25
30
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
5
1.6
1.4
1.2
1.0
0.8
0.6
V
D
= 4.5 V
GS
= 4.8 A
I
D
= 4.8 A
I
4
3
2
1
0
V
DS
= 15 V
V
D
= 2.5 V
GS
= 3.7 A
V
GS
= 24 V
I
0
1
2
3
4
5
6
- 50 - 25
0
25
50
75
100 125 150
Q
- Total Gate Charge (nC)
T - Junction Temperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
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Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
Si5511DC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.12
0.10
0.08
0.06
0.04
0.02
20
10
I
= 4.8 A
D
T
A
= 150 °C
1
0.1
T
A
= 25 °C
T
A
= 125 °C
T
A
= 25 °C
0.01
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1
2
3
4
5
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
1.5
1.3
1.1
0.9
0.7
0.5
50
40
I
D
= 250 µA
30
20
10
0
-4
-3
-2
-1
- 50 - 25
0
25
50
75
100 125 150
10
10
10
10
Time (s)
Single Pulse Power
1
10
100 600
T
- Temperature (°C)
J
Threshold Voltage
100
Limited by R
*
DS(on)
10
1
1 ms
10 ms
100 ms
1 s
10 s
0.1
DC
BVDSS Limited
0.01
T
A
= 25 °C
Single Pulse
0.001
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V
GS
minimum V at which R
is specified
DS(on)
GS
Safe Operating Area, Junction-to-Ambient
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
5
Si5511DC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
4
3
2
1
0
8
6
4
2
0
Package Limited
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
- Case Temperature (°C)
C
T
- Case Temperature (°C)
C
Power Derating
Current Derating*
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
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Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
Si5511DC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
0.05
t
1
t
0.02
2
t
t
1
2
1. Duty Cycle, D =
2. Per Unit Base = R
= 90 °C/W
thJA
(t)
3. T - T = P
JM
Z
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
7
Si5511DC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
8
5
4
3
2
1
0
V
GS
= 5 V thru 3.5 V
V
GS
= 3 V
6
V
GS
= 2.5 V
4
V
GS
= 2 V
T
A
= 125 °C
2
T
A
= 25 °C
V
GS
= 1.5 V
T
A
= - 55 °C
0
0.0
0.6
1.2
1.8
2.4
3.0
0.0
0.6
1.2
1.8
2.4
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.5
0.4
0.3
0.2
0.1
0.0
500
400
300
200
100
0
C
iss
V
GS
= 2.5 V
V
GS
= 4.5 V
C
oss
C
rss
0
2
4
6
8
10
0
5
10
15
20
25
30
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
5
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
D
= 2.3 A
V
D
= 4.5 V,
GS
= 2.3 A
4
3
2
1
0
I
V
GS
= 15 V
V
GS
= 24 V
V
D
= 2.5 V,
GS
= 1.8 A
I
0
1
2
3
4
5
- 50 - 25
0
25
50
75
100 125 150
Q
- Total Gate Charge (nC)
T - Junction Temperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
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Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
Si5511DC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.40
0.32
0.24
0.16
0.08
0.00
20
10
I
D
= 2.3 A
T
= 150 °C
J
T
A
= 125 °C
1
0.1
T
= 25 °C
J
T
A
= 25 °C
0.01
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1
2
3
4
5
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
1.3
1.2
1.1
1.0
0.9
0.8
0.7
50
40
I
D
= 250 µA
30
20
10
0
2
3
- 50 - 25
0
25
50
75
100 125 150
-4
-3
-2
-1
10
10
10
10
Time (s)
Single Pulse Power
10
1
10
10
T
- Temperature (°C)
J
Threshold Voltage
100
Limited by R
*
DS(on)
10
10 ms
1
100 ms
1 s
10 s
0.1
DC
T
= 25 °C
A
0.01
Single Pulse
0.001
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V
GS
minimum V at which R
is specified
DS(on)
GS
Safe Operating Area, Junction-to-Case
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
9
Si5511DC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
4
3
2
1
0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
- Case Temperature (°C)
T
- Case Temperature (°C)
C
C
Current Derating*
Power Derating
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
10
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
Si5511DC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
t
0.05
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 110 °C/W
thJA
(t)
3. T - T = P
JM
Z
A
DM thJA
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73787.
Document Number: 73787
S10-0547-Rev. C, 08-Mar-10
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11
Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
4
E
1
E
x
S
e
b
c
Backside View
2X 0.10/0.13 R
A
DETAIL X
NOTES:
1. All dimensions are in millimeaters.
2. Mold gate burrs shall not exceed 0.13 mm per side.
3. Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4. Dimensions exclusive of mold gate burrs.
5. No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
INCHES
Min Nom Max
Dim
A
b
c
c1
D
E
E1
e
Min
1.00
0.25
0.1
Nom
−
Max
1.10
0.039
0.010
0.004
0
−
0.012
0.006
−
0.043
0.014
0.008
0.0015
0.122
0.078
0.067
0.30
0.35
0.15
0.20
0
−
0.038
3.10
2.95
1.825
1.55
3.05
0.116
0.072
0.061
0.120
0.075
0.065
0.0256 BSC
−
1.90
1.975
1.70
1.65
0.65 BSC
−
0.28
0.42
0.011
0.017
L
0.55 BSC
5_Nom
0.022 BSC
5_Nom
S
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
www.vishay.com
1
AN812
Vishay Siliconix
Dual-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
80 mil
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
25 mil
18 mil
43 mil
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8
pin-out, package outline, pad patterns, evaluation board
layout, and thermal performance.
10 mil
26 mil
PIN-OUT
FIGURE 2.
Footprint With Copper Spreading
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thus thermal
performance. The legs of the device are very short, again
helping to reduce the thermal path to the external heatsink/pcb
and allowing a larger die to be fitted in the device if necessary.
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins 5 and
6, pins 7 and 8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0019 sq. in. or
1.22 sq. mm. This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay
Siliconix Evaluation Board described in the next section
(Figure 3).
Dual 1206-8 ChipFET
S
1
G
1
S
2
G
2
D
1
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE DUAL 1206-8
D
1
D
2
D
2
The dual ChipFET 1206-08 evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around each of the two drain leads on the top-side—
approximately 0.0246 sq. in. or 15.87 sq. mm—and vias
added through to the underside of the board, again with a
maximized copper pad area of approximately the board-size
dimensions, split into two for each of the drains. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71127
12-Dec-03
www.vishay.com
1
AN812
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30_C/W typical, 40_C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
200
Min. Footprint
160
Dual EVB
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
120
The typical RQja for the dual-channel 1206-8 ChipFET is
90_C/W steady state, identical to the SO-8. Maximum ratings
are 110_C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
80
40
1” Square PCB
Testing
0
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the Dual 1206-8
ChipFET are :
-5
-4
-3
-2
-1
10
10
10
10
10
Time (Secs)
1
10
100
1000
FIGURE 4.
Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
1) Minimum recommended pad pattern (see 185_C/W
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
2) The evaluation board with the pad pattern 128_C/W
described on Figure 3.
ASSOCIATED DOCUMENT
3) Industry standard 1” square pcb with
maximum copper both sides.
90_C/W
1206-8 ChipFET Single Thermal performance, AN811,
(http://www.vishay.com/doc?71126).
Document Number: 71127
12-Dec-03
www.vishay.com
2
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
(2.357)
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
www.vishay.com
2
Document Number: 72593
Revision: 21-Jan-08
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Revision: 02-Oct-12
Document Number: 91000
1
相关型号：
SI5513DC-T1-GE3
TRANSISTOR 3100 mA, 20 V, 2 CHANNEL, N AND P-CHANNEL, Si, SMALL SIGNAL, MOSFET, HALOGEN FREE AND ROHS COMPLIANT, 1206-8, CHIPFET-8, FET General Purpose Small Signal
VISHAY
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