SI7148DP [VISHAY]
N-Channel 75-V (D-S) MOSFET; N通道75 -V （D -S ）的MOSFET
| 型号： | SI7148DP |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 75-V (D-S) MOSFET |
| 文件： | 总3页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model Si7148DP
Vishay Siliconix
N-Channel 75-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 73323
S-50456Rev. A, 14-Mar-05
1
SPICE Device Model Si7148DP
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Condition
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Current a
VGS(th)
ID(on)
1.6
522
2
V
A
V
DS = VGS, ID = 250 µA
V
DS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 15 A
0.0091
0.012
18
0.0091
0.012
60
Drain-Source On-State Resistance a
rDS(on)
Ω
V
GS = 4.5 V, ID = 13.5 A
VDS = 15 V, ID = 15 A
IS = 38 A, VGS = 0 V
Forward Transconductance a
Diode Forward Voltage a
gfs
S
V
VSD
0.77
0.82
Dynamic b
Input Capacitance
Ciss
Coss
Crss
3600
406
165
58
2900
370
196
68
V
DS = 35 V, VGS = 0 V, f = 1 MHZ
pF
nC
Output Capacitance
Reverse Transfer Capacitance
VDS = 38 V, VGS = 10 V, ID = 15 A
Total Gate Charge
Qg
26
33
VDS = 38 V, VGS = 4.5 V, ID = 15 A
Gate-Source Charge
Gate-Drain Charge
Qgs
Qgd
9.5
9.5
16.8
16.8
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 73323
S-50456Rev. A, 14-Mar-05
2
SPICE Device Model Si7148DP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 73323
S-50456Rev. A, 14-Mar-05
3
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