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SI7794DP

更新时间：2025-07-09 10:19:20
品牌：VISHAY
描述：N-Channel 30 V (D-S) MOSFET with Schottky Diode

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SI7794DP 概述

N-Channel 30 V (D-S) MOSFET with Schottky Diode N沟道30 V （ D- S）的MOSFET与肖特基二极管

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New Product  
Si7794DP  
Vishay Siliconix  
N-Channel 30 V (D-S) MOSFET with Schottky Diode  
FEATURES  
PRODUCT SUMMARY  
•
Halogen-free According to IEC 61249-2-21  
Definition  
VDS (V)  
RDS(on) ()  
Qg (Typ.)  
I
D (A)a  
60  
0.0034 at VGS = 10 V  
0.0042 at VGS = 4.5 V  
•
SkyFET™ Monolithic TrenchFET® Gen III  
Power MOSFET and Schottky Diode  
100 % Rg Tested  
30  
23 nC  
60  
•
•
•
100 % Avalanche Tested  
PowerPAK® SO-8  
Compliant to RoHS Directive 2002/95/EC  
APPLICATIONS  
S
6.15 mm  
5.15 mm  
1
•
Low Side in Vcore, System and Memory  
- Notebook PCs  
S
2
S
D
3
G
4
D
8
D
7
D
Schottky  
Diode  
6
D
G
5
N-Channel MOSFET  
Bottom View  
Ordering Information: Si7794DP-T1-GE3 (Lead (Pb)-free and Halogen-free)  
S
ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)  
A
Parameter  
Symbol  
Limit  
30  
Unit  
VDS  
Drain-Source Voltage  
Gate-Source Voltage  
V
VGS  
20  
60a  
60a  
28.6b, c  
22.8b, c  
80  
60a  
5.6b, c  
40  
TC = 25 °C  
C = 70 °C  
T
Continuous Drain Current (TJ = 150 °C)  
ID  
TA = 25 °C  
TA = 70 °C  
A
IDM  
IS  
Pulsed Drain Current (t = 300 µs)  
TC = 25 °C  
Continuous Source-Drain Diode Current  
TA = 25 °C  
L =0.1 mH  
TC = 25 °C  
IAS  
Single Pulse Avalanche Current  
Single Pulse Avalanche Energy  
EAS  
mJ  
W
80  
48  
T
C = 70 °C  
A = 25 °C  
31  
PD  
Maximum Power Dissipation  
5.0b, c  
3.2b, c  
T
TA = 70 °C  
TJ, Tstg  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature)d, e  
- 55 to 150  
°C  
260  
THERMAL RESISTANCE RATINGS  
Parameter  
Maximum Junction-to-Ambientb, f  
Maximum Junction-to-Case (Drain)  
Symbol  
RthJA  
Typical  
Maximum  
Unit  
t 10 s  
20  
25  
°C/W  
Steady State  
RthJC  
2.1  
2.6  
Notes:  
a. Package limited.  
b. Surface mounted on 1" x 1" FR4 board.  
c. t = 10 s.  
d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper  
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not  
required to ensure adequate bottom side solder interconnection.  
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.  
f. Maximum under steady state conditions is 70 °C/W.  
Document Number: 67692  
S11-1150-Rev. A, 13-Jun-11  
www.vishay.com  
1
This datasheet is subject to change without notice.  
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
New Product  
Si7794DP  
Vishay Siliconix  
SPECIFICATIONS (T = 25 °C, unless otherwise noted)  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Static  
VDS  
VGS(th)  
IGSS  
VGS = 0, ID = 250 µA  
Drain-Source Breakdown Voltage  
30  
1
V
nA  
mA  
A
VDS = VGS, ID = 250 µA  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
2.5  
100  
0.2  
30  
VDS = 0 V, VGS  
=
20 V  
VDS = 30 V, VGS = 0 V  
0.035  
3
IDSS  
ID(on)  
RDS(on)  
gfs  
Zero Gate Voltage Drain Current  
On-State Drain Currenta  
V
DS = 30 V, VGS = 0 V, TJ = 100 °C  
V
DS 5 V, VGS = 10 V  
VGS = 10 V, ID = 20 A  
GS = 4.5 V, ID = 10 A  
VDS = 15 V, ID = 20 A  
30  
0.0027  
0.0033  
85  
0.0034  
0.0042  
Drain-Source On-State Resistancea  
V
Forward Transconductancea  
S
Dynamicb  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
2520  
630  
220  
48  
VDS = 15 V, VGS = 0 V, f = 1 MHz  
VDS = 15 V, VGS = 10 V, ID = 10 A  
pF  
72  
35  
Qg  
Total Gate Charge  
23  
nC  
Qgs  
Qgd  
Rg  
Gate-Source Charge  
Gate-Drain Charge  
Gate Resistance  
V
DS = 15 V, VGS = 4.5 V, ID = 10 A  
f = 1 MHz  
6.4  
7.2  
1.1  
22  
0.3  
2.2  
40  
30  
55  
20  
22  
20  
55  
20  
td(on)  
tr  
td(off)  
tf  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
16  
V
DD = 15 V, RL = 1.5   
ID 10 A, VGEN = 4.5 V, Rg = 1   
Turn-Off Delay Time  
Fall Time  
30  
10  
ns  
Turn-On Delay Time  
Rise Time  
11  
10  
V
DD = 15 V, RL = 1.5   
I
D 10 A, VGEN = 10 V, Rg = 1   
Turn-Off Delay Time  
Fall Time  
30  
10  
Drain-Source Body Diode Characteristics  
Continuous Source-Drain Diode Current  
IS  
ISM  
VSD  
trr  
TC = 25 °C  
IS = 3 A  
60  
80  
0.5  
55  
34  
A
Pulse Diode Forward Currenta  
Body Diode Voltage  
0.39  
28  
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Reverse Recovery Fall Time  
Reverse Recovery Rise Time  
ns  
nC  
Qrr  
ta  
17  
IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C  
14  
ns  
tb  
14  
Notes:  
a. Pulse test; pulse width 300 µs, duty cycle 2 %.  
b. Guaranteed by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
www.vishay.com  
2
Document Number: 67692  
S11-1150-Rev. A, 13-Jun-11  
This datasheet is subject to change without notice.  
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
New Product  
Si7794DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
80  
64  
48  
32  
16  
0
10  
VGS = 10 V thru 3 V  
8
6
TC = 25 °C  
4
2
TC = 125 °C  
TC = - 55 °C  
VGS = 2 V  
2.0 2.5  
0
0.0  
0.5  
1.0  
1.5  
0
0.8  
1.6  
2.4  
3.2  
4.0  
VDS - Drain-to-Source Voltage (V)  
VGS - Gate-to-Source Voltage (V)  
Output Characteristics  
Transfer Characteristics  
0.0040  
3200  
Ciss  
0.0036  
0.0032  
0.0028  
0.0024  
0.0020  
2560  
1920  
1280  
640  
0
VGS = 4.5 V  
VGS = 10 V  
Coss  
Crss  
0
16  
32  
48  
64  
80  
0
6
12  
18  
24  
30  
ID - Drain Current (A)  
VDS - Drain-to-Source Voltage (V)  
On-Resistance vs. Drain Current and Gate Voltage  
Capacitance  
10  
8
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
ID = 10 A  
ID = 20 A  
VGS = 10 V  
6
VGS = 4.5 V  
VDS = 10 V  
VDS = 20 V  
4
VDS = 15 V  
2
0
- 50 - 25  
0
25  
50  
75  
100 125 150  
0
10  
20  
30  
40  
50  
TJ - Junction Temperature (°C)  
Qg - Total Gate Charge (nC)  
Gate Charge  
On-Resistance vs. Junction Temperature  
Document Number: 67692  
S11-1150-Rev. A, 13-Jun-11  
www.vishay.com  
3
This datasheet is subject to change without notice.  
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
New Product  
Si7794DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
100  
0.015  
0.012  
0.009  
0.006  
0.003  
0.000  
ID = 20 A  
10  
TJ = 150 °C  
TJ = 25 °C  
1
0.1  
TJ = 125 °C  
0.01  
TJ = 25 °C  
0.001  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
0
2
4
6
8
10  
VGS - Gate-to-Source Voltage (V)  
VSD - Source-to-Drain Voltage (V)  
Source-Drain Diode Forward Voltage  
On-Resistance vs. Gate-to-Source Voltage  
200  
160  
120  
80  
-1  
10  
-2  
10  
10  
30 V  
-3  
10 V  
-4  
-5  
-6  
10  
10  
10  
20 V  
40  
0
0.001  
0.01  
0.1  
1
10  
0
25  
50  
75  
100  
125  
150  
Time (s)  
T - Temperature (°C)  
J
Reverse Current (Schottky)  
Single Pulse Power, Junction-to-Ambient  
IDM Limited  
100  
ID Limited  
10  
1
1 ms  
10 ms  
100 ms  
Limited by RDS(on)  
*
1 s  
10 s  
0.1  
0.01  
TC = 25 °C  
DC  
Single Pulse  
BVDSS Limited  
10  
0.01  
0.1  
1
100  
VDS - Drain-to-Source Voltage (V)  
* VGS > minimum VGS at which RDS(on) is specified  
Safe Operating Area, Junction-to-Ambient  
www.vishay.com  
4
Document Number: 67692  
S11-1150-Rev. A, 13-Jun-11  
This datasheet is subject to change without notice.  
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
New Product  
Si7794DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
100  
80  
Package Limited  
60  
40  
20  
0
0
25  
50  
75  
100  
125  
150  
TC - Case Temperature (°C)  
Current Derating*  
60  
48  
36  
24  
12  
0
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
0
25  
50  
75  
100  
125  
150  
0
25  
50  
75  
100  
125  
150  
TC - Case Temperature (°C)  
TA - Ambient Temperature (°C)  
Power, Junction-to-Case  
Power, Junction-to-Ambient  
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper  
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package  
limit.  
Document Number: 67692  
S11-1150-Rev. A, 13-Jun-11  
www.vishay.com  
5
This datasheet is subject to change without notice.  
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
New Product  
Si7794DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)  
1
Duty Cycle = 0.5  
0.2  
Notes:  
0.1  
0.1  
P
DM  
0.05  
t
1
t
2
t
t
1
2
1. Duty Cycle, D =  
0.02  
2. Per Unit Base = R  
= 70 °C/W  
thJA  
(t)  
3. T - T = P  
JM  
Z
A
DM thJA  
Single Pulse  
4. Surface Mounted  
0.01  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.05  
0.1  
0.02  
Single Pulse  
0.01  
0.0001  
0.001  
0.01  
0.1  
1
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Case  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see www.vishay.com/ppg?67692.  
www.vishay.com  
6
Document Number: 67692  
S11-1150-Rev. A, 13-Jun-11  
This datasheet is subject to change without notice.  
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Package Information  
Vishay Siliconix  
PowerPAK® SO-8, (SINGLE/DUAL)  
L
H
E2  
K
E4  
W
1
1
2
3
4
Z
2
3
4
D
L1  
E3  
A1  
Backside View of Single Pad  
L
H
K
E2  
E4  
2
E1  
E
Detail Z  
1
2
3
4
D1  
D2  
Notes  
1. Inch will govern.  
E3  
2
Dimensions exclusive of mold gate burrs.  
Backside View of Dual Pad  
3. Dimensions exclusive of mold flash and cutting burrs.  
MILLIMETERS  
INCHES  
NOM.  
0.041  
DIM.  
A
MIN.  
0.97  
0.00  
0.33  
0.23  
5.05  
4.80  
3.56  
1.32  
NOM.  
1.04  
MAX.  
1.12  
0.05  
0.51  
0.33  
5.26  
5.00  
3.91  
1.68  
MIN.  
0.038  
0.000  
0.013  
0.009  
0.199  
0.189  
0.140  
0.052  
MAX.  
0.044  
0.002  
0.020  
0.013  
0.207  
0.197  
0.154  
0.066  
A1  
b
-
-
0.41  
0.016  
c
0.28  
0.011  
D
5.15  
0.203  
D1  
D2  
D3  
D4  
D5  
E
4.90  
0.193  
3.76  
0.148  
1.50  
0.059  
0.57 TYP.  
3.98 TYP.  
6.15  
0.0225 TYP.  
0.157 TYP.  
0.242  
6.05  
5.79  
3.48  
3.68  
6.25  
5.99  
3.84  
3.91  
0.238  
0.228  
0.137  
0.145  
0.246  
0.236  
0.151  
0.154  
E1  
E2  
E3  
E4  
e
5.89  
0.232  
3.66  
0.144  
3.78  
0.149  
0.75 TYP.  
1.27 BSC  
1.27 TYP.  
-
0.030 TYP.  
0.050 BSC  
0.050 TYP.  
-
K
K1  
H
0.56  
0.51  
0.51  
0.06  
0°  
-
0.022  
0.020  
0.020  
0.002  
0°  
-
0.61  
0.71  
0.71  
0.20  
12°  
0.024  
0.028  
0.028  
0.008  
12°  
L
0.61  
0.024  
L1  
θ
0.13  
0.005  
-
-
W
M
0.15  
0.25  
0.36  
0.006  
0.010  
0.014  
0.125 TYP.  
0.005 TYP.  
ECN: T10-0055-Rev. J, 15-Feb-10  
DWG: 5881  
Document Number: 71655  
Revison: 15-Feb-10  
www.vishay.com  
1
AN821  
Vishay Siliconix  
®
PowerPAK SO-8 Mounting and Thermal Considerations  
Wharton McDaniel  
MOSFETs for switching applications are now available  
PowerPAK SO-8 SINGLE MOUNTING  
with die on resistances around 1 mΩ and with the  
capability to handle 85 A. While these die capabilities  
represent a major advance over what was available  
just a few years ago, it is important for power MOSFET  
packaging technology to keep pace. It should be obvi-  
ous that degradation of a high performance die by the  
package is undesirable. PowerPAK is a new package  
technology that addresses these issues. In this appli-  
cation note, PowerPAK’s construction is described.  
Following this mounting information is presented  
including land patterns and soldering profiles for max-  
imum reliability. Finally, thermal and electrical perfor-  
mance is discussed.  
The PowerPAK single is simple to use. The pin  
arrangement (drain, source, gate pins) and the pin  
dimensions are the same as standard SO-8 devices  
(see Figure 2). Therefore, the PowerPAK connection  
pads match directly to those of the SO-8. The only dif-  
ference is the extended drain connection area. To take  
immediate advantage of the PowerPAK SO-8 single  
devices, they can be mounted to existing SO-8 land  
patterns.  
THE PowerPAK PACKAGE  
The PowerPAK package was developed around the  
SO-8 package (Figure 1). The PowerPAK SO-8 uti-  
lizes the same footprint and the same pin-outs as the  
standard SO-8. This allows PowerPAK to be substi-  
tuted directly for a standard SO-8 package. Being a  
leadless package, PowerPAK SO-8 utilizes the entire  
SO-8 footprint, freeing space normally occupied by the  
leads, and thus allowing it to hold a larger die than a  
standard SO-8. In fact, this larger die is slightly larger  
than a full sized DPAK die. The bottom of the die attach  
pad is exposed for the purpose of providing a direct,  
low resistance thermal path to the substrate the device  
is mounted on. Finally, the package height is lower  
than the standard SO-8, making it an excellent choice  
for applications with space constraints.  
Standard SO-8  
PowerPAK SO-8  
Figure 2.  
The minimum land pattern recommended to take full  
advantage of the PowerPAK thermal performance see  
Application Note 826, Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Sili-  
conix MOSFETs. Click on the PowerPAK SO-8 single  
in the index of this document.  
In this figure, the drain land pattern is given to make full  
contact to the drain pad on the PowerPAK package.  
This land pattern can be extended to the left, right, and  
top of the drawn pattern. This extension will serve to  
increase the heat dissipation by decreasing the ther-  
mal resistance from the foot of the PowerPAK to the  
PC board and therefore to the ambient. Note that  
increasing the drain land area beyond a certain point  
will yield little decrease in foot-to-board and foot-to-  
ambient thermal resistance. Under specific conditions  
of board configuration, copper weight and layer stack,  
experiments have found that more than about 0.25 to  
2
0.5 in of additional copper (in addition to the drain  
land) will yield little improvement in thermal perfor-  
mance.  
Figure 1. PowerPAK 1212 Devices  
Document Number 71622  
28-Feb-06  
www.vishay.com  
1
AN821  
Vishay Siliconix  
PowerPAK SO-8 DUAL  
For the lead (Pb)-free solder profile, see http://  
www.vishay.com/doc?73257.  
The pin arrangement (drain, source, gate pins) and the  
pin dimensions of the PowerPAK SO-8 dual are the  
same as standard SO-8 dual devices. Therefore, the  
PowerPAK device connection pads match directly to  
those of the SO-8. As in the single-channel package,  
the only exception is the extended drain connection  
area. Manufacturers can likewise take immediate  
advantage of the PowerPAK SO-8 dual devices by  
mounting them to existing SO-8 dual land patterns.  
To take the advantage of the dual PowerPAK SO-8’s  
thermal performance, the minimum recommended  
land pattern can be found in Application Note 826,  
Recommended Minimum Pad Patterns With Outline  
Drawing Access for Vishay Siliconix MOSFETs. Click  
on the PowerPAK 1212-8 dual in the index of this doc-  
ument.  
Ramp-Up Rate  
+ 6 °C /Second Maximum  
The gap between the two drain pads is 24 mils. This  
matches the spacing of the two drain pads on the Pow-  
erPAK SO-8 dual package.  
Temperature at 155 15 °C  
120 Seconds Maximum  
Temperature Above 180 °C  
Maximum Temperature  
Time at Maximum Temperature  
Ramp-Down Rate  
70 - 180 Seconds  
240 + 5/- 0 °C  
20 - 40 Seconds  
+ 6 °C/Second Maximum  
REFLOW SOLDERING  
Vishay Siliconix surface-mount packages meet solder  
reflow reliability requirements. Devices are subjected  
to solder reflow as a test preconditioning and are then  
reliability-tested using temperature cycle, bias humid-  
ity, HAST, or pressure pot. The solder reflow tempera-  
ture profile used, and the temperatures and time  
duration, are shown in Figures 3 and 4.  
Figure 3. Solder Reflow Temperature Profile  
10 s (max)  
210 - 220 °C  
3 °C(max)  
4 °C/s (max)  
183 °C  
140 - 170 °C  
50 s (max)  
3 °C(max)  
60 s (min)  
Reflow Zone  
Pre-Heating Zone  
Maximum peak temperature at 240 °C is allowed.  
Figure 3. Solder Reflow Temperatures and Time Durations  
www.vishay.com  
2
Document Number 71622  
28-Feb-06  
AN821  
Vishay Siliconix  
THERMAL PERFORMANCE  
Introduction  
Because of the presence of the trough, this result sug-  
gests a minimum performance improvement of 10 °C/W  
by using a PowerPAK SO-8 in a standard SO-8 PC  
board mount.  
A basic measure of a device’s thermal performance is  
the junction-to-case thermal resistance, Rθ , or the  
junction-to-foot thermal resistance, Rθ . This parameter  
jc  
jf  
is measured for the device mounted to an infinite heat  
sink and is therefore a characterization of the device  
only, in other words, independent of the properties of the  
object to which the device is mounted. Table 1 shows a  
comparison of the DPAK, PowerPAK SO-8, and stan-  
dard SO-8. The PowerPAK has thermal performance  
equivalent to the DPAK, while having an order of magni-  
tude better thermal performance over the SO-8.  
The only concern when mounting a PowerPAK on a  
standard SO-8 pad pattern is that there should be no  
traces running between the body of the MOSFET.  
Where the standard SO-8 body is spaced away from the  
pc board, allowing traces to run underneath, the Power-  
PAK sits directly on the pc board.  
Thermal Performance - Spreading Copper  
Designers may add additional copper, spreading cop-  
per, to the drain pad to aid in conducting heat from a  
device. It is helpful to have some information about the  
thermal performance for a given area of spreading cop-  
per.  
TABLE 1.  
DPAK and PowerPAK SO-8  
Equivalent Steady State Performance  
DPAK  
PowerPAK  
SO-8  
Standard  
SO-8  
Thermal  
Resistance Rθjc  
1.2 °C/W  
1.0 °C/W  
16 °C/W  
Figure 6 shows the thermal resistance of a PowerPAK  
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4  
PC board. The two internal layers and the backside layer  
are solid copper. The internal layers were chosen as  
solid copper to model the large power and ground  
planes common in many applications. The top layer was  
cut back to a smaller area and at each step junction-to-  
ambient thermal resistance measurements were taken.  
The results indicate that an area above 0.3 to 0.4 square  
inches of spreading copper gives no additional thermal  
performance improvement. A subsequent experiment  
was run where the copper on the back-side was  
reduced, first to 50 % in stripes to mimic circuit traces,  
and then totally removed. No significant effect was  
observed.  
Thermal Performance on Standard SO-8 Pad Pattern  
Because of the common footprint, a PowerPAK SO-8  
can be mounted on an existing standard SO-8 pad pat-  
tern. The question then arises as to the thermal perfor-  
mance of the PowerPAK device under these conditions.  
A characterization was made comparing a standard SO-8  
and a PowerPAK device on a board with a trough cut out  
underneath the PowerPAK drain pad. This configuration  
restricted the heat flow to the SO-8 land pads. The  
results are shown in Figure 5.  
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board  
SO-8 Pattern, Trough Under Drain  
R
vs. Spreading Copper  
th  
(0 %, 50 %, 100 % Back Copper)  
60  
50  
56  
51  
46  
41  
36  
40  
Si4874DY  
30  
Si7446DP  
20  
100 %  
10  
0 %  
50 %  
0
0.0001  
0.01  
1
10000  
100  
Pulse Duration (sec)  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path  
Figure 6. Spreading Copper Junction-to-Ambient Performance  
Document Number 71622  
28-Feb-06  
www.vishay.com  
3
AN821  
Vishay Siliconix  
SYSTEM AND ELECTRICAL IMPACT OF  
PowerPAK SO-8  
In any design, one must take into account the change in  
Suppose each device is dissipating 2.7 W. Using the  
junction-to-foot thermal resistance characteristics of the  
PowerPAK SO-8 and the standard SO-8, the die tem-  
perature is determined to be 107 °C for the PowerPAK  
(and for DPAK) and 148 °C for the standard SO-8. This  
is a 2 °C rise above the board temperature for the Pow-  
erPAK and a 43 °C rise for the standard SO-8. Referring  
to Figure 7, a 2 °C difference has minimal effect on  
MOSFET r  
with temperature (Figure 7).  
DS(on)  
On-Resistance vs. Junction Temperature  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
r
whereas a 43C difference has a significant effect  
V
I
= 10 V  
GS  
DS(on)  
= 23 A  
D
on r  
.
DS(on)  
Minimizing the thermal rise above the board tempera-  
ture by using PowerPAK has not only eased the thermal  
design but it has allowed the device to run cooler, keep  
r
low, and permits the device to handle more cur-  
DS(on)  
rent than the same MOSFET die in the standard SO-8  
package.  
CONCLUSIONS  
PowerPAK SO-8 has been shown to have the same  
thermal performance as the DPAK package while hav-  
ing the same footprint as the standard SO-8 package.  
The PowerPAK SO-8 can hold larger die approximately  
equal in size to the maximum that the DPAK can accom-  
modate implying no sacrifice in performance because of  
package limitations.  
Recommended PowerPAK SO-8 land patterns are pro-  
vided to aid in PC board layout for designs using this  
new package.  
-50  
-25  
0
25  
50  
75  
100 125 150  
T
- Junction Temperature (°C)  
J
Figure 7. MOSFET rDS(on) vs. Temperature  
A MOSFET generates internal heat due to the current  
passing through the channel. This self-heating raises  
the junction temperature of the device above that of the  
PC board to which it is mounted, causing increased  
power dissipation in the device. A major source of this  
problem lies in the large values of the junction-to-foot  
thermal resistance of the SO-8 package.  
Thermal considerations have indicated that significant  
advantages can be gained by using PowerPAK SO-8  
devices in designs where the PC board was laid out for  
the standard SO-8. Applications experimental data gave  
thermal performance data showing minimum and typical  
thermal performance in a SO-8 environment, plus infor-  
mation on the optimum thermal performance obtainable  
including spreading copper. This further emphasized the  
DPAK equivalency.  
PowerPAK SO-8 minimizes the junction-to-board ther-  
mal resistance to where the MOSFET die temperature is  
very close to the temperature of the PC board. Consider  
two devices mounted on a PC board heated to 105 °C  
by other components on the board (Figure 8).  
PowerPAK SO-8 therefore has the desired small size  
characteristics of the SO-8 combined with the attractive  
thermal characteristics of the DPAK package.  
PowerPAK SO-8  
Standard SO-8  
107 °C  
148 °C  
0.8 °C/W  
PC Board at 105 °C  
16 C/W  
Figure 8. Temperature of Devices on a PC Board  
www.vishay.com  
4
Document Number 71622  
28-Feb-06  
Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single  
0.260  
(6.61)  
0.150  
(3.81)  
0.024  
(0.61)  
0.026  
(0.66)  
0.050  
(1.27)  
0.032  
(0.82)  
0.040  
(1.02)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
Document Number: 72599  
Revision: 21-Jan-08  
www.vishay.com  
15  
Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical  
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular  
product with the properties described in the product specification is suitable for use in a particular application. Parameters  
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All  
operating parameters, including typical parameters, must be validated for each customer application by the customer’s  
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,  
including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree  
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and  
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay  
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to  
obtain written terms and conditions regarding products designed for such applications.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by  
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.  
Document Number: 91000  
Revision: 11-Mar-11  
www.vishay.com  
1

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