SI7904BDN-T1-GE3 [VISHAY]

Dual N-Channel 20-V (D-S) MOSFET; 双N通道20 -V (D -S )的MOSFET
SI7904BDN-T1-GE3
型号: SI7904BDN-T1-GE3
厂家: VISHAY    VISHAY
描述:

Dual N-Channel 20-V (D-S) MOSFET
双N通道20 -V (D -S )的MOSFET

文件: 总13页 (文件大小:558K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Si7904BDN  
Vishay Siliconix  
Dual N-Channel 20-V (D-S) MOSFET  
FEATURES  
PRODUCT SUMMARY  
Halogen-free According to IEC 61249-2-21  
VDS (V)  
RDS(on) (Ω)  
Qg (Typ.)  
I
D (A)a  
Available  
TrenchFET® Power MOSFET  
0.030 at VGS = 4.5 V  
0.036 at VGS = 2.5 V  
0.045 at VGS = 1.8 V  
6
6
6
20  
9 nC  
APPLICATIONS  
HDD Spindle Drive  
PowerPAK 1212-8  
S1  
3.30 mm  
3.30 mm  
D
1
D
2
1
G1  
2
S2  
3
G2  
4
D1  
8
D1  
G
1
G
2
7
D2  
6
D2  
5
Bottom View  
S
1
S
2
Ordering Information: Si7904BDN-T1-E3 (Lead (Pb)-free)  
Si7904BDN-T1-GE3 (Lead (Pb)-free and Halogen-free)  
N-Channel MOSFET  
N-Channel MOSFET  
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted  
A
Parameter  
Symbol  
Limit  
20  
Unit  
Drain-Source Voltage  
Gate-Source Voltage  
VDS  
V
VGS  
8
6a  
6a  
6a  
5.1b, c  
T
T
C = 25 °C  
C = 85 °C  
Continuous Drain Current (TJ = 150 °C)  
ID  
TA = 25 °C  
TA = 85 °C  
A
Pulsed Drain Current  
IDM  
IS  
20  
6a  
T
C = 25 °C  
Continuous Source-Drain Diode Current  
2.1b, c  
17.8  
9.3  
2.5b, c  
1.3b, c  
TA = 25 °C  
TC = 25 °C  
T
C = 85 °C  
Maximum Power Dissipation  
PD  
W
TA = 25 °C  
TA = 85 °C  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature)d, e  
TJ, Tstg  
- 55 to 150  
260  
°C  
THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
Typical  
40  
Maximum  
Unit  
Maximum Junction-to-Ambientb, f  
t 10 s  
Steady State  
RthJA  
RthJC  
50  
7
°C/W  
Maximum Junction-to-Case (Drain)  
5.6  
Notes:  
a. Package limited.  
b. Surface Mounted on 1" x 1" FR4 board.  
c. t = 10 s.  
d. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed  
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed  
and is not required to ensure adequate bottom side solder interconnection.  
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.  
f. Maximum under steady state conditions is 94 °C/W.  
Document Number: 74409  
S-83050-Rev. B, 29-Dec-08  
www.vishay.com  
1
Si7904BDN  
Vishay Siliconix  
SPECIFICATIONS T = 25 °C, unless otherwise noted  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Static  
VDS  
ΔVDS/TJ  
ΔVGS(th)/TJ  
VGS(th)  
VGS = 0 V, ID = 250 µA  
ID = 250 µA  
Drain-Source Breakdown Voltage  
20  
V
V
DS Temperature Coefficient  
22.5  
- 2.9  
mV/°C  
VGS(th) Temperature Coefficient  
VDS = VGS , ID = 250 µA  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
0.45  
20  
1.0  
100  
1
V
IGSS  
VDS = 0 V, VGS  
=
8 V  
ns  
VDS = 20 V, VGS = 0 V  
DS = 20 V, VGS = 0 V, TJ = 55 °C  
VDS 5 V, VGS = 4.5 V  
VGS = 4.5 V, ID = 7.1 A  
VGS = 2.5 V, ID = 6.5 A  
VGS = 1.8 V, ID = 2.2 A  
VDS = 10 V, ID = 7.1 A  
IDSS  
Zero Gate Voltage Drain Current  
On-State Drain Currenta  
µA  
V
10  
ID(on)  
Α
0.025  
0.030  
0.036  
26  
0.030  
0.036  
0.045  
RDS(on)  
Ω
Drain-Source On-State Resistancea  
Forward Transconductancea  
gfs  
S
Dynamicb  
ciss  
coss  
crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
860  
110  
65  
16  
9
V
DS = 10 V, VGS = 0 V, f = 1 MHz  
pF  
V
DS = 10 V, VGS = 8 V, ID = 6 A  
DS = 10 V, VGS = 4.5 V, ID = 6 A  
f = 1 MHz  
24  
Total Gate Charge  
Qg  
13.5  
nC  
Qgs  
Qgd  
Rg  
Gate-Source Charge  
1.4  
1.4  
3.2  
7
V
Gate-Drain Charge  
Gate Resistance  
Ω
td(on)  
tr  
td(off)  
tf  
td(on)  
tr  
td(off)  
tf  
Turn-on Delay Time  
15  
90  
40  
10  
10  
25  
40  
10  
Rise Time  
60  
25  
6
V
DD = 10 V, RL = 1 Ω  
Turn-Off Delay Time  
ID 5.1 A, VGEN = 4.5 V, Rg = 1 Ω  
Fall Time  
ns  
Turn-on Delay Time  
5
Rise Time  
15  
25  
5
VDD = 10 V, RL = 1 Ω  
Turn-Off Delay Time  
ID 5.1 A, VGEN = 8 V, Rg = 1 Ω  
Fall Time  
Drain-Source Body Diode Characteristics  
Continuous Source-Drain Diode Current  
Pulse Diode Forward Current  
Body Diode Voltage  
IS  
ISM  
VSD  
trr  
TC = 25 °C  
6
A
20  
1.2  
40  
20  
IS = 5.1 A, VGS = 0 V  
0.8  
20  
9
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Reverse Recovery Fall Time  
Reverse Recovery Rise Time  
ns  
nC  
Qrr  
ta  
IF = 5.1 A, dI/dt = 100 A/µs, TJ = 25 °C  
12  
8
ns  
tb  
Notes:  
a. Pulse test; pulse width 300 µs, duty cycle 2 %  
b. Guaranteed by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
www.vishay.com  
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Document Number: 74409  
S-83050-Rev. B, 29-Dec-08  
Si7904BDN  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
10  
8
20  
V
GS  
= 5 thru 2 V  
15  
10  
5
6
4
1.5 V  
1 V  
T
= 125 °C  
C
2
25 °C  
- 55 °C  
0
0
0.0  
0.4  
0.8  
1.2  
1.6  
2.0  
0.0  
0.3  
0.6  
0.9  
1.2  
1.5  
1.8  
V
DS  
- Drain-to-Source Voltage (V)  
V
GS  
- Gate-to-Source Voltage (V)  
Output Characteristics  
Transfer Characteristics  
0.060  
0.050  
0.040  
0.030  
0.020  
1200  
900  
600  
300  
0
V
GS  
= 1.8 V  
C
iss  
V
GS  
= 2.5 V  
C
oss  
V
GS  
= 4.5 V  
C
rss  
0
5
10  
- Drain Current (A)  
15  
20  
0
4
8
12  
16  
20  
I
D
V
DS  
- Drain-to-Source Voltage (V)  
On-Resistance vs. Drain Current and Gate Voltage  
Capacitance  
8
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
V
D
= 10 V  
DS  
= 6 A  
7
6
5
4
3
2
1
0
I
I
D
= 7.1 A  
V
= 16 V  
DS  
= 6 A  
I
D
0
3
6
9
12  
15  
18  
- 50 - 25  
0
25  
50  
75  
100 125 150  
Q
- Total Gate Charge (nC)  
T - Junction Temperature (°C)  
J
g
Gate Charge  
On-Resistance vs. Junction Temperature  
Document Number: 74409  
S-83050-Rev. B, 29-Dec-08  
www.vishay.com  
3
Si7904BDN  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
100  
0.060  
0.050  
0.040  
0.030  
0.020  
I
D
= 7.1 A  
25 °C  
I = 7.1 A  
D
125 °C  
T
= 150 °C  
J
10  
T
= 25 °C  
J
1
0.4  
- Source-to-Drain Voltage (V)  
0
0.2  
0.6  
0.8  
1
1.2  
0
1
2
3
4
5
V
SD  
V
GS  
- Gate-to-Source Voltage (V)  
On-Resistance vs. Gate-to-Source Voltage  
Source-Drain Diode Forward Voltage  
0.8  
50  
40  
I
D
= 250 µA  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
30  
20  
10  
0
- 50 - 25  
0
25  
50  
75  
100 125 150  
0.001  
0.01  
0.1  
1
10  
100  
600  
T
- Temperature (°C)  
J
Time (s)  
Threshold Voltage  
Single Pulse Power (Junction-to-Ambient)  
100  
Limited by R  
*
DS(on)  
10  
1
100 µs  
1 ms  
10 ms  
100 ms  
1 s  
10 s  
DC  
T
= 25 °C  
A
0.1  
Single Pulse  
BVDSS Limited  
0.01  
0.1  
1
10  
100  
V
DS  
- Drain-to-Source Voltage (V)  
*
V
GS  
minimum V at which R is specified  
DS(on)  
GS  
Safe Operating Area, Junction-to-Ambient  
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Document Number: 74409  
S-83050-Rev. B, 29-Dec-08  
Si7904BDN  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
25  
25  
20  
15  
10  
5
20  
15  
10  
5
0
0
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
100  
125  
150  
T
- Case Temperature (°C)  
T
- Case Temperature (°C)  
C
C
Current Derating*  
Power Derating  
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper  
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package  
limit.  
Document Number: 74409  
S-83050-Rev. B, 29-Dec-08  
www.vishay.com  
5
Si7904BDN  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
Notes:  
P
DM  
0.1  
0.05  
t
1
t
2
t
t
1
0.02  
1 .Duty Cycle, D =  
2. Per Unit Base = R  
2
thJA  
= 75 °C/W  
(t)  
3. T - T = P Z  
DM thJA  
JM  
A
Single Pulse  
4. Surface Mounted  
0.01  
-4  
-3  
-2  
-1  
10  
10  
10  
10  
1
10  
100  
600  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.05  
0.1  
0.02  
Single Pulse  
0.01  
-3  
-2  
-1  
10  
10  
10  
Square Wave Pulse Duration (s)  
1
10  
Normalized Thermal Transient Impedance, Junction-to-Case  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see www.vishay.com/ppg?74409.  
www.vishay.com  
6
Document Number: 74409  
S-83050-Rev. B, 29-Dec-08  
Package Information  
Vishay Siliconix  
PowerPAK® 1212-8, (SINGLE/DUAL)  
L
H
E2  
E4  
K
W
8
1
1
2
3
4
Z
2
4
5
L1  
E3  
Backside View of Single Pad  
A1  
L
H
K
E2  
E4  
H
2
E1  
E
1
2
3
4
Detail Z  
D1  
D2  
Notes:  
1. Inch will govern  
2
Dimensions exclusive of mold gate burrs  
3. Dimensions exclusive of mold flash and cutting burrs  
E3  
Backside View of Dual Pad  
MILLIMETERS  
INCHES  
NOM.  
0.041  
DIM.  
A
MIN.  
0.97  
0.00  
0.23  
0.23  
3.20  
2.95  
1.98  
0.48  
NOM.  
1.04  
MAX.  
MIN.  
0.038  
0.000  
0.009  
0.009  
0.126  
0.116  
0.078  
0.019  
MAX.  
0.044  
0.002  
0.016  
0.013  
0.134  
0.124  
0.088  
0.035  
1.12  
0.05  
0.41  
0.33  
3.40  
3.15  
2.24  
0.89  
A1  
b
-
-
0.30  
0.012  
c
0.28  
0.011  
D
3.30  
0.130  
D1  
D2  
D3  
D4  
D5  
E
3.05  
0.120  
2.11  
0.083  
-
-
0.47 TYP.  
2.3 TYP.  
3.30  
0.0185 TYP.  
0.090 TYP.  
0.130  
3.20  
2.95  
1.47  
1.75  
3.40  
3.15  
1.73  
1.98  
0.126  
0.116  
0.058  
0.069  
0.134  
0.124  
0.068  
0.078  
E1  
E2  
E3  
E4  
e
3.05  
0.120  
1.60  
0.063  
1.85  
0.073  
0.34 TYP.  
0.65 BSC  
0.86 TYP.  
-
0.013 TYP.  
0.026 BSC  
0.034 TYP.  
-
K
K1  
H
0.35  
0.30  
0.30  
0.06  
0°  
-
0.014  
0.012  
0.012  
0.002  
0°  
-
0.41  
0.51  
0.56  
0.20  
12°  
0.016  
0.020  
0.022  
0.008  
12°  
L
0.43  
0.017  
L1  
θ
0.13  
0.005  
-
-
W
M
0.15  
0.25  
0.36  
0.006  
0.010  
0.014  
0.125 TYP.  
0.005 TYP.  
ECN: S10-0951-Rev. J, 03-May-10  
DWG: 5882  
Document Number: 71656  
Revison: 03-May-10  
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1
AN822  
Vishay Siliconix  
®
PowerPAK 1212 Mounting and Thermal Considerations  
Johnson Zhao  
MOSFETs for switching applications are now available  
The PowerPAK 1212-8 has a footprint area compara-  
ble to TSOP-6. It is over 40 % smaller than standard  
TSSOP-8. Its die capacity is more than twice the size  
of the standard TSOP-6’s. It has thermal performance  
an order of magnitude better than the SO-8, and 20  
times better than TSSOP-8. Its thermal performance is  
better than all current SMT packages in the market. It  
will take the advantage of any PC board heat sink  
capability. Bringing the junction temperature down also  
increases the die efficiency by around 20 % compared  
with TSSOP-8. For applications where bigger pack-  
ages are typically required solely for thermal consider-  
ation, the PowerPAK 1212-8 is a good option.  
with die on resistances around 1 mΩ and with the  
capability to handle 85 A. While these die capabilities  
represent a major advance over what was available  
just a few years ago, it is important for power MOSFET  
packaging technology to keep pace. It should be obvi-  
ous that degradation of a high performance die by the  
package is undesirable. PowerPAK is a new package  
technology that addresses these issues. The PowerPAK  
1212-8 provides ultra-low thermal impedance in a  
small package that is ideal for space-constrained  
applications. In this application note, the PowerPAK  
1212-8’s construction is described. Following this,  
mounting information is presented. Finally, thermal  
and electrical performance is discussed.  
Both the single and dual PowerPAK 1212-8 utilize the  
same pin-outs as the single and dual PowerPAK SO-8.  
The low 1.05 mm PowerPAK height profile makes both  
versions an excellent choice for applications with  
space constraints.  
THE PowerPAK PACKAGE  
The PowerPAK 1212-8 package (Figure 1) is a deriva-  
tive of PowerPAK SO-8. It utilizes the same packaging  
technology, maximizing the die area. The bottom of the  
die attach pad is exposed to provide a direct, low resis-  
tance thermal path to the substrate the device is  
mounted on. The PowerPAK 1212-8 thus translates  
the benefits of the PowerPAK SO-8 into a smaller  
package, with the same level of thermal performance.  
PowerPAK 1212 SINGLE MOUNTING  
To take the advantage of the single PowerPAK 1212-8’s  
thermal performance see Application Note 826,  
Recommended Minimum Pad Patterns With Outline  
Drawing Access for Vishay Siliconix MOSFETs. Click  
on the PowerPAK 1212-8 single in the index of this  
document.  
(Please refer to application note “PowerPAK SO-8  
Mounting and Thermal Considerations.”)  
In this figure, the drain land pattern is given to make full  
contact to the drain pad on the PowerPAK package.  
This land pattern can be extended to the left, right, and  
top of the drawn pattern. This extension will serve to  
increase the heat dissipation by decreasing the ther-  
mal resistance from the foot of the PowerPAK to the  
PC board and therefore to the ambient. Note that  
increasing the drain land area beyond a certain point  
will yield little decrease in foot-to-board and foot-to-  
ambient thermal resistance. Under specific conditions  
of board configuration, copper weight, and layer stack,  
experiments have found that adding copper beyond an  
2
area of about 0.3 to 0.5 in of will yield little improve-  
ment in thermal performance.  
Figure 1. PowerPAK 1212 Devices  
Document Number 71681  
03-Mar-06  
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1
AN822  
Vishay Siliconix  
PowerPAK 1212 DUAL  
To take the advantage of the dual PowerPAK 1212-8’s  
thermal performance, the minimum recommended  
land pattern can be found in Application Note 826,  
Recommended Minimum Pad Patterns With Outline  
Drawing Access for Vishay Siliconix MOSFETs. Click  
on the PowerPAK 1212-8 dual in the index of this doc-  
ument.  
ture profile used, and the temperatures and time  
duration, are shown in Figures 2 and 3. For the lead  
(Pb)-free solder profile, see http://www.vishay.com/  
doc?73257.  
The gap between the two drain pads is 10 mils. This  
matches the spacing of the two drain pads on the Pow-  
erPAK 1212-8 dual package.  
This land pattern can be extended to the left, right, and  
top of the drawn pattern. This extension will serve to  
increase the heat dissipation by decreasing the ther-  
mal resistance from the foot of the PowerPAK to the  
PC board and therefore to the ambient. Note that  
increasing the drain land area beyond a certain point  
will yield little decrease in foot-to-board and foot-to-  
ambient thermal resistance. Under specific conditions  
of board configuration, copper weight, and layer stack,  
experiments have found that adding copper beyond an  
area of about 0.3 to 0.5 in of will yield little improve-  
Ramp-Up Rate  
+ 6 °C /Second Maximum  
2
Temperature at 155 15 °C  
Temperature Above 180 °C  
Maximum Temperature  
Time at Maximum Temperature  
Ramp-Down Rate  
120 Seconds Maximum  
ment in thermal performance.  
70 - 180 Seconds  
240 + 5/- 0 °C  
20 - 40 Seconds  
REFLOW SOLDERING  
+ 6 °C/Second Maximum  
Vishay Siliconix surface-mount packages meet solder  
reflow reliability requirements. Devices are subjected  
to solder reflow as a preconditioning test and are then  
reliability-tested using temperature cycle, bias humid-  
ity, HAST, or pressure pot. The solder reflow tempera-  
Figure 2. Solder Reflow Temperature Profile  
10 s (max)  
210 - 220 °C  
3 °C/s (max)  
4 °C/s (max)  
183 °C  
140 - 170 °C  
50 s (max)  
3° C/s (max)  
60 s (min)  
Reflow Zone  
Pre-Heating Zone  
Maximum peak temperature at 240 °C is allowed.  
Figure 3. Solder Reflow Temperatures and Time Durations  
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Document Number 71681  
03-Mar-06  
AN822  
Vishay Siliconix  
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE  
Package  
SO-8  
Single  
20  
TSSOP-8  
TSOP-8  
PPAK 1212  
PPAK SO-8  
Single Dual  
1.8 5.5  
Configuration  
Dual  
Single  
Dual  
Single  
40  
Dual  
Single  
Dual  
40  
52  
83  
90  
2.4  
5.5  
Thermal Resiatance RthJC(C/W)  
PowerPAK 1212  
49.8 °C  
Standard SO-8  
Standard TSSOP-8  
TSOP-6  
85 °C  
149 °C  
125 °C  
2.4 °C/W  
20 °C/W  
52 °C/W  
40 °C/W  
PC Board at 45 °C  
Figure 4. Temperature of Devices on a PC Board  
THERMAL PERFORMANCE  
Introduction  
Spreading Copper  
A basic measure of a device’s thermal performance is Designers add additional copper, spreading copper, to  
the junction-to-case thermal resistance, Rθjc, or the the drain pad to aid in conducting heat from a device. It  
junction to- foot thermal resistance, Rθjf. This parameter is helpful to have some information about the thermal  
is measured for the device mounted to an infinite heat performance for a given area of spreading copper.  
sink and is therefore a characterization of the device  
only, in other words, independent of the properties of the  
object to which the device is mounted. Table 1 shows a  
comparison of the PowerPAK 1212-8, PowerPAK SO-8,  
standard TSSOP-8 and SO-8 equivalent steady state  
performance.  
Figure 5 and Figure 6 show the thermal resistance of a  
PowerPAK 1212-8 single and dual devices mounted on  
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-  
nal layers and the backside layer are solid copper. The  
internal layers were chosen as solid copper to model the  
large power and ground planes common in many appli-  
By minimizing the junction-to-foot thermal resistance, the cations. The top layer was cut back to a smaller area and  
MOSFET die temperature is very close to the tempera- at each step junction-to-ambient thermal resistance  
ture of the PC board. Consider four devices mounted on measurements were taken. The results indicate that an  
a PC board with a board temperature of 45 °C (Figure 4)  
.
area above 0.2 to 0.3 square inches of spreading copper  
gives no additional thermal performance improvement.  
A subsequent experiment was run where the copper on  
the back-side was reduced, first to 50 % in stripes to  
mimic circuit traces, and then totally removed. No signif-  
icant effect was observed.  
Suppose each device is dissipating 2 W. Using the junc-  
tion-to-foot thermal resistance characteristics of the  
PowerPAK 1212-8 and the other SMT packages, die  
temperatures are determined to be 49.8 °C for the Pow-  
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for  
standard TSSOP-8, and 125 °C for TSOP-6. This is a  
4.8 °C rise above the board temperature for the Power-  
PAK 1212-8, and over 40 °C for other SMT packages. A  
4.8 °C rise has minimal effect on r  
whereas a rise  
DS(ON)  
of over 40 °C will cause an increase in r  
as 20 %.  
as high  
DS(ON)  
Document Number 71681  
03-Mar-06  
www.vishay.com  
3
AN822  
Vishay Siliconix  
130  
120  
110  
100  
90  
105  
Spreading Copper (sq. in.)  
Spreading Copper (sq. in.)  
95  
85  
75  
65  
55  
45  
80  
50 %  
100 %  
70  
100 %  
0 %  
60  
50 %  
0 %  
50  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
Figure 6. Spreading Copper - Junction-to-Ambient Performance  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
Figure 5. Spreading Copper - Si7401DN  
CONCLUSIONS  
As a derivative of the PowerPAK SO-8, the PowerPAK The PowerPAK 1212-8 combines small size with attrac-  
1212-8 uses the same packaging technology and has tive thermal characteristics. By minimizing the thermal  
been shown to have the same level of thermal perfor- rise above the board temperature, PowerPAK simplifies  
mance while having a footprint that is more than 40 % thermal design considerations, allows the device to run  
smaller than the standard TSSOP-8.  
cooler, keeps r  
low, and permits the device to  
DS(ON)  
handle more current than a same- or larger-size MOS-  
FET die in the standard TSSOP-8 or SO-8 packages.  
Recommended PowerPAK 1212-8 land patterns are  
provided to aid in PC board layout for designs using this  
new package.  
www.vishay.com  
4
Document Number 71681  
03-Mar-06  
Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Dual  
0.152  
(3.860)  
0.039  
0.068  
(0.990)  
(1.725)  
0.016  
(0.405)  
0.039  
0.010  
(0.990)  
(0.225)  
0.094  
(2.390)  
0.039  
(0.990)  
0.026  
(0.660)  
0.030  
(0.760)  
0.025  
(0.635)  
Recommended Minimum PADs for PowerPAK 1212-8 Dual  
Dimensions in Inches/(mm)  
Return to Index  
www.vishay.com  
1
Document Number: 72598  
Revision: 14-Apr-08  
Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
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Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
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Document Number: 91000  
Revision: 11-Mar-11  
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1

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