SI8417DB [VISHAY]

P-Channel 1.8-V (G-S) MOSFET; P沟道1.8 -V （G -S ）的MOSFET


型号：	SI8417DB
厂家：	VISHAY
描述：	P-Channel 1.8-V (G-S) MOSFET P沟道1.8 -V （G -S ）的MOSFET
文件：	总3页 (文件大小：182K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPICE Device Model Si8417DB

Vishay Siliconix

P-Channel 1.8-V (G-S) MOSFET

CHARACTERISTICS

• P-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical electrical

characteristics of the p-channel vertical DMOS. The subcircuit

model is extracted and optimized over the −55 to 125°C

temperature ranges under the pulsed 0-V to 5-V gate drive. The

saturated output impedance is best fit at the gate bias near the

threshold voltage.

A novel gate-to-drain feedback capacitance network is used to model

the gate charge characteristics while avoiding convergence difficulties

of the switched C_gdmodel. All model parameter values are optimized

to provide a best fit to the measured electrical data and are not

intended as an exact physical interpretation of the device.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

www.vishay.com

Document Number: 74135

S-52282Rev. A, 31-Oct-05

SPICE Device Model Si8417DB

Vishay Siliconix

SPECIFICATIONS (T_J= 25°C UNLESS OTHERWISE NOTED)

Simulated Measured

Parameter

Symbol

Test Condition

Unit

Data

Static

Gate Threshold Voltage

On-State Drain Current^a

V_GS(th)

I_D(on)

0.80

191

_DS= V_GS, I_D= −250µA

V_DS≤ −5V, V_GS= −4.5V

0.0184

0.0211

0.0252

0.0174

0.0214

0.0270

8.3

V_GS= −4.5V, I_D= −1 A

V_GS= −2.5V, I_D= −1 Α

V_GS= −1.8V, I_D= −1 Α

Drain-Source On-State Resistance^a

r_DS(on)

Ω

Forward Transconductance^a

Diode Forward Voltage^a

g_fs

V_DS= −4V, I_D= −1 A

V_SD

_S= −1A, V_GS= 0 V

−0.78

−0.80

Dynamic^b

Input Capacitance

C_iss

C_oss

C_rss

3228

913

542

2220

865

555

_DS= −6 V, V_GS= 0 V, f = 1 MHz

Output Capacitance

Reverse Transfer Capacitance

V_DS= −6 V, V_GS= −5 V, I_D= −1 A

Total Gate Charge

Q_g

V_DS= −6 V, V_GS= −4.5 V, I_D= −1 A

Gate-Source Charge

Gate-Drain Charge

Q_gs

Q_gd

7.3

5.9

7.3

5.9

Notes

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.

b. Guaranteed by design, not subject to production testing.

www.vishay.com

Document Number: 74135

S-52282Rev. A, 31-Oct-05

SPICE Device Model Si8417DB

Vishay Siliconix

COMPARISON OF MODEL WITH MEASURED DATA (T_J=25°C UNLESS OTHERWISE NOTED)

www.vishay.com

Document Number: 74135

S-52282Rev. A, 31-Oct-05

相关型号：

SI8417DB-T2-E1

Small Signal Field-Effect Transistor, 0.0097A I(D), 12V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, 2.40 X 2 MM, ROHS COMPLIANT, ULTRA SMALL, MICRO FOOT, 4 PIN

VISHAY