SI8424DB-T1-E1 [VISHAY]
N-Channel 1.2-V (G-S) MOSFET; N沟道1.2 -V （G -S ）的MOSFET
| 型号： | SI8424DB-T1-E1 |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 1.2-V (G-S) MOSFET |
| 文件： | 总11页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8424DB
Vishay Siliconix
N-Channel 1.2-V (G-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
•
•
TrenchFET® Power MOSFET
I
D (A)a
12.2
11.6
11.2
10.2
1.3
VDS (V)
RDS(on) (Ω)
Qg (Typ.)
Industry First 1.2 V Rated MOSFET
Ultra Small MICRO FOOT® Chipscale
0.031 at VGS = 4.5 V
0.033 at VGS = 2.5 V
0.035 at VGS = 1.8 V
0.043 at VGS = 1.5 V
0.077 at VGS = 1.2 V
RoHS
COMPLIANT
Packaging Reduces Footprint Area, Profile
(0.62 mm) and On-Resistance Per Footprint Area
8
20 nC
APPLICATIONS
•
Low Threshold Load Switch for Portable Devices
- Low Power Consumption
- Increased Battery Life
• Ultra Low Voltage Load Switch
D
MICRO FOOT
Bump Side View
Backside View
3
4
2
D
S
D
G
G
8424
XXX
Device Marking: 8424
xxx = Date/Lot Traceability Code
S
Ordering Information: Si8424DB-T1-E1 (Lead (Pb)-free)
1
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
Limit
8
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
V
VGS
5
T
C = 25 °C
12.2
9.8
TC = 70 °C
TA = 25 °C
TA = 70 °C
Continuous Drain Current (TJ = 150 °C)
ID
8.1b,c
6.5b,c
20
A
IDM
IS
Pulsed Drain Current
TC = 25 °C
TA = 25 °C
TC = 25 °C
5.2
Continuous Source-Drain Diode Current
2.3b,c
6.25
4
TC = 70 °C
PD
Maximum Power Dissipation
W
2.78b,c
1.78b,c
TA = 25 °C
TA = 70 °C
TJ, Tstg
- 55 to 150
260
Operating Junction and Storage Temperature Range
Package Reflow Conditionsd
°C
IR/Convection
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering.
e. In this document, any reference to the Case represents the body of the MICRO FOOT device and Foot is the bump.
Document Number: 74400
S-82119-Rev. B, 08-Sep-08
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1
Si8424DB
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta,b
Symbol
Typical
35
Maximum
Unit
RthJA
45
20
°C/W
RthJF
Maximum Junction-to-Foot (Drain)
Steady State
16
Notes
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 72 °C/W.
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS
VGS = 0 V, ID = 250 µA
ID = 250 µA
8
V
V
V
DS Temperature Coefficient
ΔVDS/TJ
ΔVGS(th)/TJ
8.9
mV/°C
GS(th) Temperature Coefficient
- 2.5
0.35
1.0
VGS(th)
IGSS
VDS = VGS, ID = 250 µA
Gate-Source Threshold Voltage
Gate-Source Leakage
V
VDS = 0 V, VGS = 5 V
VDS = 8 V, VGS = 0 V
100
1
nA
IDSS
Zero Gate Voltage Drain Current
On-State Drain Currenta
µA
A
V
DS = 8 V, VGS = 0 V , TJ = 70 °C
VDS ≤ 5 V, VGS = 4.5 V
VGS = 4.5 V, ID = 1 A
10
ID(on)
20
0.025
0.027
0.029
0.032
0.049
8.3
0.031
0.033
0.035
0.043
0.077
13
V
V
V
V
GS = 2.5 V, ID = 1 A
GS = 1.8 V, ID = 1 A
GS = 1.5 V, ID = 1 A
GS = 1.2 V, ID = 1 A
Drain-Source On-State
Resistancea
RDS(on)
Ω
Forward Transconductancea
gfs
VDS = 4 V, ID = 1 A
S
Dynamicb
Input Capacitance
Ciss
Coss
Crss
1950
610
350
22
Output Capacitance
VDS = 4 V, VGS = 0 V, f = 1 MHz
pF
Reverse Transfer Capacitance
V
DS = 4 V, VGS = 5 V, ID = 1 A
33
30
Qg
Total Gate Charge
20
nC
Ω
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Qgs
Qgd
Rg
3.5
VDS = 4 V, VGS = 4.5 V, ID = 1 A
VGS = 0.1 V, f = 1 MHz
1.8
13
8
td(on)
tr
td(off)
tf
12
18
12
110
40
VDD = 4 V, RL = 4 Ω
ID ≅ 1 A, VGEN = – 4.5 V, Rg = 1 Ω
ns
Turn-Off Delay Time
Fall Time
165
60
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Document Number: 74400
S-82119-Rev. B, 08-Sep-08
Si8424DB
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
ISM
VSD
trr
TC = 25 °C
6.25
20
A
Pulse Diode Forward Current
Body Diode Voltage
IS = 1 A, VGS = 0 V
0.6
104
88
1.2
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
156
132
ns
nC
Qrr
ta
IF = – 1 A, dI/dt = 100 A/µs, TJ = 25 °C
26
ns
tb
78
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS T = 25 °C, unless otherwise noted
A
20
15
10
5
20
15
10
5
V
= 5 thru 1.5 V
GS
T
C
= 125 °C
T
C
= 25 °C
V
= 1 V
GS
T
= - 55 °C
1.5
C
0
0.0
0
0.0
0.3
0.6
0.9
1.2
1.8
0.5
1.0
1.5
2.0
V
GS
- Gate-to-Source Voltage (V)
V
DS
- Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
Document Number: 74400
S-82119-Rev. B, 08-Sep-08
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3
Si8424DB
Vishay Siliconix
TYPICAL CHARACTERISTICS T = 25 °C, unless otherwise noted
A
0.12
3000
2400
0.09
C
iss
V
GS
= 1.2 V
1800
1200
600
0
0.06
0.03
0.00
V
= 1.5 V
GS
V
= 1.8 V
GS
V
GS
= 2.5 V
C
oss
C
rss
V
GS
= 4.5 V
0
5
10
15
20
0
2
4
6
8
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
RDS(on) vs. Drain Current
Capacitance
1.5
1.3
1.1
0.9
0.7
5
4
3
2
1
0
I
D
= 1 A
I
D
= 1 A
V
DS
= 4 V
V
GS
= 4.5 V, 2.5 V, 1.8 V
V
DS
= 6.4 V
V
GS
= 1.5 V
- 50 - 25
0
25
50
75
100 125 150
0
5
10
15
20
25
T - Junction Temperature (°C)
J
Q
g
- Total Gate Charge (nC)
Gate Charge
On-Resistance vs. Junction Temperature
10.00
0.050
0.045
0.040
0.035
0.030
0.025
0.020
I
D
= 1 A
T
A
= 150 °C
1.00
0.10
0.01
T
A
= 125 °C
T
A
= 25 °C
T
A
= 25 °C
2
0.0
0.2
0.4
0.6
0.8
1.0
0
1
3
4
5
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Forward Diode Voltage vs Temp
RDS(on) vs VGS vs Temperature
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Document Number: 74400
S-82119-Rev. B, 08-Sep-08
Si8424DB
Vishay Siliconix
TYPICAL CHARACTERISTICS T = 25 °C, unless otherwise noted
A
0.8
0.7
0.6
0.5
0.4
0.3
0.2
80
60
I
D
= 250 µA
40
20
0
- 50 - 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
T
J
- Temperature (°C)
Time (s)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
14
12
10
8
8
7
6
5
4
3
2
1
0
6
4
2
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
F
- Foot Temperature (°C)
Case Temperature (°C)
Current Derating**
Power Derating
100
10
Limited by R
DS(on)*
P(t) = 100 ms
P(t) = 1s
P(t) = 10s
1
DC
0.1
T
= 25 °C
A
0.01
Single Pulse
** The power dissipation PD is based on TJ(max) = 150 °C,
using junction-to-foot thermal resistance, and is more useful
in settling the upper dissipation limit for cases where
additional heatsinking is used. It is used to determine the
current rating, when this rating falls below the package limit.
0.001
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V
> minimum V
at which R
is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Ambient
Document Number: 74400
S-82119-Rev. B, 08-Sep-08
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Si8424DB
Vishay Siliconix
TYPICAL CHARACTERISTICS T = 25 °C, unless otherwise noted
A
2
1
Duty Cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
0.05
t
1
t
2
t
t
1
1. Duty Cycle, D =
0.02
2
2. Per Unit Base = R
=72 °C/W
thJ A
(t)
3. T - T
=
P
Z
JM
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
10
1
10
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Document Number: 74400
S-82119-Rev. B, 08-Sep-08
Si8424DB
Vishay Siliconix
PACKAGE OUTLINE
MICRO FOOT: 4-BUMP (2 x 2, 0.8-mm PITCH)
4 x ∅ 0.30 ~ 0.31
Note 3
Solder Mask ∅ ~ 0.40
e
A
2
Silicon
A
A
1
Bump Note 2
b Diameter
e
S
e
Recommended Land
E
8424
XXX
e
S
D
Mark on Backside of Die
Notes (Unless Otherwise Specified):
1. Laser mark on the silicon die back, coated with a thin metal.
2. Bumps are Sn/Ag/Cu.
3. Non-solder mask defined copper landing pad.
4. The flat side of wafers is oriented at the bottom.
Millimetersa
Inches
Max.
Dim.
Min.
0.600
0.260
Max.
0.650
0.290
Min.
A
0.0236
0.0102
0.0256
0.0114
A1
A2
0.340
0.370
1.520
1.520
0.750
0.370
0.360
0.410
1.600
1.600
0.850
0.380
0.0134
0.0146
0.0598
0.0598
0.0295
0.0146
0.0142
0.0161
0.0630
0.0630
0.0335
0.0150
b
D
E
e
S
Notes:
a. Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?74400.
Document Number: 74400
S-82119-Rev. B, 08-Sep-08
www.vishay.com
7
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
Si8900EDB
3
2
1
0.18 ~ 0.25
A
B
1.08
0.5
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
0.285
0.5
0.285
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
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AN824
Vishay Siliconix
TABLE 1
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
Bump Pitch*
Bump Diameter*
Bump Height*
MICRO FOOT CSP MOSFET
0.8
0.5
0.5
0.37-0.41
0.18-0.25
0.32-0.34
0.26-0.29
0.14-0.19
0.21-0.24
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
TABLE 2
MICRO FOOT Reliability Results
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Test Condition C: −65_ to 150_C
Test condition B: −40_ to 125_C
121_C @ 15PSI 100% Humidity Test
>500 Cycles
>1000 Cycles
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Solder Mask
Copper
FIGURE 3. SMD
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
www.vishay.com
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AN824
Vishay Siliconix
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
Solder Mask
Opening
Stencil
Aperture
Pitch Copper Pad
0.33 " 0.01 mm
Thermal Profile
0.80 mm 0.30 " 0.01 mm 0.41 " 0.01 mm
0.50 mm 0.17 " 0.01 mm 0.27 " 0.01 mm
in ciircle aperture
250
0.30 " 0.01 mm
in square aperture
200
150
100
50
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Stencil Design
IIncoming Tape and Reel Inspection
Solder Paste Printing
Chip Placement
0
0
100
200
300
400
Time (Seconds
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
FIGURE 5. SMT Assembly Process Flow
1. Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
2. Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3. Resurface the pads using a temperature-controlled
soldering iron.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
4. Apply gel flux to the pad.
5. Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
6. Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
www.vishay.com
3
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Disclaimer
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provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
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Document Number: 91000
Revision: 11-Mar-11
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