SI8902EDB-T2-E1 概述
Bi-Directional N-Channel 20-V (D-S) MOSFET 双向N通道20 -V (D -S )的MOSFET 小信号场效应晶体管
SI8902EDB-T2-E1 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Obsolete | 零件包装代码: | CSP |
包装说明: | GRID ARRAY, R-XBGA-B6 | 针数: | 6 |
Reach Compliance Code: | unknown | ECCN代码: | EAR99 |
风险等级: | 5.23 | Is Samacsys: | N |
其他特性: | ESD PROTECTED, ULTRA-LOW RESISTANCE | 配置: | COMMON DRAIN, 2 ELEMENTS WITH BUILT-IN DIODE AND RESISTOR |
最小漏源击穿电压: | 20 V | 最大漏极电流 (ID): | 3.9 A |
最大漏源导通电阻: | 0.072 Ω | FET 技术: | METAL-OXIDE SEMICONDUCTOR |
JESD-30 代码: | R-XBGA-B6 | JESD-609代码: | e1 |
元件数量: | 2 | 端子数量: | 6 |
工作模式: | ENHANCEMENT MODE | 最高工作温度: | 150 °C |
封装主体材料: | UNSPECIFIED | 封装形状: | RECTANGULAR |
封装形式: | GRID ARRAY | 峰值回流温度(摄氏度): | 260 |
极性/信道类型: | N-CHANNEL | 最大功率耗散 (Abs): | 1.7 W |
认证状态: | Not Qualified | 子类别: | FET General Purpose Power |
表面贴装: | YES | 端子面层: | Tin/Silver/Copper (Sn/Ag/Cu) |
端子形式: | BALL | 端子位置: | BOTTOM |
处于峰值回流温度下的最长时间: | 40 | 晶体管应用: | SWITCHING |
晶体管元件材料: | SILICON | Base Number Matches: | 1 |
SI8902EDB-T2-E1 数据手册
通过下载SI8902EDB-T2-E1数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Si8902EDB
Vishay Siliconix
Bi-Directional N-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
•
•
•
•
Halogen-free According to IEC 61249-2-21
VS1S2 (V)
RS1S2(on) (Ω)
IS1S2 (A)
5.0
TrenchFET® Power MOSFET
0.045 at VGS = 4.5 V
0.048 at VGS = 3.7 V
0.057 at VGS = 2.5 V
0.072 at VGS = 1.8 V
Ultra-Low RSS(on)
ESD Protected: 4000 V
MICRO FOOT® Chipscale Packaging
Reduces Footprint Area Profile (0.62 mm) and
On-Resistance Per Footprint Area
4.8
20
4.4
3.9
APPLICATIONS
•
Battery Protection Circuit
- 1-2 Cell Li+/LiP Battery Pack for Portable Devices
S
1
MICRO FOOT
Bump Side View
Backside View
G
G
S2
G2
S1
S2
G1
S1
5
6
4
3
2
1
2
4 kΩ
4 kΩ
Pin 1 Identifier
Device Marking:
8902E = P/N Code
xxx = Date/Lot Traceability Code
Ordering Information:
1
Si8902EDB-T2-E1 (Lead (Pb)-free and Halogen-free)
N-Channel
S
2
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
5 s
Steady State
Unit
VS1S2
Source1- Source2 Voltage
Gate-Source Voltage
20
40
V
VGS
IS1S2
ISM
12
TA = 25 °C
TA = 85 °C
5.0
3.4
3.9
2.8
Continuous Source1- Source2 Current (TJ = 150 °C)a
Pulsed Source1- Source2 Current
A
TA = 25 °C
TA = 85 °C
1.7
0.8
1
Maximum Power Dissipationa
PD
W
0.5
TJ, Tstg
Operating Junction and Storage Temperature Range
Package Reflow Conditionsc
- 55 to 150
260
°C
IR/Convection
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
60
Maximum
Unit
t ≤ 5 s
75
120
22
Maximum Junction-to-Ambienta
Maximum Junction-to-Footb
RthJA
Steady State
Steady State
95
°C/W
RthJF
18
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. The foot is defined as the top surface of the package.
c. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering.
Document Number: 71862
S-83049-Rev. I, 22-Dec-08
www.vishay.com
1
Si8902EDB
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
IGSS
VSS = VGS, ID = 980 µA
Gate Threshold Voltage
0.45
1.0
4
V
VSS = 0 V, VGS
SS = 0 V, VGS
=
=
4.5 V
12 V
µA
mA
Gate-Body Leakage
V
10
1
VSS = 20 V, VGS = 0 V
SS = 20 V, VGS = 0 V, TJ = 85 °C
VSS = 5 V, VGS = 4.5 V
IS1S2
IS(on)
Zero Gate Voltage Source Current
On-State Source Currenta
µA
A
V
5
5
VGS = 4.5 V, ISS = 1 A
0.038
0.041
0.048
0.060
20
0.045
0.048
0.057
0.072
V
GS = 3.7 V, ISS = 1 A
VGS = 2.5 V, ISS = 1 A
GS = 1.8 V, ISS = 1 A
Source1-Source2 On State Resistancea
Forward Transconductancea
RS1S2(on)
Ω
V
gfs
VSS = 10 V, ISS = 1 A
S
Dynamicb
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
1
3
1.5
4.5
26
VSS = 10 V, RL = 10 Ω
ISS ≅ 1 A, VGEN = 4.5 V, Rg = 6 Ω
µs
Turn-Off Delay Time
Fall Time
17
10
15
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10 000
20
I
at 25 °C (mA)
GSS
1000
100
16
12
8
T
= 150 °C
J
10
1
T
= 25 °C
J
4
0.1
0.01
0
0
3
6
9
12
15
0
3
6
9
12
- Gate-to-Source Voltage (V)
GS
15
V
V
GS
- Gate-to-Source Voltage (V)
Gate-Current vs. Gate-Source Voltage
Gate Current vs. Gate-Source Voltage
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2
Document Number: 71862
S-83049-Rev. I, 22-Dec-08
Si8902EDB
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
10
8
V
GS
= 5 thru 1.5 V
8
6
4
2
0
6
4
T
= 125 °C
C
2
25 °C
1 V
- 55 °C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.2
0.4
V - Gate-to-Source Voltage (V)
GS
0.6
0.8
1.0
1.2
1.4
V
DS
- Drain-to-Source Voltage (V)
Transfer Characteristics
Output Characteristics
0.10
1.6
V
S1S2
= 4.5 V
GS
I
= 1 A
0.08
0.06
0.04
0.02
0.00
1.4
1.2
1.0
0.8
0.6
V
GS
= 1.8 V
V
= 2.5 V
= 4.5 V
GS
V
GS
V
GS
= 3.7 V
0
2
4
6
8
10
- 50 - 25
0
25
50
75
100 125 150
T - Junction Temperature (°C)
J
I
D
- Drain Current (A)
On-Resistance vs. Drain Current
On-Resistance vs. Junction Temperature
0.2
0.1
0.10
0.08
0.06
0.04
0.02
0.00
I
= 5 A
S1S2
I
= 980 µA
S1S2
I
= 1 A
S1S2
0.0
- 0.1
- 0.2
- 0.3
- 0.4
- 50 - 25
0
25
50
75
100 125 150
0
1
2
3
4
5
T
- Temperature (°C)
V
GS
- Gate-to-Source Voltage (V)
J
Threshold Voltage
On-Resistance vs. Gate-to-Source Voltage
Document Number: 71862
S-83049-Rev. I, 22-Dec-08
www.vishay.com
3
Si8902EDB
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
I
Limited
30
25
DM
Limited by R
DS(on) *
0.0001 s
10
1
0.001 s
0.01 s
20
15
10
I
D(on)
Limited
0.1 s
1 s
10 s
DC
0.1
T
= 25 °C
A
Single Pulse
5
0
BVDSS Limited
0.01
0.1
1
10
100
100
0.01
0.1
1
10
1000
V
DS
- Drain-to-Source Voltage (V)
* V > minimum V
GS
at which R
is specified
Time (s)
GS
DS(on)
Single Pulse Power, Junction-to-Ambient
Safe Operating Area
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
P
DM
0.1
0.05
t
1
t
2
t
t
1
2
0.02
1. Duty Cycle, D =
2. PER UNIT BASE = RTHJA = 95 °C/W
(t)
3. TJM - T = P
4. Surface Mounted
Z
A
DM thJA
Single Pulse
0.01
-4
10
-3
10
-2
10
-1
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
10
-3
10
-2
-1
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
1
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4
Document Number: 71862
S-83049-Rev. I, 22-Dec-08
Si8902EDB
Vishay Siliconix
PACKAGE OUTLINE
MICRO FOOT: 6 BUMP (2 x 3, 0.8 mm PITCH)
6 x 0.30
Note 3
Solder Mask - 0.4
0.31
Note 2
A
A
2
A
e
1
b Diameter
Bump Note 1
e
e
Recommended Land
8902E
D
e
s
XXX
Mark on Backside of Die
s
e
e
E
Notes (Unless Otherwise Specified):
1. 6 solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ag/Ni/Ti layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
Millimetersa
Inches
Dim.
Min.
Max.
0.650
0.290
Min.
Max.
0.0256
0.114
A
0.600
0.260
0.0236
0.102
A1
A2
0.33
0.360
0.410
1.600
2.400
0.850
0.400
0.0134
0.0146
0.0598
0.0913
0.0295
0.0150
0.0142
0.0161
0.0630
0.0945
0.0335
0.0157
b
D
E
e
0.370
1.520
2.320
0.750
0.380
s
Notes:
a. Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71862.
Document Number: 71862
S-83049-Rev. I, 22-Dec-08
www.vishay.com
5
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
Si8900EDB
3
2
1
0.18 ~ 0.25
A
B
1.08
0.5
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
0.285
0.5
0.285
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
www.vishay.com
1
AN824
Vishay Siliconix
TABLE 1
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
Bump Pitch*
Bump Diameter*
Bump Height*
MICRO FOOT CSP MOSFET
0.8
0.5
0.5
0.37-0.41
0.18-0.25
0.32-0.34
0.26-0.29
0.14-0.19
0.21-0.24
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
TABLE 2
MICRO FOOT Reliability Results
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Test Condition C: −65_ to 150_C
Test condition B: −40_ to 125_C
121_C @ 15PSI 100% Humidity Test
>500 Cycles
>1000 Cycles
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Solder Mask
Copper
FIGURE 3. SMD
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
www.vishay.com
2
AN824
Vishay Siliconix
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
Solder Mask
Opening
Stencil
Aperture
Pitch Copper Pad
0.33 " 0.01 mm
Thermal Profile
0.80 mm 0.30 " 0.01 mm 0.41 " 0.01 mm
0.50 mm 0.17 " 0.01 mm 0.27 " 0.01 mm
in ciircle aperture
250
0.30 " 0.01 mm
in square aperture
200
150
100
50
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Stencil Design
IIncoming Tape and Reel Inspection
Solder Paste Printing
Chip Placement
0
0
100
200
300
400
Time (Seconds
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
FIGURE 5. SMT Assembly Process Flow
1. Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
2. Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3. Resurface the pads using a temperature-controlled
soldering iron.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
4. Apply gel flux to the pad.
5. Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
6. Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
www.vishay.com
3
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 11-Mar-11
www.vishay.com
1
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