SI9102DN02-E3 [VISHAY]
3-W High-Voltage Switchmode Regulator; 3 -W的高电压开关模式稳压器
| 型号： | SI9102DN02-E3 |
| 厂家： | 
VISHAY |
| 描述： | 3-W High-Voltage Switchmode Regulator |
| 文件： | 总10页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9102
Vishay Siliconix
3-W High-Voltage Switchmode Regulator
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
10 to 120 V Input Range
The Si9102 high-voltage switchmode regulator is a mono-
lithic BiC/DMOS integrated circuit which contains most of the
components necessary to implement a high-efficiency dc-to-
dc converter up to 3 watts. It can either be operated from
a low-voltage dc supply, or directly from a 10 to 120 V un-
regulated dc power source.
Current-Mode Control
On-chip 200 V, 7 Ω MOSFET Switch
SHUTDOWN and RESET
High Efficiency Operation (> 80 %)
Internal Start-Up Circuit
This device may be used with an appropriate transformer to
implement most single-ended isolated power converter
topologies (i.e., flyback and forward).
Internal Oscillator (1 MHz)
The Si9102 is available in both standard and lead (Pb)-free
14-pin plastic DIP and 20-pin PLCC packages which are
specified to operate over the industrial temperature range of
- 40 °C to 85 °C.
FUNCTIONAL BLOCK DIAGRAM
OSC OSC
IN OUT
FB
14 (20)
COMP
13 (18)
DISCHARGE
9 (12)
8 (11)
7 (10)
Error
Amplifier
OSC
-
10 (14)
1
Clock ( /
f
)
2
OSC
+
V
REF
2 V
Current-Mode
Comparator
-
4 V (1 %)
R
S
+
Q
Ref
Gen
3 (5)
5 (8)
+
-
DRAIN
C/L
Comparator
- V
IN
(BODY)
1.2 V
1 (2)
Current
Sources
To
Internal
Circuits
BIAS
4 (7)
SOURCE
V
CC
6 (9)
2 (3)
V
CC
Undervoltage
Comparator
11 (16)
12 (17)
SHUTDOWN
RESET
S
R
+V
-
IN
Q
+
8.8 V
-
+
9.4 V
Note: Figures in parenthesis represent pin numbers for 20-pin package.
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
www.vishay.com
1
Si9102
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Unit
Voltages Referenced to - VIN (VCC < + VIN + 0.3 V)
VCC
+VIN
VDS
15
120
V
200
I
I
D (Peak) (Note: 300 µs pulse, 2 % duty cycle)
D (rms)
2
A
250
mA
Logic Inputs (RESET, SHUTDOWN, OSC IN)
Linear Inputs (FEEDBACK, SOURCE)
HV Pre-Regulator Input Current (continuous)
Storage Temperature
- 0.3 V to VCC + 0.3 V
V
- 0.3 to 7
3
mA
- 65 to 125
- 40 to 85
150
Operating Temperature
°C
Junction Temperature (TJ)
14-Pin Plastic DIP (J Suffix)b
20-Pin PLCC (N Suffix)c
750
Power Dissipation (Package)a
mW
1400
14-Pin Plastic DIP
167
Thermal Impedance (ΘJA
Notes:
)
°C/W
20-Pin PLCC
90
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 6 mW/°C above 25 °C.
c. Derate 11.2 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Limit
Unit
Voltages Referenced to - VIN
VCC
9.5 to 13.5
25 kΩ to 1 MΩ
0 to 7
V
ROSC
Linear Inputs
+ VIN
V
V
10 to 120
fOSC
40 kHz to 1 MHz
0 to VCC
Digital Inputs
a
SPECIFICATIONS
Test Conditions
Limits
D Suffix - 40 to 85 °C
Unless Otherwise Specified
DISCHARGE = - VIN = 0 V
VCC = 10 V, + VIN = 48 V
RBIAS = 390 kΩ, ROSC = 330 kΩ
Parameter
Reference
Symbol
Tempb
Mind
Typc
Maxd
Unit
OSC IN = - VIN (OSC Disabled)
Room
Full
3.92
3.86
4.0
4.08
4.14
Output Voltage
VR
V
RL = 10 MΩ
Output Impedancee
Short Circuit Current
Temperature Stabilitye
Oscillator
ZOUT
ISREF
TREF
Room
Room
Full
15
70
30
100
0.5
45
130
1.0
kΩ
µA
VREF = - VIN
mV/°C
Maximum Frequencye
fMAX
fOSC
ROSC = 0
ROSC = 330 kΩg
ROSC = 150 kΩg
Room
Room
Room
Room
Full
1
3
MHz
kHz
80
100
200
10
120
240
15
Initial Accuracy
160
Voltage Stability
Temperature Coefficiente
Δf/f
Δf/f = f(13.5 V) - f(9.5 V)/f(9.5 V)
%
TOSC
200
500
ppm/°C
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2
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
Si9102
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Limits
D Suffix - 40 to 85 °C
Unless Otherwise Specified
DISCHARGE = - VIN = 0 V
V
CC = 10 V, + VIN = 48 V
Parameter
Symbol
Tempb
Mind
Typc
Maxd
Unit
RBIAS = 390 kΩ, ROSC = 330 kΩ
Error Amplifier
FB Tied to COMP
Feedback Input Voltage
VFB
Room
3.96
4.00
4.04
500
V
OSC IN = - VIN (OSC Disabled)
Input BIAS Current
IFB
AVOL
BW
Room
Room
Room
Room
Room
Room
Room
Room
25
80
nA
dB
Open Loop Voltage Gaine
Unity Gain Bandwidthe
Dynamic Output Impedancee
60
OSC IN = - VIN, VFB = 4 V,
OSC IN = - VIN (OSC Disabled)
0.7
1
MHz
Ω
ZOUT
IOUT
VOS
1000
- 2.0
15
2000
- 1.4
40
Source (VFB = 3.4 V)
OSC IN = - VIN (OSC Disabled)
Sink (VFB = 4.5 V)
Output Current
mA
mV
mA
dB
Input OFFSET Voltage
Output Current
IOUT
PSRR
0.12
50
0.15
70
9.5 V ≤ VCC ≤ 13.5 V
Power Supply Rejection
Current Limit
RL = 100 Ω from DRAIN to VCC
VSOURCE
td
Threshold Voltage
Delay to Outpute
Room
Room
1.0
1.2
1.4
V
VFB = 0 V
RL = 100 Ω from DRAIN to VCC
VSOURCE = 1.5 V, See Figure 1
100
200
ns
Pre-Regulator/Start-Up
Input Voltage
+ VIN
+ IIN
IIN = 10 µA
VCC ≥ 10 V
Room
Room
Room
120
10
V
Input Leakage Current
Pre-Regulator Start-Up Current
µA
mA
ISTART
Pulse Width ≤ 300 µs, VCC = 7 V
8
15
V
CC Pre-Regulator Turn-Off
VREG
IPRE-REGULATOR = 10 µA
Room
7.8
9.4
9.7
9.2
Threshold Voltage
RL = 100 Ω from DRAIN to VCC
V
VUVLO
VDELTA
Undervoltage Lockout
Room
Room
7.0
0.3
8.8
0.6
See Detailed Description
VREG, - VUVLO
Supply
ICC
Supply Current
Bias Current
Room
Room
0.45
10
0.6
15
1.0
20
mA
µA
IBIAS
Logic
SHUTDOWN Delaye
SHUTDOWN Pulse Widthe
RESET Pulse Widthe
Latching Pulse Widthe
SHUTDOWN and RESET Low
tSD
tSW
tRW
Room
Room
Room
50
100
VSOURCE = - VIN, See Figure 2
See Figure 3
50
50
ns
tLW
Room
25
Input Low Voltage
VIL
VIH
IIH
Room
Room
Room
Room
2.0
5
V
Input High Voltage
8.0
- 35
200
VIN = 10 V
VIN = 0 V
Input Current Input Voltage High
Input Current Input Voltage Low
MOSFET Switch
1
µA
IIL
- 25
IDRAIN = 100 µA
IDRAIN = 100 mA
VDRAIN = 100 V
Breakdown Voltage
VBR(DSS)
rDS(on)
IDSS
Full
220
V
Ω
Drain-Source On Resistancef
Drain Off Leakage Current
Drain Capacitance
Room
Room
Room
7
5
10
µA
pF
CDS
35
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. Temperature coefficient of rDS(on) is 0.75 % per °C, typical.
g. CSTRAY Pin 8 = ≤ 5 pF.
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
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3
Si9102
Vishay Siliconix
TIMING WAVEFORMS
V
CC
1.5 V
SOURCE
-
-
t
f
≤ 10 ns
t
r
≤ 10 ns
SHUTDOWN
0 -
50 %
50 %
0
t
t
d
V
CC
SD
V
-
CC
DRAIN
0
DRAIN
0
10 %
10 %
Figure 2.
Figure 1.
t
SW
V
CC
t , t ≤ 10 ns
r
f
SHUTDOWN
50 %
50 %
-
0
t
LW
V
CC
50 %
50 %
RESET
50 %
-
0
t
RW
Figure 3.
TYPICAL CHARACTERISTICS
1 M
140
V
CC
= - V
IN
120
100
80
60
40
20
0
100 k
10 k
10 k
100 k
1 M
10
15
20
r
- Oscillator Resistance (Ω)
+I (mA)
IN
OSC
Figure 4. + VIN vs. + IIN at Start-Up
Figure 5. Output Switching Frequency
vs. Oscillator Resistance
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4
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
Si9102
Vishay Siliconix
PIN CONFIGURATIONS
PDIP-14
PIN DESCRIPTION
Pin
Function
1
2
3
4
5
6
7
14
13
12
11
10
9
14-Pin DIP
20-Pin PLCC*
BIAS
+ VIN
1
2
3
4
5
2
3
5
7
8
DRAIN
SOURCE
- VIN
VCC
6
7
9
8
OSC OUT
OSC IN
10
11
12
14
16
17
18
20
8
Top View
DISCHARGE
VREF
9
10
11
12
13
14
PLCC-20
SHUTDOWN
RESET
COMP
3
2
1
20 19
FB
*Pins 1, 4, 6, 13, 15, and 19 = N/C
4
5
6
7
8
18
17
16
15
14
ORDERING INFORMATION
Standard
Lead (Pb)-free
Temperature
Package
Part Number
Part Number
Range
Si9102DJ02
Si9102DN02
Si9102DJ02-E3
Si9102DN02-E3
PDIP-14
9
10 11 12 13
Top View
- 40 to 85 °C
Si9102DN02-T1 Si9102DN02-T1-E3
(With Tape
and Reel)
PLCC-20
(With Tape
and Reel)
DETAIL DESCRIPTION
Pre-Regulator/Start-Up Section
As the supply voltage rises toward the normal operating con-
ditions, an internal undervoltage (UV) lockout circuit keeps
the output MOSFET disabled until VCC exceeds the under-
voltage lockout threshold (typically 8.8 V). This guarantees
that the control logic will be functioning properly and that suf-
ficient gate drive voltage is available before the MOSFET
turns on. The design of the IC is such that the undervoltage
lockout threshold will not exceed the pre-regulator turn-off
voltage. Power dissipation can be minimized by providing an
external power source to VCC such that the constant current
source is always disabled.
Due to the low quiescent current requirement of the Si9102
control circuitry, bias power can be supplied from the unreg-
ulated input power source, from an external regulated low-
voltage supply, or from an auxiliary "bootstrap" winding on
the output inductor or transformer.
When power is first applied during start-up, + VIN will draw a
constant current. The magnitude of this current is determined
by a high-voltage depletion MOSFET device which is con-
nected between + VIN and VCC. This start-up circuitry pro-
vides initial power to the IC by charging an external bypass
capacitance connected to the VCC pin. The constant current
is disabled when VCC exceeds 9.4 V. If VCC is not forced to
exceed the 9.4 V threshold, then VCC will be regulated to a
nominal value of 9.4 V by the pre-regulator circuit.
Note: During start-up or when VCC drops below 9.4 V the
start-up circuit is capable of sourcing up to 20 mA. This may
lead to a high level of power dissipation in the IC (for a 48 V
input, approximately 1 W). Excessive start-up time caused
by external loading of the VCC supply can result in device
damage. Figure 4 gives the typical pre-regulator current at
start-up as a function of input voltage.
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
www.vishay.com
5
Si9102
Vishay Siliconix
DETAIL DESCRIPTION
BIAS
SHUTDOWN and RESET
To properly set the bias for the Si9102, a 390 kΩ resistor
should be tied from BIAS to - VIN. This determines the mag-
nitude of bias current in all of the analog sections and the
pull-up current for the SHUTDOWN and RESET pins. The
current flowing in the bias resistor is nominally 15 µA.
SHUTDOWN and RESET are intended for overriding the
output MOSFET switch via external control logic. The two
inputs are fed through a latch preceding the output switch.
Depending on the logic state of RESET, SHUTDOWN can
be either a latched or unlatched input. The output is off when-
ever SHUTDOWN is low. By simultaneously having SHUT-
DOWN and RESET low, the latch is set and SHUTDOWN
has no effect until RESET goes high. The truth table for these
inputs is given in Table 1.
Reference Section
The reference section of the Si9102 consists of a tempera-
ture compensated buried zener and trimmable divider net-
work. The output of the reference section is connected
internally to the non-inverting input of the error amplifier.
Nominal reference output voltage is 4 V. The trimming proce-
dure that is used on the Si9102 brings the output of the error
amplifier (which is configured for unity gain during trimming)
to within 1 % of 4 V. This automatically compensates for the
input offset voltage in the error amplifier.
Both pins have internal current source pull-ups and should
be left disconnected when not in use. An added feature of the
current sources is the ability to connect a capacitor and an
open-collector driver to the SHUTDOWN or RESET pins to
provide variable shutdown time.
Table 1. Truth Table for the SHUTDOWN and RESET Pins
RESET
Output
Normal Operation
SHUTDOWN
The output impedance of the reference section has been
purposely made high so that a low impedance external volt-
age source can be used to override the internal voltage
source, if desired, without otherwise altering the perfor-
mance of the device.
H
H
L
H
Normal Operation (No Change)
Off (Not Latched)
H
L
L
L
Off (Latched)
Off (Latched, No Change)
Error Amplifier
Output Switch
Closed-loop regulation is provided by the error amplifier,
which is intended for use with "around-the-amplifier" com-
pensation. A MOS differential input stage provides for low
input current. The noninverting input to the error amplifier
(VREF) is internally connected to the output of the reference
supply and should be bypassed with a small capacitor to
ground.
The output switch is a 7 Ω , 200 V lateral DMOS device. Like
discrete MOSFETs, the switch contains an intrinsic body-
drain diode. However, the body contact in the Si9102 is con-
nected internally to - VIN and is independent of the SOURCE.
Oscillator Section
The oscillator consists of a ring of CMOS inverters, capaci-
tors, and a capacitor discharge switch. Frequency is set by
an external resistor between the OSC in and OSC out pins.
(See Figure 5 for details of resistor value vs. frequency.) The
DISCHARGE pin should be tied to - VIN for normal internal
oscillator operation. A frequency divider in the logic section
limits switch duty cycle to ≤ 50 % by locking the switching fre-
quency to one half of the oscillator frequency.
Remote synchronization can be accomplished by capacitive
coupling of a synchronization pulse into the OSC IN terminal.
For a 5 V pulse amplitude and 0.5 µs pulse width, typical val-
ues would be 100 pF in series with 3 kΩ to OSC IN.
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6
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
Si9102
Vishay Siliconix
APPLICATIONS
1N5819
+V
IN
100 µH
+ 5 V
GND
2
3
300 µH
0.1 µF
20 µF
220 µF
GND
1
7
4
5
0.1 µF
47 µF
- 5 V
18 kΩ
14
13
12
11
10
1
2
1N5819
6
240 kΩ
0.022 µF
8
3
4
5
6
7
390 kΩ
Si9102DJ
0.1 µF
9
8
0.1 µF
2 Ω
2
12 kΩ
1N4148
1
/
W
150 kΩ
- V (- 96 V
)
DC
IN
Figure 6. Flyback Converter for Double Battery Telecommunications Power Supplies
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70001.
Document Number: 70001
S-70497-Rev. H, 19-Mar-07
www.vishay.com
7
Package Information
Vishay Siliconix
PLCC: 2O-LEAD (POWER IC ONLY)
D−SQUARE
A
2
MILLIMETERS
INCHES
D −SQUARE
1
Dim
A
A1
A2
B
B1
D
D1
D2
e1
Min
4.20
Max
4.57
3.04
−
Min
Max
0.180
0.120
−
B
1
0.165
0.090
0.020
0.013
0.026
0.385
0.350
0.290
2.29
B
0.51
0.331
0.661
9.78
0.553
0.812
10.03
9.042
8.38
0.021
0.032
0.395
0.356
0.330
e
1
D
2
8.890
7.37
1.27 BSC
0.050 BSC
ECN: S-40081—Rev. A, 02-Feb-04
DWG: 5917
A
1
A
0.101 mm
0.004″
Document Number: 72812
28-Jan-04
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1
Package Information
Vishay Siliconix
PDIP: 14-LEAD (POWER IC ONLY)
14
1
13
2
12
3
11
4
10
5
9
6
8
7
E
E
1
D
S
1
Q
A
A
1
L
15°
MAX
C
e
1
B
B
1
e
A
MILLIMETERS
INCHES
Min
Dim
A
A1
B
B1
C
D
Min
3.81
0.38
0.38
0.89
0.20
17.27
7.62
5.59
2.29
7.37
2.79
1.27
1.02
Max
5.08
1.27
0.51
1.65
0.30
19.30
8.26
7.11
2.79
7.87
3.81
2.03
2.03
Max
0.200
0.050
0.020
0.065
0.012
0.760
0.325
0.280
0.110
0.310
0.150
0.080
0.080
0.150
0.015
0.015
0.035
0.008
0.680
0.300
0.220
0.090
0.290
0.110
0.050
0.040
E
E1
e1
eA
L
Q1
S
ECN: S-40081—Rev. A, 02-Feb-04
DWG: 5919
Document Number: 72814
28-Jan-04
www.vishay.com
1
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
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damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 11-Mar-11
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1
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