SI9118_11 [VISHAY]
Programmable Duty Cycle Controller; 可编程占空比控制器
| 型号： | SI9118_11 |
| 厂家： | 
VISHAY |
| 描述： | Programmable Duty Cycle Controller |
| 文件： | 总11页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9118, Si9119
Vishay Siliconix
Programmable Duty Cycle Controller
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
10 to 200 V Input Range
Current-Mode Control
Internal Start-Up Circuit
The Si9118/Si9119 are a BiC/DMOS current-mode pulse
width modulation (PWM) controller ICs for high-frequency
dc/dc converters. Single-ended topologies (forward and
flyback) can be implemented at frequencies up to 1 MHz.
The controller operates in constant frequency mode during
the full load and automatically switches to pulse skipping
mode under light load to maintain high efficiency throughout
the full load range. The maximum duty cycle is easily
programmed with a resistor divider for optimum control.
The push-pull output driver provides high-speed switching to
external MOSPOWER devices large enough to supply 50 W
of output power. Shoot-through current for internal push-pull
stage is almost eliminated to minimize quiescent supply
current.
Buffer Slope Compensation Voltage
Soft-Start
2.7 MHz Error Amp
500 mA Output Drive Current
Light Load Frequency Fold-Back
Low Quiescent Current
Programmable Maximum Duty Cycle, with 80 % as
Default
The push-pull output driver provides high-speed switching to
external MOSPOWER devices large enough to supply 50 W
of output power. Shoot-through current for internal push-pull
stage is almost eliminated to minimize quiescent supply
current.
The high-voltage DMOS transistor permits direct operation
from bus voltages of up to 200 V. Other features include a
1.5 % accurate voltage reference, 2.7 MHz bandwidth error
amplifier, standby mode, soft-start and undervoltage lockout
circuits.
The Si9118/Si9119 are available in both standard and lead
(Pb)-free packages.
FUNCTIONAL BLOCK DIAGRAM
LIMIT
MAX
CS
SYNC (Si9119)
5
6
10
11
2
12
13
Error
Amplifier
9
1.0 - 2.0 V
R
C
OSC
PWM
+
–
OSC
8
–
+
4
3
OSC
–
+
NI
Ref
Gen
V
REF
Pulse Skip
EN
4.6 V
+
–
R
S
15
14
100 mV
600 mV
DR
Q
23µA
I
MAX
7
SS/EN
+
–
-V
IN
–V
IN
Substrate
16
1
V
CC
+V
–
+
IN
–
+
8.6 V
9.3 V (V
Undervoltage
Lockout
–
+
)
REG
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Unit
18
Voltage Reference VCC to VIN
200
- 0.3 to Vcc + 0.3
- 0.3 to Vcc + 0.3
5
+VIN ( Note: VCC < + VIN + 0.3 V)
V
Logic Input (SYNC)
Linear Input (FB, ICS, ILIMIT, SS/EN)
HV Pre-Regulator Input Current (continuous)
Storage Temperature
mA
°C
- 65 to 150
- 40 to 85
3.2
Operating Temperature
DMAX
V
150
Junction Temperature (TJ)
°C
Power Dissipation (Package)a
16-Pin SOIC (Y Suffix)b
900
140
mW
Thermal Impedance (JA
)
°C/W
16-Pin SOIC
Notes:
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/°C above 25 °C.
* Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating
may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one
Absolute Maximum rating should be applied at any one time.
RECOMMENDED OPERATING RANGE
Parameter
Limit
Unit
Voltage Reference Vcc to VIN
10 to 16.5
V
+VIN
10 to 200
40 kHz to 1 MHz
56 k to 1 M
47 to 200
fOSC
ROSC
COSC
pF
Linear Inputs
Digital Inputs
0 to Vcc - 4
0 to Vcc
V
V
SPECIFICATIONS
Limits
D Suffix - 40 to 85 °C
Test Conditions
Unless Otherwise Specified
Parameter
Reference
Symbol
Temp.a
Min.
Typ.b
Max.
Unit
- VIN = 0 V, VCC = 10 V
OSC Disabled, TA = 25 °C
Room
Full
3.94
3.88
4.0
4.0
4.06
4.12
VREF
Output Voltage
V
OSC Disabled, Over Voltage and
Temperature Rangesc
VREF = -VIN
ISREF
Short Circuit Current
Load Regulation
- 30
10
- 5
40
mA
mV
VR/IR
IREF = 0 to - 1mA
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
SPECIFICATIONS
Limits
D Suffix - 40 to 85 °C
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Parameter
Oscillator
Symbol
Temp.a
Min.
Typ.b
Max.
Unit
fOSC
ROSC = 374 k COSC = 200 pF
90
100
500
110
550
Initial Accuracyd
kHz
c
ROSC = 70 k COSC = 200 pF
ROSC = 70 k COSC = 200 pF
450
fOSC
Voltage Stabilityc
f/f
1
2
%
f/f = [f(16.5 V) - f(9.5 V)] / f(9.5 V)
ppm/°C
Temperature Coefficientc
- 40 TA 85 °C, fOSC = 100 kHz
OSC TC
200
500
Sync High Pulse Width (Si9119)
Sync Low Pulse Width (Si9119)
Sync Rise/Fall Time (Si9119)
Sync Logic Low (Si9119)
200
200
ns
200
0.8
VIL
V
VIH
Sync Logic High (Si9119)
4
fEXT
Sync Rangec (Si9119)
PWM/PSM
1.05 x fOSC
kHz
VIH
VIL
PWM/PSM Logic High
PWM/PSM Logic Low
DMAX
4
V
0.8
fOSC = 100 kHz with 1 % Resistor
VFB = 5 V, NI = VREF
Accuracy
10
%
Error Amplifier (OSC Disabled)
Input BIAS Current
IFB
< 1.0
5
200
25
nA
mV
VOS2
AVOL
BW
Input OFFSET Voltage
Open Loop Voltage Gainc
Unity Gain Bandwidthc
dB
65
1.8
- 1.0
1.0
50
80
2.7
- 2.7
2.4
80
MHz
Source (VFB = 3.5 V, NI = VREF
)
IOUT
Output Current
mA
dB
Sink (VFB = 4.5 V, NI = VREF
)
10 V VCC 16.5 V
Power Supply Rejection
PSRR
Pre-Regulator/Start-up
Input Voltagec
+VIN
+IIN
IIN = 10 µA
VCC 10 V
Room
Room
Room
200
V
Input Leakage Current
Pre-Regulator Start-Up Current
10
µA
mA
ISTART
Pulse Width 300 µs, VCC = VULVO
8
15
VCC Pre-Regulator Turn-Off
Threshold Voltage
VREG
IPRE_REGULATOR = 15 µA
Room
8.7
9.3
9.8
9.3
V
VUVLO
VDELTA
Undervoltage Lockout
VREG - VUVLO
Room
Room
8.0
0.3
8.6
0.7
Supply
ICC
CLOAD 50 pF, fOSC = 100 kHZ
Supply Current
1.9
3.0
mA
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
SPECIFICATIONS
Limits
D Suffix - 40 to 85 °C
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Parameter
Protection
Symbol
Temp.a
Min.
Typ.b
Max.
Unit
VI(Limit)
VFB = 0, NI = VREF
Current Limit Treshold Voltage
0.5
0.6
77
0.7
100
- 30
V
ns
µA
V
Current Limit Delay to Outputc
Soft-Start Current
td
VSENSE 0.85 V, See Figure 1
ISS
- 12
0.5
- 23
1.26
VSS(off)
VPS
Output Inhibit Voltage
Soft-Start Voltage to Disable Driver Output
Pulse Skipping Threshold
Voltage
80
100
120
mV
Mosfet Driver
V
CC - 0.3
Room
Full
VOH
VOL
IOUT = - 10 mA
Output High Voltage
VCC - 0.5
V
Room
Full
0.3
0.5
30
IOUT = 10 mA
Output Low Voltage
Room
Full
20
25
Output Resistancec
Rise Timec
ROUT
IOUT = 10 mA, Source or Sink
50
tr
tr
Room
Room
40
40
75
75
CL = 500 pF
ns
Fall Timec
Notes:
a. Room = 25 °C, Full = as determined by the operating temperature suffix.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. Guaranteed by design, not subject to production test.
d. CSTRAY 5 pF on COSC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TIMING WAVEFORMS
t
r
10 ns
0.85
Current
Sense
50 %
0
t
d
Output
V
CC
90 %
0
Figure 1.
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
TYPICAL CHARACTERISTICS (T = 25 °C, unless noted)
A
200
150
100
50
2 x 1000
47 pF
t for C = 2500 pF
r
L
100 pF
150 pF
200 pF
t for C = 2500 pF
f
L
2 x 100
t for C = 1000 pF
r
L
Note: These curves were measured
in a board with 3.5 pF of
external parasitic
t for C = 1000 pF
f L
t 10 % to 90 %
f
r
capacitance.
t 90 % to 10 %
2 x 10
0
10
100
1000
9
10
11
12
13
14
15
16
17
r
– Oscillator Resistance (k
)
OSC
V
CC
– Supply Voltage (V)
Oscillator Frequency
Output Driver Rise and Fall Time
36
32
28
24
12
9
V
= 12 V
OSC
CC
C
R
C
= 127 k
= 47 pF
= 47 pF
OSC
OSC
fs = 500 kHz
C
L
= 1000 pF
C
L
= 2500 pF
20
6
16
12
C
L
= 1000 pF
8
3
C
L
= 0 pF
C = 0 pF
L
4
0
0
0
200
400
600
800
1000
9
10
11
12
13
14
15
16
17
f
– Output Frequency (kHz)
OUT
V
– Supply Voltage (V)
CC
Supply Current vs. Output Frequency
Supply Current vs. Supply Voltage
1.05
R
OSC
C
OSC
= 56 k
= 100 pF
1.00
0.95
0.90
0.85
8
9
10
11
12
13
14
15
16 17
V
CC
– Supply Voltage (V)
Switching Frequency vs. Supply Voltage
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
PIN CONFIGURATIONS AND ORDERING INFORMATION
+V
V
+V
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
CC
IN
PWM/PSM
PWM/PSM
DR
DR
V
REF
V
REF
-V
-V
IN
IN
NI
FB
NI
FB
D
D
MAX
MAX
SOIC
SOIC
Si9118DY
Si9119DY
V
SC
SYNC
Top View
Top View
COMP
SS/EN
COMP
SS/EN
I
I
I
CS
LIMIT
CS
I
LIMIT
R
R
OSC
C
OSC
C
OSC
OSC
ORDERING INFORMATION
Part Number
Temperature Range
Package
Si9118DY
Si9118DY-T1
Si9118DY-T1-E3
Si9119DY
- 40 to 85 °C
SOIC-16
Si9119DY-T1
Si9119DY-T1-E3
PIN DESCRIPTION
Symbol
Description
Pin Number
+VIN
Input bus voltage ranging from 10 V to 200 V.
1
Connected to VREF forces the converter into PWM mode. Connected to -VIN forces the converter into PSM
mode.
2
PWM/PSM
VREF
4 V reference voltage. Decouple with 0.1 µF ceramic capacitor.
3
4
5
6
7
8
NI
Non-inverting input of an error amplifier.
FB
Inverting input of an error amplifier.
COMP
SS/EN
COSC
Error amplifier output for external compensation network.
Programmable soft-start with external capacitor or externally controlled disable mode.
External capacitor to determine the switching frequency.
ROSC
ILIMIT
External resistor to determine the switching frequency.
9
Pulse by pulse peak current limiting pin. When the current sense voltage exceeds the current limit threshold,
the gate drive signal is terminated. ILIMIT is also used to sense the current in pulse skipping mode.
10
11
12
ICS
Current sense input to control feedback response.
Si9118: slope compensation pin. Si9119: clock synchronization pin. Logic high to low transition from external
signal synchronizes the internal clock frequency.
SYNC or VSC
DMAX
-VIN
DR
Sets the maximum duty cycle. Internally, the maximum duty cycle is clamped to 80 %.
Single point ground.
13
14
15
16
Gate drive for the external MOSFET switch.
VCC
Supply voltage for the IC after the startup transition.
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Si9118, Si9119
Vishay Siliconix
STANDARD APPLICATION CIRCUITS
V
O
+V
IN
V
CC
Si9420DY
PWM/PSM
I
CS
V
REF
DR
NI
-V
IN
FB
D
MAX
TL431
COMP
V
SC
SS/EN
C
OSC
R
OSC
I
LIMIT
- 48 V (- 42 to - 56 V)
Figure 2. Si9118 15 W Forward Converter Schematic
+V
IN
V
CC
Si9420DY
PWM/PSM
I
CS
V
REF
DR
NI
-V
IN
FB
D
MAX
COMP
SS/EN
SYNC
TL431
C
OSC
R
OSC
I
LIMIT
- 48 V (- 42 to - 56 V)
Figure 3. Si9119 Forward Converter With External Slope Compensation
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Si9118, Si9119
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION
Start-Up
response is determined by the feedback compensation
network while the large signal response is determined
by the inductor di/dt slew rate. Besides the inductance
value, the error amplifier gain-bandwidth determine the
converter response time. In order to minimize the
response time, Si9118/Si9119 is designed with a
2.7 MHz error amplifier gain-bandwidth product to
provide the widest converter bandwidth possible.
Si9118/Si9119 are designed with internal depletion
mode MOSFET capable of powering directly from the
high input bus voltage. This feature eliminates the
typical external start-up circuit saving valuable space
and cost. But, most of all, this feature improves the
converter efficiency during full load and has an even
greater impact on light load. With an input bus voltage
applied to the +V pin, the V voltage is regulated to
PWM Mode
The converter operates in PWM mode if the PWM/
IN
CC
9.3 V. The UVLO circuit prevents the controller output
driver section from turning on, until V voltage
PSM pin is connected to V
pin or logic high. As the
REF
load current and line voltage vary, the Si9118/Si9119
maintain constant switching frequency until they reach
minimum duty cycle. Once the output voltage
regulation is exceeded with minimum duty cycle, the
switching frequency will continue to decrease until
regulation is achieved. The switching frequency is
CC
exceeds 8.7 V. In order to maximize converter
efficiency, the designer should provide an external
bootstrap winding to override the internal V
regulator. If external VCC voltage is greater than 9.3 V,
the internal depletion mode MOSFET regulator is
disabled and power is derived from the external V
CC
controlled by the external R
and C
as shown by
CC
osc
osc
supply. The V supply provides power to the internal
the typical oscillator frequency curve. In PWM mode,
output ripple noise is constant reducing EMI concerns
as well as simplifying the filter to minimize the system
noise.
CC
circuity as well as providing supply voltage to the gate
drive circuit.
Soft-Start/Enable
The soft-start time is externally programmable with
capacitor connected to the SS/EN pin. A constant
current source provides the current to the SS/EN pin to
generate a linear start-up time versus the capacitance
value. The SS/EN pin clamps the error amplifier output
voltage, limiting the rate of increase in duty cycle. By
controlling the rate of rise in duty cycle gradually, the
output voltage rises gradually preventing the output
voltage from overshooting. The SS/EN pin can also be
used to enable or disable the output driver section with
an external logic signal.
Pulse Skipping Mode
If the PWM/PSM pin is connected to -V pin (logic
IN
low), the converter can operate in either PWM or PSM
mode depending on the load current. The converter
automatically transitions from PWM to PSM or vise
versa to maintain output voltage regulation. In PSM
mode, the MOSFET switch is turned on until the peak
current sensed voltage reaches 100 mV and the output
voltage meets or exceeds its regulation voltage. The
converter is operating in pulse skipping mode because
each pulse delivers excess energy into the output
capacitor forcing the output voltage to exceed its
regulation voltage. By forcing the output voltage to
exceed the regulation voltage, succeeding pulses are
skipped until the output voltage drops below the
regulation point. Therefore, switching frequency will
continue to reduce during PSM control as the demand
for output current decreases. The pulse skipping mode
cuts down the switching losses, the dominant power
consumed during low output current, thereby
maintaining high efficiency throughout the entire load
range. With PWM/PSM pin in logic low state, the
converter transitions back into PWM mode, if the peak
current sensed voltage of 100 mV does not generate
the required output voltage. In the region between
pulse skipping mode and PWM mode, the controller
may transition between the two modes, delivering
spurts of pulses. This may cause the current waveform
to look irregular, but this will not overly affect the ripple
voltage. Even in this transitional mode, efficiency
remains high.
Synchronization
The synchronization to external clock is easily
accomplished by connecting the external clock into the
SYNC pin (Si9119 only). The logic high to low
transition synchronizes the clock. The external clock
frequency must be at least 5 % faster than the internal
clock frequency.
Reference Voltage
The reference voltage for the Si9118/Si9119 are set at
4.0 V. The reference voltage is not connected to the
non-inverting inputs of the error amplifier, therefore,
the minimum output voltage is not limited to reference
voltage. The V
capacitor.
pin requires a 0.1 µF decoupling
REF
Error Amplifier
The error amplifier gain-bandwidth product is critical
parameter which determines the transient response of
converter. The transient response is function of both
small and large signal responses. The small signal
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION (CONT’D)
Programmable Duty Cycle Control
summation of this signal should be fed into I pin. For
CS
optimum performance, proper slope compensation is
required. The amount of slope compensation is
The maximum duty cycle limit is controlled by the
voltage on D
pin. A D
voltage of 3.2 V
MAX
MAX
determined by the resistors connected to the I pin.
generates
0 % duty cycle. The 80 % duty cycle is maximum
default condition at 1 MHz switching frequency. The
voltage can be easily generated using resistor
80 % duty cycle while 0.0 V generates
CS
The amplitude of the V signal is same as the C
SC
OSC
pin voltage (4 V). For designs which use with SYNC
pin, instead of V pin, the converter can still operate
D
SC
MAX
at duty cycles greater than 50 % by generating an
external slope compensation ramp using a
simple RC circuit from the MOSFET driver output pin
as shown on the application circuit.
divider from the reference voltage.The maximum duty
cycle limitation will be different when the converter is
synchronized by an external frequency. If the internal
free running frequency is much slower than the
external SYNC signal (SYNC signal causes the
internal clock to reset before the Cosc voltage ramps
to 3.2 V) , duty cycle is determined by the one shot
discharge time of the oscillator capacitor (100 ns).
Therefore, with 1 MHz SYNC signal, maximum duty
cycle of 90 % can be achieved (100 ns is 10 % of
1 MHz). If the internal free running frequency is very
close to the external SYNC frequency (SYNC signal
causes the internal clock to reset somewhere between
3.2 V to 4 V), duty cycle is determined by the ratio of
Over Current Protection
Si9118/Si9119 are designed with a pulse-to-pulse
peak
current limiting protection circuit to protect itself, and
the load in case of a failure. The voltage across the
sense resistor is monitored continuously and if the
voltage reaches its trigger level, the duty cycle is
terminated. This limits the maximum current delivered
to the load. In order to improve the accuracy of over
current protection from traditional controllers, Si9118/
C
voltage at the SYNC point and the 3.2 V. At this
osc
condition, the maximum duty cycle can be greater than
90 %. Therefore, D voltage must be modified in
Si9119 are designed with separate I
and I pins.
LIMIT CS
Voltage on the I
pin does not sum in the traditional
MAX
LIMIT
order to maintain desired maximum duty cycle.
slope compensation voltage, which adds error into the
detection level. I pin is used to sum the current
sense signal and the slope compensation for loop
stability.
CS
Slope Compensation
Slope compensation is necessary for duty cycles
greater than 50 % to stabilize the inner current loop
and maintain overall loop stability. In order to simplify
the slope compensation circuitry, the Si9118 provides
Output Driver Stage
The DR pin is designed to drive a low-side N-Channel
MOSFET. The driver stage is sized to sink and source
the buffered oscillator ramp signal, V to be used for
SC
external slope compensation. V
is only available
peak currents up to 500 mA with V
= 12 V. This
SC
CC
when DR is high. The V signal super-imposed with
actual current sense signal should be used by the
PWM comparator to determine the duty cycle. The
provides ample drive capability for 50 W of output
power.
SC
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70815.
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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This document is subject to change without notice.
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Package Information
Vishay Siliconix
SOIC (NARROW): 16-LEAD (POWER IC ONLY)
JEDEC Part Number: MS-012
MILLIMETERS
INCHES
Dim
A
A1
B
C
D
Min
1.35
0.10
0.38
0.18
9.80
3.80
Max
1.75
0.20
0.51
0.23
10.00
4.00
Min
Max
0.069
0.008
0.020
0.009
0.393
0.157
0.053
0.004
0.015
0.007
0.385
0.149
E
16 15
14 13
12 11
10
7
9
8
1.27 BSC
0.050 BSC
e
H
L
Ĭ
5.80
0.50
0_
6.20
0.93
8_
0.228
0.020
0_
0.244
0.037
8_
E
1
2
3
4
5
6
ECN: S-40080—Rev. A, 02-Feb-04
DWG: 5912
H
D
C
All Leads
0.101 mm
0.004 IN
A1
Ĭ
L
e
B
Document Number: 72807
28-Jan-04
www.vishay.com
1
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
www.vishay.com
1
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